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@@ -23,6 +23,7 @@
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#define INVALID_ID 0xffff
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#define GTC_CNTCR_REG 0x0
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+#define GTC_CNTFID0_REG 0x20
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#define GTC_CNTR_EN 0x3
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/**
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@@ -31,6 +32,7 @@
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* @rproc_rst: rproc reset control data
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* @sci: Pointer to TISCI handle
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* @tsp: TISCI processor control helper structure
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+ * @gtc_clk: GTC clock description
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* @gtc_base: Timer base address.
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*/
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struct k3_arm64_privdata {
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@@ -38,6 +40,7 @@ struct k3_arm64_privdata {
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struct power_domain gtc_pwrdmn;
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struct reset_ctl rproc_rst;
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struct ti_sci_proc tsp;
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+ struct clk gtc_clk;
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void *gtc_base;
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};
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@@ -73,6 +76,7 @@ static int k3_arm64_load(struct udevice *dev, ulong addr, ulong size)
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static int k3_arm64_start(struct udevice *dev)
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{
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struct k3_arm64_privdata *rproc = dev_get_priv(dev);
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+ ulong gtc_rate;
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int ret;
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dev_dbg(dev, "%s\n", __func__);
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@@ -83,6 +87,11 @@ static int k3_arm64_start(struct udevice *dev)
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return ret;
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}
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+ gtc_rate = clk_get_rate(&rproc->gtc_clk);
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+ dev_dbg(dev, "GTC RATE= %d\n", (u32) gtc_rate);
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+ /* Store the clock frequency down for GTC users to pick up */
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+ writel((u32)gtc_rate, rproc->gtc_base + GTC_CNTFID0_REG);
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+
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/* Enable the timer before starting remote core */
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writel(GTC_CNTR_EN, rproc->gtc_base + GTC_CNTCR_REG);
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@@ -169,6 +178,12 @@ static int k3_arm64_of_to_priv(struct udevice *dev,
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return ret;
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}
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+ ret = clk_get_by_index(dev, 0, &rproc->gtc_clk);
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+ if (ret) {
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+ dev_err(dev, "clk_get failed: %d\n", ret);
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+ return ret;
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+ }
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+
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ret = reset_get_by_index(dev, 0, &rproc->rproc_rst);
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if (ret) {
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dev_err(dev, "reset_get() failed: %d\n", ret);
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