|
@@ -454,14 +454,6 @@ static int zynq_gem_init(struct udevice *dev)
|
|
|
priv->int_pcs) {
|
|
|
nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
|
|
|
ZYNQ_GEM_NWCFG_PCS_SEL;
|
|
|
-#ifdef CONFIG_ARM64
|
|
|
- if (priv->phydev->phy_id != PHY_FIXED_ID)
|
|
|
- writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
|
|
|
- ®s->pcscntrl);
|
|
|
- else
|
|
|
- writel(readl(®s->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
|
|
|
- ®s->pcscntrl);
|
|
|
-#endif
|
|
|
}
|
|
|
|
|
|
switch (priv->phydev->speed) {
|
|
@@ -480,6 +472,23 @@ static int zynq_gem_init(struct udevice *dev)
|
|
|
break;
|
|
|
}
|
|
|
|
|
|
+#ifdef CONFIG_ARM64
|
|
|
+ if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
|
|
|
+ priv->int_pcs) {
|
|
|
+ /*
|
|
|
+ * Disable AN for fixed link configuration, enable otherwise.
|
|
|
+ * Must be written after PCS_SEL is set in nwconfig,
|
|
|
+ * otherwise writes will not take effect.
|
|
|
+ */
|
|
|
+ if (priv->phydev->phy_id != PHY_FIXED_ID)
|
|
|
+ writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
|
|
|
+ ®s->pcscntrl);
|
|
|
+ else
|
|
|
+ writel(readl(®s->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
|
|
|
+ ®s->pcscntrl);
|
|
|
+ }
|
|
|
+#endif
|
|
|
+
|
|
|
ret = clk_set_rate(&priv->tx_clk, clk_rate);
|
|
|
if (IS_ERR_VALUE(ret)) {
|
|
|
dev_err(dev, "failed to set tx clock rate\n");
|