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@@ -153,6 +153,30 @@ static int gen3_clk_disable(struct clk *clk)
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return renesas_clk_endisable(clk, priv->base, priv->info, false);
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}
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+static u64 gen3_clk_get_rate64(struct clk *clk);
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+
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+static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv,
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+ struct clk *parent,
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+ const struct cpg_core_clk *core,
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+ u32 mul_reg, u32 mult, u32 div,
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+ char *name)
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+{
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+ u32 value;
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+ u64 rate;
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+
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+ if (mul_reg) {
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+ value = readl(priv->base + mul_reg);
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+ mult = (((value >> 24) & 0x7f) + 1) * 2;
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+ div = 1;
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+ }
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+
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+ rate = (gen3_clk_get_rate64(parent) * mult) / div;
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+
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+ debug("%s[%i] %s clk: parent=%i mult=%u div=%u => rate=%llu\n",
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+ __func__, __LINE__, name, core->parent, mult, div, rate);
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+ return rate;
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+}
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+
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static u64 gen3_clk_get_rate64(struct clk *clk)
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{
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struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
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@@ -161,7 +185,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
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const struct cpg_core_clk *core;
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const struct rcar_gen3_cpg_pll_config *pll_config =
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priv->cpg_pll_config;
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- u32 value, mult, div, prediv, postdiv;
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+ u32 value, div, prediv, postdiv;
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u64 rate = 0;
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int i, ret;
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@@ -203,60 +227,36 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
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return -EINVAL;
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case CLK_TYPE_GEN3_MAIN:
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- rate = gen3_clk_get_rate64(&parent) / pll_config->extal_div;
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- debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%llu\n",
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- __func__, __LINE__,
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- core->parent, pll_config->extal_div, rate);
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- return rate;
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+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
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+ 0, 1, pll_config->extal_div,
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+ "MAIN");
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case CLK_TYPE_GEN3_PLL0:
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- value = readl(priv->base + CPG_PLL0CR);
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- mult = (((value >> 24) & 0x7f) + 1) * 2;
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- rate = gen3_clk_get_rate64(&parent) * mult;
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- debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%llu\n",
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- __func__, __LINE__, core->parent, mult, rate);
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- return rate;
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+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
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+ CPG_PLL0CR, 0, 0, "PLL0");
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case CLK_TYPE_GEN3_PLL1:
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- rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult;
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- rate /= pll_config->pll1_div;
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- debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n",
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- __func__, __LINE__,
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- core->parent, pll_config->pll1_mult,
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- pll_config->pll1_div, rate);
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- return rate;
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+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
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+ 0, pll_config->pll1_mult,
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+ pll_config->pll1_div, "PLL1");
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case CLK_TYPE_GEN3_PLL2:
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- value = readl(priv->base + CPG_PLL2CR);
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- mult = (((value >> 24) & 0x7f) + 1) * 2;
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- rate = gen3_clk_get_rate64(&parent) * mult;
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- debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%llu\n",
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- __func__, __LINE__, core->parent, mult, rate);
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- return rate;
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+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
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+ CPG_PLL2CR, 0, 0, "PLL2");
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case CLK_TYPE_GEN3_PLL3:
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- rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult;
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- rate /= pll_config->pll3_div;
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- debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n",
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- __func__, __LINE__,
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- core->parent, pll_config->pll3_mult,
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- pll_config->pll3_div, rate);
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- return rate;
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+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
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+ 0, pll_config->pll3_mult,
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+ pll_config->pll3_div, "PLL3");
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case CLK_TYPE_GEN3_PLL4:
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- value = readl(priv->base + CPG_PLL4CR);
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- mult = (((value >> 24) & 0x7f) + 1) * 2;
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- rate = gen3_clk_get_rate64(&parent) * mult;
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- debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%llu\n",
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- __func__, __LINE__, core->parent, mult, rate);
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- return rate;
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+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
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+ CPG_PLL4CR, 0, 0, "PLL4");
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case CLK_TYPE_FF:
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- rate = (gen3_clk_get_rate64(&parent) * core->mult) / core->div;
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- debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%llu\n",
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- __func__, __LINE__,
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- core->parent, core->mult, core->div, rate);
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- return rate;
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+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
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+ 0, core->mult, core->div,
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+ "FIXED");
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case CLK_TYPE_GEN3_MDSEL:
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div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
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