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@@ -0,0 +1,442 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * SAM9X60's PLL clock support.
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+ *
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+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
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+ *
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+ * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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+ *
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+ * Based on drivers/clk/at91/clk-sam9x60-pll.c from Linux.
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+ *
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+ */
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+
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+#include <asm/processor.h>
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+#include <common.h>
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+#include <clk-uclass.h>
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+#include <div64.h>
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+#include <dm.h>
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+#include <linux/clk-provider.h>
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+#include <linux/clk/at91_pmc.h>
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+#include <linux/delay.h>
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+
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+#include "pmc.h"
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+
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+#define UBOOT_DM_CLK_AT91_SAM9X60_DIV_PLL "at91-sam9x60-div-pll-clk"
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+#define UBOOT_DM_CLK_AT91_SAM9X60_FRAC_PLL "at91-sam9x60-frac-pll-clk"
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+
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+#define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0)
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+#define PMC_PLL_CTRL1_MUL_MSK GENMASK(31, 24)
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+#define PMC_PLL_CTRL1_FRACR_MSK GENMASK(21, 0)
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+
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+#define PLL_DIV_MAX (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
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+#define UPLL_DIV 2
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+#define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
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+
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+#define FCORE_MIN (600000000)
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+#define FCORE_MAX (1200000000)
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+
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+#define PLL_MAX_ID 7
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+
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+struct sam9x60_pll {
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+ void __iomem *base;
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+ const struct clk_pll_characteristics *characteristics;
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+ const struct clk_pll_layout *layout;
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+ struct clk clk;
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+ u8 id;
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+};
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+
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+#define to_sam9x60_pll(_clk) container_of(_clk, struct sam9x60_pll, clk)
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+
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+static inline bool sam9x60_pll_ready(void __iomem *base, int id)
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+{
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+ unsigned int status;
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+
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+ pmc_read(base, AT91_PMC_PLL_ISR0, &status);
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+
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+ return !!(status & BIT(id));
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+}
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+
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+static long sam9x60_frac_pll_compute_mul_frac(u32 *mul, u32 *frac, ulong rate,
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+ ulong parent_rate)
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+{
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+ unsigned long tmprate, remainder;
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+ unsigned long nmul = 0;
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+ unsigned long nfrac = 0;
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+
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+ if (rate < FCORE_MIN || rate > FCORE_MAX)
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+ return -ERANGE;
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+
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+ /*
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+ * Calculate the multiplier associated with the current
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+ * divider that provide the closest rate to the requested one.
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+ */
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+ nmul = mult_frac(rate, 1, parent_rate);
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+ tmprate = mult_frac(parent_rate, nmul, 1);
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+ remainder = rate - tmprate;
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+
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+ if (remainder) {
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+ nfrac = DIV_ROUND_CLOSEST_ULL((u64)remainder * (1 << 22),
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+ parent_rate);
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+
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+ tmprate += DIV_ROUND_CLOSEST_ULL((u64)nfrac * parent_rate,
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+ (1 << 22));
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+ }
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+
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+ /* Check if resulted rate is valid. */
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+ if (tmprate < FCORE_MIN || tmprate > FCORE_MAX)
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+ return -ERANGE;
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+
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+ *mul = nmul - 1;
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+ *frac = nfrac;
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+
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+ return tmprate;
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+}
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+
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+static ulong sam9x60_frac_pll_set_rate(struct clk *clk, ulong rate)
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+{
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+ struct sam9x60_pll *pll = to_sam9x60_pll(clk);
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+ void __iomem *base = pll->base;
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+ ulong parent_rate = clk_get_parent_rate(clk);
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+ u32 nmul, cmul, nfrac, cfrac, val;
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+ bool ready = sam9x60_pll_ready(base, pll->id);
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+ long ret;
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+
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+ if (!parent_rate)
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+ return 0;
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+
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+ ret = sam9x60_frac_pll_compute_mul_frac(&nmul, &nfrac, rate,
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+ parent_rate);
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+ if (ret < 0)
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+ return 0;
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
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+ pll->id);
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+ pmc_read(base, AT91_PMC_PLL_CTRL1, &val);
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+ cmul = (val & pll->layout->mul_mask) >> pll->layout->mul_shift;
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+ cfrac = (val & pll->layout->frac_mask) >> pll->layout->frac_shift;
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+
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+ /* Check against current values. */
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+ if (sam9x60_pll_ready(base, pll->id) &&
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+ nmul == cmul && nfrac == cfrac)
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+ return 0;
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+
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+ /* Update it to hardware. */
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+ pmc_write(base, AT91_PMC_PLL_CTRL1,
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+ (nmul << pll->layout->mul_shift) |
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+ (nfrac << pll->layout->frac_shift));
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_UPDT,
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+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
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+ AT91_PMC_PLL_UPDT_UPDATE | pll->id);
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+
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+ while (ready && !sam9x60_pll_ready(base, pll->id)) {
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+ debug("waiting for pll %u...\n", pll->id);
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+ cpu_relax();
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+ }
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+
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+ return parent_rate * (nmul + 1) + ((u64)parent_rate * nfrac >> 22);
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+}
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+
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+static ulong sam9x60_frac_pll_get_rate(struct clk *clk)
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+{
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+ struct sam9x60_pll *pll = to_sam9x60_pll(clk);
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+ void __iomem *base = pll->base;
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+ ulong parent_rate = clk_get_parent_rate(clk);
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+ u32 mul, frac, val;
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+
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+ if (!parent_rate)
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+ return 0;
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
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+ pll->id);
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+ pmc_read(base, AT91_PMC_PLL_CTRL1, &val);
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+ mul = (val & pll->layout->mul_mask) >> pll->layout->mul_shift;
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+ frac = (val & pll->layout->frac_mask) >> pll->layout->frac_shift;
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+
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+ return (parent_rate * (mul + 1) + ((u64)parent_rate * frac >> 22));
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+}
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+
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+static int sam9x60_frac_pll_enable(struct clk *clk)
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+{
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+ struct sam9x60_pll *pll = to_sam9x60_pll(clk);
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+ void __iomem *base = pll->base;
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+ unsigned int val;
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+ ulong crate;
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+
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+ crate = sam9x60_frac_pll_get_rate(clk);
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+ if (crate < FCORE_MIN || crate > FCORE_MAX)
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+ return -ERANGE;
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
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+ pll->id);
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+ pmc_read(base, AT91_PMC_PLL_CTRL1, &val);
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+
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+ if (sam9x60_pll_ready(base, pll->id))
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+ return 0;
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_UPDT,
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+ AT91_PMC_PMM_UPDT_STUPTIM_MSK |
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+ AT91_PMC_PLL_UPDT_ID_MSK,
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+ AT91_PMC_PLL_UPDT_STUPTIM(0x3f) | pll->id);
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+
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+ /* Recommended value for AT91_PMC_PLL_ACR */
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+ if (pll->characteristics->upll)
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+ val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;
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+ else
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+ val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;
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+ pmc_write(base, AT91_PMC_PLL_ACR, val);
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+
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+ if (pll->characteristics->upll) {
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+ /* Enable the UTMI internal bandgap */
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+ val |= AT91_PMC_PLL_ACR_UTMIBG;
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+ pmc_write(base, AT91_PMC_PLL_ACR, val);
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+
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+ udelay(10);
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+
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+ /* Enable the UTMI internal regulator */
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+ val |= AT91_PMC_PLL_ACR_UTMIVR;
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+ pmc_write(base, AT91_PMC_PLL_ACR, val);
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+
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+ udelay(10);
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_UPDT,
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+ AT91_PMC_PLL_UPDT_UPDATE |
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+ AT91_PMC_PLL_UPDT_ID_MSK,
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+ AT91_PMC_PLL_UPDT_UPDATE | pll->id);
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+ }
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_CTRL0,
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+ AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
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+ AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL);
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_UPDT,
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+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
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+ AT91_PMC_PLL_UPDT_UPDATE | pll->id);
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+
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+ while (!sam9x60_pll_ready(base, pll->id)) {
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+ debug("waiting for pll %u...\n", pll->id);
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+ cpu_relax();
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+ }
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+
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+ return 0;
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+}
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+
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+static int sam9x60_frac_pll_disable(struct clk *clk)
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+{
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+ struct sam9x60_pll *pll = to_sam9x60_pll(clk);
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+ void __iomem *base = pll->base;
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
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+ pll->id);
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_CTRL0,
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+ AT91_PMC_PLL_CTRL0_ENPLL, 0);
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+
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+ if (pll->characteristics->upll)
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+ pmc_update_bits(base, AT91_PMC_PLL_ACR,
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+ AT91_PMC_PLL_ACR_UTMIBG |
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+ AT91_PMC_PLL_ACR_UTMIVR, 0);
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_UPDT,
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+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
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+ AT91_PMC_PLL_UPDT_UPDATE | pll->id);
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+
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+ return 0;
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+}
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+
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+static const struct clk_ops sam9x60_frac_pll_ops = {
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+ .enable = sam9x60_frac_pll_enable,
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+ .disable = sam9x60_frac_pll_disable,
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+ .set_rate = sam9x60_frac_pll_set_rate,
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+ .get_rate = sam9x60_frac_pll_get_rate,
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+};
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+
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+static int sam9x60_div_pll_enable(struct clk *clk)
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+{
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+ struct sam9x60_pll *pll = to_sam9x60_pll(clk);
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+ void __iomem *base = pll->base;
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+ unsigned int val;
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
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+ pll->id);
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+ pmc_read(base, AT91_PMC_PLL_CTRL0, &val);
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+
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+ /* Stop if enabled. */
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+ if (val & pll->layout->endiv_mask)
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+ return 0;
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_CTRL0,
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+ pll->layout->endiv_mask,
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+ (1 << pll->layout->endiv_shift));
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_UPDT,
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+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
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+ AT91_PMC_PLL_UPDT_UPDATE | pll->id);
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+
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+ while (!sam9x60_pll_ready(base, pll->id)) {
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+ debug("waiting for pll %u...\n", pll->id);
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+ cpu_relax();
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+ }
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+
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+ return 0;
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+}
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+
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+static int sam9x60_div_pll_disable(struct clk *clk)
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+{
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+ struct sam9x60_pll *pll = to_sam9x60_pll(clk);
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+ void __iomem *base = pll->base;
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
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+ pll->id);
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_CTRL0,
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+ pll->layout->endiv_mask, 0);
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_UPDT,
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+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
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+ AT91_PMC_PLL_UPDT_UPDATE | pll->id);
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+
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+ return 0;
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+}
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+
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+static ulong sam9x60_div_pll_set_rate(struct clk *clk, ulong rate)
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+{
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+ struct sam9x60_pll *pll = to_sam9x60_pll(clk);
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+ void __iomem *base = pll->base;
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+ const struct clk_pll_characteristics *characteristics =
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+ pll->characteristics;
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+ ulong parent_rate = clk_get_parent_rate(clk);
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+ u8 div = DIV_ROUND_CLOSEST_ULL(parent_rate, rate) - 1;
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+ ulong req_rate = parent_rate / (div + 1);
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+ bool ready = sam9x60_pll_ready(base, pll->id);
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+ u32 val;
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+
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+ if (!parent_rate || div > pll->layout->div_mask ||
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+ req_rate < characteristics->output[0].min ||
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+ req_rate > characteristics->output[0].max)
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+ return 0;
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
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+ pll->id);
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+ pmc_read(base, AT91_PMC_PLL_CTRL0, &val);
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+ /* Compare against current value. */
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+ if (div == ((val & pll->layout->div_mask) >> pll->layout->div_shift))
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+ return 0;
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+
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+ /* Update it to hardware. */
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+ pmc_update_bits(base, AT91_PMC_PLL_CTRL0,
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+ pll->layout->div_mask,
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+ div << pll->layout->div_shift);
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_UPDT,
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+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
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+ AT91_PMC_PLL_UPDT_UPDATE | pll->id);
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+
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+ while (ready && !sam9x60_pll_ready(base, pll->id)) {
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+ debug("waiting for pll %u...\n", pll->id);
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+ cpu_relax();
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+ }
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+
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+ return req_rate;
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+}
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+
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+static ulong sam9x60_div_pll_get_rate(struct clk *clk)
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+{
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+ struct sam9x60_pll *pll = to_sam9x60_pll(clk);
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+ void __iomem *base = pll->base;
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+ ulong parent_rate = clk_get_parent_rate(clk);
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+ u32 val;
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+ u8 div;
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+
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+ if (!parent_rate)
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+ return 0;
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+
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+ pmc_update_bits(base, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
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+ pll->id);
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+
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+ pmc_read(base, AT91_PMC_PLL_CTRL0, &val);
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+
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+ div = (val & pll->layout->div_mask) >> pll->layout->div_shift;
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+
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+ return parent_rate / (div + 1);
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+}
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+
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+static const struct clk_ops sam9x60_div_pll_ops = {
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+ .enable = sam9x60_div_pll_enable,
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+ .disable = sam9x60_div_pll_disable,
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+ .set_rate = sam9x60_div_pll_set_rate,
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+ .get_rate = sam9x60_div_pll_get_rate,
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|
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+};
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+
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+static struct clk *
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+sam9x60_clk_register_pll(void __iomem *base, const char *type,
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+ const char *name, const char *parent_name, u8 id,
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|
+ const struct clk_pll_characteristics *characteristics,
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+ const struct clk_pll_layout *layout, u32 flags)
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|
|
+{
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+ struct sam9x60_pll *pll;
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|
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+ struct clk *clk;
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+ int ret;
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|
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+
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+ if (!base || !type || !name || !parent_name || !characteristics ||
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+ !layout || id > PLL_MAX_ID)
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|
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+ return ERR_PTR(-EINVAL);
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|
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+
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+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
|
|
+ if (!pll)
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|
|
+ return ERR_PTR(-ENOMEM);
|
|
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+
|
|
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+ pll->id = id;
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|
|
+ pll->characteristics = characteristics;
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|
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+ pll->layout = layout;
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|
|
+ pll->base = base;
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|
|
+ clk = &pll->clk;
|
|
|
+ clk->flags = flags;
|
|
|
+
|
|
|
+ ret = clk_register(clk, type, name, parent_name);
|
|
|
+ if (ret) {
|
|
|
+ kfree(pll);
|
|
|
+ clk = ERR_PTR(ret);
|
|
|
+ }
|
|
|
+
|
|
|
+ return clk;
|
|
|
+}
|
|
|
+
|
|
|
+struct clk *
|
|
|
+sam9x60_clk_register_div_pll(void __iomem *base, const char *name,
|
|
|
+ const char *parent_name, u8 id,
|
|
|
+ const struct clk_pll_characteristics *characteristics,
|
|
|
+ const struct clk_pll_layout *layout, bool critical)
|
|
|
+{
|
|
|
+ return sam9x60_clk_register_pll(base,
|
|
|
+ UBOOT_DM_CLK_AT91_SAM9X60_DIV_PLL, name, parent_name, id,
|
|
|
+ characteristics, layout,
|
|
|
+ CLK_GET_RATE_NOCACHE | (critical ? CLK_IS_CRITICAL : 0));
|
|
|
+}
|
|
|
+
|
|
|
+struct clk *
|
|
|
+sam9x60_clk_register_frac_pll(void __iomem *base, const char *name,
|
|
|
+ const char *parent_name, u8 id,
|
|
|
+ const struct clk_pll_characteristics *characteristics,
|
|
|
+ const struct clk_pll_layout *layout, bool critical)
|
|
|
+{
|
|
|
+ return sam9x60_clk_register_pll(base,
|
|
|
+ UBOOT_DM_CLK_AT91_SAM9X60_FRAC_PLL, name, parent_name, id,
|
|
|
+ characteristics, layout,
|
|
|
+ CLK_GET_RATE_NOCACHE | (critical ? CLK_IS_CRITICAL : 0));
|
|
|
+}
|
|
|
+
|
|
|
+U_BOOT_DRIVER(at91_sam9x60_div_pll_clk) = {
|
|
|
+ .name = UBOOT_DM_CLK_AT91_SAM9X60_DIV_PLL,
|
|
|
+ .id = UCLASS_CLK,
|
|
|
+ .ops = &sam9x60_div_pll_ops,
|
|
|
+ .flags = DM_FLAG_PRE_RELOC,
|
|
|
+};
|
|
|
+
|
|
|
+U_BOOT_DRIVER(at91_sam9x60_frac_pll_clk) = {
|
|
|
+ .name = UBOOT_DM_CLK_AT91_SAM9X60_FRAC_PLL,
|
|
|
+ .id = UCLASS_CLK,
|
|
|
+ .ops = &sam9x60_frac_pll_ops,
|
|
|
+ .flags = DM_FLAG_PRE_RELOC,
|
|
|
+};
|
|
|
+
|