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mpc83xx: Migrate SPCR to Kconfig

Migrate the SPCR setting to Kconfig.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Mario Six %!s(int64=5) %!d(string=hai) anos
pai
achega
e35012e802
Modificáronse 37 ficheiros con 192 adicións e 52 borrados
  1. 1 0
      arch/powerpc/cpu/mpc83xx/Kconfig
  2. 1 28
      arch/powerpc/cpu/mpc83xx/cpu_init.c
  3. 5 0
      arch/powerpc/cpu/mpc83xx/initreg/Kconfig
  4. 115 0
      arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
  5. 43 0
      arch/powerpc/cpu/mpc83xx/initreg/initreg.h
  6. 1 0
      configs/MPC8308RDB_defconfig
  7. 1 0
      configs/MPC8315ERDB_defconfig
  8. 1 0
      configs/MPC8323ERDB_defconfig
  9. 2 0
      configs/MPC8349EMDS_PCI64_defconfig
  10. 2 0
      configs/MPC8349EMDS_SLAVE_defconfig
  11. 2 0
      configs/MPC8349EMDS_defconfig
  12. 2 0
      configs/MPC8349ITXGP_defconfig
  13. 2 0
      configs/MPC8349ITX_LOWBOOT_defconfig
  14. 2 0
      configs/MPC8349ITX_defconfig
  15. 1 0
      configs/MPC837XEMDS_HOST_defconfig
  16. 1 0
      configs/MPC837XEMDS_SLAVE_defconfig
  17. 1 0
      configs/MPC837XEMDS_defconfig
  18. 1 0
      configs/MPC837XERDB_SLAVE_defconfig
  19. 1 0
      configs/MPC837XERDB_defconfig
  20. 1 0
      configs/hrcon_defconfig
  21. 1 0
      configs/hrcon_dh_defconfig
  22. 1 0
      configs/mpc8308_p1m_defconfig
  23. 1 0
      configs/strider_con_defconfig
  24. 1 0
      configs/strider_con_dp_defconfig
  25. 1 0
      configs/strider_cpu_defconfig
  26. 1 0
      configs/strider_cpu_dp_defconfig
  27. 0 2
      include/configs/MPC8308RDB.h
  28. 0 2
      include/configs/MPC8315ERDB.h
  29. 0 3
      include/configs/MPC8323ERDB.h
  30. 0 2
      include/configs/MPC8349EMDS.h
  31. 0 2
      include/configs/MPC8349ITX.h
  32. 0 3
      include/configs/MPC837XEMDS.h
  33. 0 3
      include/configs/MPC837XERDB.h
  34. 0 2
      include/configs/hrcon.h
  35. 0 2
      include/configs/mpc8308_p1m.h
  36. 0 2
      include/configs/strider.h
  37. 0 1
      scripts/config_whitelist.txt

+ 1 - 0
arch/powerpc/cpu/mpc83xx/Kconfig

@@ -296,6 +296,7 @@ source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig"
 source "arch/powerpc/cpu/mpc83xx/hid/Kconfig"
 source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig"
 source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
 
 menu "Legacy options"
 

+ 1 - 28
arch/powerpc/cpu/mpc83xx/cpu_init.c

@@ -16,6 +16,7 @@
 #include "elbc/elbc.h"
 #include "sysio/sysio.h"
 #include "arbiter/arbiter.h"
+#include "initreg/initreg.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -52,34 +53,6 @@ static void config_qe_ioports(void)
  */
 void cpu_init_f (volatile immap_t * im)
 {
-	__be32 spcr_mask =
-#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
-		SPCR_OPT |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
-		SPCR_TSECEP |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
-		SPCR_TSEC1EP |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
-		SPCR_TSEC2EP |
-#endif
-		0;
-	__be32 spcr_val =
-#ifdef CONFIG_SYS_SPCR_OPT
-		(CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
-		(CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
-		(CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
-		(CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
-#endif
-		0;
 	__be32 sccr_mask =
 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
 		SCCR_ENCCM |

+ 5 - 0
arch/powerpc/cpu/mpc83xx/initreg/Kconfig

@@ -0,0 +1,5 @@
+menu "Initial register configuration"
+
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr"
+
+endmenu

+ 115 - 0
arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr

@@ -0,0 +1,115 @@
+menu "SPCR - System priority and configuration register"
+
+choice
+	prompt "Optimize"
+
+config SPCR_OPT_UNSET
+	bool "Don't set value"
+
+config SPCR_OPT_NONE
+	bool "No performance enhancement"
+
+config SPCR_OPT_SPEC_READ
+	bool "Performance enhancement by speculative read"
+
+endchoice
+
+if ARCH_MPC8308 || ARCH_MPC831X || ARCH_MPC837X
+
+choice
+	prompt "TSEC emergency priority"
+
+config SPCR_TSECEP_UNSET
+	bool "Don't set value"
+
+config SPCR_TSECEP_0
+	bool "Level 0 (lowest priority)"
+
+config SPCR_TSECEP_1
+	bool "Level 1"
+
+config SPCR_TSECEP_2
+	bool "Level 2"
+
+config SPCR_TSECEP_3
+	bool "Level 3 (highest priority)"
+
+endchoice
+
+endif
+
+if ARCH_MPC8349
+
+choice
+	prompt "TSEC1 emergency priority"
+
+config SPCR_TSEC1EP_UNSET
+	bool "Don't set value"
+
+config SPCR_TSEC1EP_0
+	bool "Level 0 (lowest priority)"
+
+config SPCR_TSEC1EP_1
+	bool "Level 1"
+
+config SPCR_TSEC1EP_2
+	bool "Level 2"
+
+config SPCR_TSEC1EP_3
+	bool "Level 3 (highest priority)"
+
+endchoice
+
+choice
+	prompt "TSEC2 emergency priority"
+
+config SPCR_TSEC2EP_UNSET
+	bool "Don't set value"
+
+config SPCR_TSEC2EP_0
+	bool "Level 0 (lowest priority)"
+
+config SPCR_TSEC2EP_1
+	bool "Level 1"
+
+config SPCR_TSEC2EP_2
+	bool "Level 2"
+
+config SPCR_TSEC2EP_3
+	bool "Level 3 (highest priority)"
+
+endchoice
+
+endif
+
+config SPCR_OPT
+	hex
+	default 0x0 if SPCR_OPT_UNSET
+	default 0x0 if SPCR_OPT_NONE
+	default 0x800000 if SPCR_OPT_SPEC_READ
+
+config SPCR_TSECEP
+	hex
+	default 0x0 if SPCR_TSECEP_UNSET
+	default 0x0 if SPCR_TSECEP_0
+	default 0x100 if SPCR_TSECEP_1
+	default 0x200 if SPCR_TSECEP_2
+	default 0x300 if SPCR_TSECEP_3
+
+config SPCR_TSEC1EP
+	hex
+	default 0x0 if SPCR_TSEC1EP_UNSET
+	default 0x0 if SPCR_TSEC1EP_0
+	default 0x100 if SPCR_TSEC1EP_1
+	default 0x200 if SPCR_TSEC1EP_2
+	default 0x300 if SPCR_TSEC1EP_3
+
+config SPCR_TSEC2EP
+	hex
+	default 0x0 if SPCR_TSEC2EP_UNSET
+	default 0x0 if SPCR_TSEC2EP_0
+	default 0x1 if SPCR_TSEC2EP_1
+	default 0x2 if SPCR_TSEC2EP_2
+	default 0x3 if SPCR_TSEC2EP_3
+
+endmenu

+ 43 - 0
arch/powerpc/cpu/mpc83xx/initreg/initreg.h

@@ -0,0 +1,43 @@
+#define SPCR_PCIHPE_MASK	0x10000000
+#define SPCR_PCIPR_MASK		0x03000000
+#define SPCR_OPT_MASK		0x00800000
+#define SPCR_TBEN_MASK		0x00400000
+#define SPCR_COREPR_MASK	0x00300000
+#define SPCR_TSEC1DP_MASK	0x00003000
+#define SPCR_TSEC1BDP_MASK	0x00000C00
+#define SPCR_TSEC1EP_MASK	0x00000300
+#define SPCR_TSEC2DP_MASK	0x00000030
+#define SPCR_TSEC2BDP_MASK	0x0000000C
+#define SPCR_TSEC2EP_MASK	0x00000003
+#define SPCR_TSECDP_MASK	0x00003000
+#define SPCR_TSECBDP_MASK	0x00000C00
+#define SPCR_TSECEP_MASK	0x00000300
+
+	const __be32 spcr_mask =
+#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
+		SPCR_OPT_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET)
+		SPCR_TSECEP_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET)
+		SPCR_TSEC1EP_MASK |
+#endif
+#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
+		SPCR_TSEC2EP_MASK |
+#endif
+		0;
+	const __be32 spcr_val =
+#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
+		CONFIG_SPCR_OPT |
+#endif
+#if defined(CONFIG_SPCR_TSECEP) && !defined(CONFIG_SPCR_TSECEP_UNSET)
+		CONFIG_SPCR_TSECEP |
+#endif
+#if defined(CONFIG_SPCR_TSEC1EP) && !defined(CONFIG_SPCR_TSEC1EP_UNSET)
+		CONFIG_SPCR_TSEC1EP |
+#endif
+#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
+		CONFIG_SPCR_TSEC2EP |
+#endif
+		0;

+ 1 - 0
configs/MPC8308RDB_defconfig

@@ -72,6 +72,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y
 CONFIG_SICR_TMSOBI2_2_5_V=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y

+ 1 - 0
configs/MPC8315ERDB_defconfig

@@ -82,6 +82,7 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

+ 1 - 0
configs/MPC8323ERDB_defconfig

@@ -75,6 +75,7 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_OPT_SPEC_READ=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

+ 2 - 0
configs/MPC8349EMDS_PCI64_defconfig

@@ -58,6 +58,8 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

+ 2 - 0
configs/MPC8349EMDS_SLAVE_defconfig

@@ -56,6 +56,8 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
 CONFIG_PCI_ONE_PCI1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y

+ 2 - 0
configs/MPC8349EMDS_defconfig

@@ -58,6 +58,8 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
 CONFIG_PCI_ONE_PCI1=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y

+ 2 - 0
configs/MPC8349ITXGP_defconfig

@@ -101,6 +101,8 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000"

+ 2 - 0
configs/MPC8349ITX_LOWBOOT_defconfig

@@ -101,6 +101,8 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

+ 2 - 0
configs/MPC8349ITX_defconfig

@@ -100,6 +100,8 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSEC1EP_3=y
+CONFIG_SPCR_TSEC2EP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

+ 1 - 0
configs/MPC837XEMDS_HOST_defconfig

@@ -106,6 +106,7 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

+ 1 - 0
configs/MPC837XEMDS_SLAVE_defconfig

@@ -66,6 +66,7 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"

+ 1 - 0
configs/MPC837XEMDS_defconfig

@@ -86,6 +86,7 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=6

+ 1 - 0
configs/MPC837XERDB_SLAVE_defconfig

@@ -66,6 +66,7 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE"

+ 1 - 0
configs/MPC837XERDB_defconfig

@@ -106,6 +106,7 @@ CONFIG_HID0_FINAL_ICE=y
 CONFIG_HID2_HBE=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCIE"

+ 1 - 0
configs/hrcon_defconfig

@@ -69,6 +69,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y
 CONFIG_SICR_TMSOBI2_2_5_V=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y

+ 1 - 0
configs/hrcon_dh_defconfig

@@ -69,6 +69,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y
 CONFIG_SICR_TMSOBI2_2_5_V=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y

+ 1 - 0
configs/mpc8308_p1m_defconfig

@@ -70,6 +70,7 @@ CONFIG_SICR_GTM_GPIO=y
 CONFIG_SICR_GPIOSEL_IEEE1588=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_BOOTDELAY=5

+ 1 - 0
configs/strider_con_defconfig

@@ -68,6 +68,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y
 CONFIG_SICR_TMSOBI2_2_5_V=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y

+ 1 - 0
configs/strider_con_dp_defconfig

@@ -68,6 +68,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y
 CONFIG_SICR_TMSOBI2_2_5_V=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y

+ 1 - 0
configs/strider_cpu_defconfig

@@ -68,6 +68,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y
 CONFIG_SICR_TMSOBI2_2_5_V=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y

+ 1 - 0
configs/strider_cpu_dp_defconfig

@@ -68,6 +68,7 @@ CONFIG_SICR_TMSOBI1_2_5_V=y
 CONFIG_SICR_TMSOBI2_2_5_V=y
 CONFIG_ACR_PIPE_DEP_4=y
 CONFIG_ACR_RPTCNT_4=y
+CONFIG_SPCR_TSECEP_3=y
 CONFIG_CMD_IOLOOP=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y

+ 0 - 2
include/configs/MPC8308RDB.h

@@ -33,8 +33,6 @@
 #define CONFIG_FSL_SERDES
 #define CONFIG_FSL_SERDES1	0xe3000
 
-#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
-
 /*
  * DDR Setup
  */

+ 0 - 2
include/configs/MPC8315ERDB.h

@@ -31,8 +31,6 @@
 
 #define CONFIG_HWCONFIG
 
-#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
-
 /*
  * DDR Setup
  */

+ 0 - 3
include/configs/MPC8323ERDB.h

@@ -20,9 +20,6 @@
  */
 #define CONFIG_SYS_SICRL		0x00000000
 
-/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
-#define CONFIG_SYS_SPCR_OPT	1
-
 /*
  * DDR Setup
  */

+ 0 - 2
include/configs/MPC8349EMDS.h

@@ -328,8 +328,6 @@
 /*
  * System performance
  */
-#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
 #define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
 #define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
 

+ 0 - 2
include/configs/MPC8349ITX.h

@@ -403,8 +403,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 /*
  * System performance
  */
-#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
 #define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
 #define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
 #define CONFIG_SYS_SCCR_USBMPHCM 3	/* USB MPH controller's clock */

+ 0 - 3
include/configs/MPC837XEMDS.h

@@ -12,9 +12,6 @@
  */
 #define CONFIG_E300		1 /* E300 family */
 
-/* System Priority Control Register */
-#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC1/2 emergency has highest priority */
-
 /*
  * IP blocks clock configuration
  */

+ 0 - 3
include/configs/MPC837XERDB.h

@@ -23,9 +23,6 @@
 /* System performance - define the value i.e. CONFIG_SYS_XXX
 */
 
-/* System Priority Control Regsiter */
-#define CONFIG_SYS_SPCR_TSECEP	3	/* eTSEC1&2 emergency priority (0-3) */
-
 /* System Clock Configuration Register */
 #define CONFIG_SYS_SCCR_TSEC1CM	1		/* eTSEC1 clock mode (0-3) */
 #define CONFIG_SYS_SCCR_TSEC2CM	1		/* eTSEC2 clock mode (0-3) */

+ 0 - 2
include/configs/hrcon.h

@@ -21,8 +21,6 @@
 #define CONFIG_FSL_SERDES
 #define CONFIG_FSL_SERDES1	0xe3000
 
-#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
-
 /*
  * DDR Setup
  */

+ 0 - 2
include/configs/mpc8308_p1m.h

@@ -36,8 +36,6 @@
 #define CONFIG_FSL_SERDES
 #define CONFIG_FSL_SERDES1	0xe3000
 
-#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
-
 /*
  * DDR Setup
  */

+ 0 - 2
include/configs/strider.h

@@ -21,8 +21,6 @@
 #define CONFIG_FSL_SERDES
 #define CONFIG_FSL_SERDES1	0xe3000
 
-#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
-
 /*
  * DDR Setup
  */

+ 0 - 1
scripts/config_whitelist.txt

@@ -4085,7 +4085,6 @@ CONFIG_SYS_SPANSION_BOOT
 CONFIG_SYS_SPCR_OPT
 CONFIG_SYS_SPCR_TSEC1EP
 CONFIG_SYS_SPCR_TSEC2EP
-CONFIG_SYS_SPCR_TSECEP
 CONFIG_SYS_SPD_BUS_NUM
 CONFIG_SYS_SPI0
 CONFIG_SYS_SPI0_NUM_CS