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@@ -0,0 +1,651 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (C) 2016 Nexell Co., Ltd.
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+ *
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+ * Author: junghyun, kim <jhkim@nexell.co.kr>
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+ *
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+ * Copyright (C) 2020 Stefan Bosch <stefan_b@posteo.net>
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+ */
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+
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+#include <config.h>
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+#include <common.h>
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+#include <command.h>
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+#include <dm.h>
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+#include <mapmem.h>
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+#include <malloc.h>
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+#include <linux/compat.h>
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+#include <linux/err.h>
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+#include <video.h> /* For struct video_uc_platdata */
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+#include <video_fb.h>
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+#include <lcd.h>
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+#include <asm/global_data.h>
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+#include <asm/io.h>
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+#include <asm/arch/display.h>
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+#include <asm/arch/display_dev.h>
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+#include "videomodes.h"
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+#if !defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL)
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+static struct nx_display_dev *dp_dev;
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+#endif
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+
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+static char *const dp_dev_str[] = {
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+ [DP_DEVICE_RESCONV] = "RESCONV",
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+ [DP_DEVICE_RGBLCD] = "LCD",
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+ [DP_DEVICE_HDMI] = "HDMI",
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+ [DP_DEVICE_MIPI] = "MiPi",
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+ [DP_DEVICE_LVDS] = "LVDS",
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+ [DP_DEVICE_CVBS] = "TVOUT",
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+ [DP_DEVICE_DP0] = "DP0",
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+ [DP_DEVICE_DP1] = "DP1",
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+};
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+
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+#if CONFIG_IS_ENABLED(OF_CONTROL)
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+static void nx_display_parse_dp_sync(ofnode node, struct dp_sync_info *sync)
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+{
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+ sync->h_active_len = ofnode_read_s32_default(node, "h_active_len", 0);
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+ sync->h_sync_width = ofnode_read_s32_default(node, "h_sync_width", 0);
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+ sync->h_back_porch = ofnode_read_s32_default(node, "h_back_porch", 0);
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+ sync->h_front_porch = ofnode_read_s32_default(node, "h_front_porch", 0);
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+ sync->h_sync_invert = ofnode_read_s32_default(node, "h_sync_invert", 0);
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+ sync->v_active_len = ofnode_read_s32_default(node, "v_active_len", 0);
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+ sync->v_sync_width = ofnode_read_s32_default(node, "v_sync_width", 0);
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+ sync->v_back_porch = ofnode_read_s32_default(node, "v_back_porch", 0);
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+ sync->v_front_porch = ofnode_read_s32_default(node, "v_front_porch", 0);
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+ sync->v_sync_invert = ofnode_read_s32_default(node, "v_sync_invert", 0);
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+ sync->pixel_clock_hz = ofnode_read_s32_default(node, "pixel_clock_hz", 0);
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+
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+ debug("DP: sync ->\n");
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+ debug("ha:%d, hs:%d, hb:%d, hf:%d, hi:%d\n",
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+ sync->h_active_len, sync->h_sync_width,
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+ sync->h_back_porch, sync->h_front_porch, sync->h_sync_invert);
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+ debug("va:%d, vs:%d, vb:%d, vf:%d, vi:%d\n",
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+ sync->v_active_len, sync->v_sync_width,
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+ sync->v_back_porch, sync->v_front_porch, sync->v_sync_invert);
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+}
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+
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+static void nx_display_parse_dp_ctrl(ofnode node, struct dp_ctrl_info *ctrl)
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+{
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+ /* clock gen */
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+ ctrl->clk_src_lv0 = ofnode_read_s32_default(node, "clk_src_lv0", 0);
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+ ctrl->clk_div_lv0 = ofnode_read_s32_default(node, "clk_div_lv0", 0);
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+ ctrl->clk_src_lv1 = ofnode_read_s32_default(node, "clk_src_lv1", 0);
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+ ctrl->clk_div_lv1 = ofnode_read_s32_default(node, "clk_div_lv1", 0);
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+
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+ /* scan format */
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+ ctrl->interlace = ofnode_read_s32_default(node, "interlace", 0);
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+
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+ /* syncgen format */
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+ ctrl->out_format = ofnode_read_s32_default(node, "out_format", 0);
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+ ctrl->invert_field = ofnode_read_s32_default(node, "invert_field", 0);
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+ ctrl->swap_RB = ofnode_read_s32_default(node, "swap_RB", 0);
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+ ctrl->yc_order = ofnode_read_s32_default(node, "yc_order", 0);
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+
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+ /* extern sync delay */
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+ ctrl->delay_mask = ofnode_read_s32_default(node, "delay_mask", 0);
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+ ctrl->d_rgb_pvd = ofnode_read_s32_default(node, "d_rgb_pvd", 0);
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+ ctrl->d_hsync_cp1 = ofnode_read_s32_default(node, "d_hsync_cp1", 0);
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+ ctrl->d_vsync_fram = ofnode_read_s32_default(node, "d_vsync_fram", 0);
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+ ctrl->d_de_cp2 = ofnode_read_s32_default(node, "d_de_cp2", 0);
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+
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+ /* extern sync delay */
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+ ctrl->vs_start_offset =
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+ ofnode_read_s32_default(node, "vs_start_offset", 0);
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+ ctrl->vs_end_offset = ofnode_read_s32_default(node, "vs_end_offset", 0);
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+ ctrl->ev_start_offset =
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+ ofnode_read_s32_default(node, "ev_start_offset", 0);
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+ ctrl->ev_end_offset = ofnode_read_s32_default(node, "ev_end_offset", 0);
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+
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+ /* pad clock seletor */
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+ ctrl->vck_select = ofnode_read_s32_default(node, "vck_select", 0);
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+ ctrl->clk_inv_lv0 = ofnode_read_s32_default(node, "clk_inv_lv0", 0);
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+ ctrl->clk_delay_lv0 = ofnode_read_s32_default(node, "clk_delay_lv0", 0);
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+ ctrl->clk_inv_lv1 = ofnode_read_s32_default(node, "clk_inv_lv1", 0);
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+ ctrl->clk_delay_lv1 = ofnode_read_s32_default(node, "clk_delay_lv1", 0);
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+ ctrl->clk_sel_div1 = ofnode_read_s32_default(node, "clk_sel_div1", 0);
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+
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+ debug("DP: ctrl [%s] ->\n",
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+ ctrl->interlace ? "Interlace" : " Progressive");
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+ debug("cs0:%d, cd0:%d, cs1:%d, cd1:%d\n",
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+ ctrl->clk_src_lv0, ctrl->clk_div_lv0,
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+ ctrl->clk_src_lv1, ctrl->clk_div_lv1);
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+ debug("fmt:0x%x, inv:%d, swap:%d, yb:0x%x\n",
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+ ctrl->out_format, ctrl->invert_field,
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+ ctrl->swap_RB, ctrl->yc_order);
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+ debug("dm:0x%x, drp:%d, dhs:%d, dvs:%d, dde:0x%x\n",
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+ ctrl->delay_mask, ctrl->d_rgb_pvd,
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+ ctrl->d_hsync_cp1, ctrl->d_vsync_fram, ctrl->d_de_cp2);
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+ debug("vss:%d, vse:%d, evs:%d, eve:%d\n",
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+ ctrl->vs_start_offset, ctrl->vs_end_offset,
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+ ctrl->ev_start_offset, ctrl->ev_end_offset);
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+ debug("sel:%d, i0:%d, d0:%d, i1:%d, d1:%d, s1:%d\n",
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+ ctrl->vck_select, ctrl->clk_inv_lv0, ctrl->clk_delay_lv0,
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+ ctrl->clk_inv_lv1, ctrl->clk_delay_lv1, ctrl->clk_sel_div1);
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+}
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+
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+static void nx_display_parse_dp_top_layer(ofnode node, struct dp_plane_top *top)
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+{
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+ top->screen_width = ofnode_read_s32_default(node, "screen_width", 0);
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+ top->screen_height = ofnode_read_s32_default(node, "screen_height", 0);
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+ top->video_prior = ofnode_read_s32_default(node, "video_prior", 0);
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+ top->interlace = ofnode_read_s32_default(node, "interlace", 0);
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+ top->back_color = ofnode_read_s32_default(node, "back_color", 0);
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+ top->plane_num = DP_PLANS_NUM;
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+
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+ debug("DP: top [%s] ->\n",
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+ top->interlace ? "Interlace" : " Progressive");
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+ debug("w:%d, h:%d, prior:%d, bg:0x%x\n",
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+ top->screen_width, top->screen_height,
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+ top->video_prior, top->back_color);
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+}
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+
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+static void nx_display_parse_dp_layer(ofnode node, struct dp_plane_info *plane)
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+{
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+ plane->left = ofnode_read_s32_default(node, "left", 0);
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+ plane->width = ofnode_read_s32_default(node, "width", 0);
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+ plane->top = ofnode_read_s32_default(node, "top", 0);
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+ plane->height = ofnode_read_s32_default(node, "height", 0);
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+ plane->pixel_byte = ofnode_read_s32_default(node, "pixel_byte", 0);
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+ plane->format = ofnode_read_s32_default(node, "format", 0);
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+ plane->alpha_on = ofnode_read_s32_default(node, "alpha_on", 0);
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+ plane->alpha_depth = ofnode_read_s32_default(node, "alpha", 0);
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+ plane->tp_on = ofnode_read_s32_default(node, "tp_on", 0);
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+ plane->tp_color = ofnode_read_s32_default(node, "tp_color", 0);
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+
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+ /* enable layer */
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+ if (plane->fb_base)
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+ plane->enable = 1;
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+ else
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+ plane->enable = 0;
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+
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+ if (plane->fb_base == 0) {
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+ printf("fail : dp plane.%d invalid fb base [0x%x] ->\n",
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+ plane->layer, plane->fb_base);
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+ return;
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+ }
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+
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+ debug("DP: plane.%d [0x%x] ->\n", plane->layer, plane->fb_base);
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+ debug("f:0x%x, l:%d, t:%d, %d * %d, bpp:%d, a:%d(%d), t:%d(0x%x)\n",
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+ plane->format, plane->left, plane->top, plane->width,
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+ plane->height, plane->pixel_byte, plane->alpha_on,
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+ plane->alpha_depth, plane->tp_on, plane->tp_color);
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+}
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+
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+static void nx_display_parse_dp_planes(ofnode node,
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+ struct nx_display_dev *dp,
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+ struct video_uc_platdata *plat)
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+{
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+ const char *name;
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+ ofnode subnode;
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+
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+ ofnode_for_each_subnode(subnode, node) {
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+ name = ofnode_get_name(subnode);
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+
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+ if (strcmp(name, "layer_top") == 0)
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+ nx_display_parse_dp_top_layer(subnode, &dp->top);
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+
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+ /*
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+ * TODO: Is it sure that only one layer is used? Otherwise
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+ * fb_base must be different?
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+ */
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+ if (strcmp(name, "layer_0") == 0) {
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+ dp->planes[0].fb_base =
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+ (uint)map_sysmem(plat->base, plat->size);
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+ debug("%s(): dp->planes[0].fb_base == 0x%x\n", __func__,
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+ (uint)dp->planes[0].fb_base);
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+ nx_display_parse_dp_layer(subnode, &dp->planes[0]);
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+ }
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+
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+ if (strcmp(name, "layer_1") == 0) {
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+ dp->planes[1].fb_base =
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+ (uint)map_sysmem(plat->base, plat->size);
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+ debug("%s(): dp->planes[1].fb_base == 0x%x\n", __func__,
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+ (uint)dp->planes[1].fb_base);
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+ nx_display_parse_dp_layer(subnode, &dp->planes[1]);
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+ }
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+
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+ if (strcmp(name, "layer_2") == 0) {
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+ dp->planes[2].fb_base =
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+ (uint)map_sysmem(plat->base, plat->size);
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+ debug("%s(): dp->planes[2].fb_base == 0x%x\n", __func__,
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+ (uint)dp->planes[2].fb_base);
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+ nx_display_parse_dp_layer(subnode, &dp->planes[2]);
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+ }
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+ }
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+}
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+
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+static int nx_display_parse_dp_lvds(ofnode node, struct nx_display_dev *dp)
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+{
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+ struct dp_lvds_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
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+
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+ if (!dev) {
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+ printf("failed to allocate display LVDS object.\n");
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+ return -ENOMEM;
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+ }
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+
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+ dp->device = dev;
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+
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+ dev->lvds_format = ofnode_read_s32_default(node, "format", 0);
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+ dev->pol_inv_hs = ofnode_read_s32_default(node, "pol_inv_hs", 0);
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+ dev->pol_inv_vs = ofnode_read_s32_default(node, "pol_inv_vs", 0);
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+ dev->pol_inv_de = ofnode_read_s32_default(node, "pol_inv_de", 0);
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+ dev->pol_inv_ck = ofnode_read_s32_default(node, "pol_inv_ck", 0);
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+ dev->voltage_level = ofnode_read_s32_default(node, "voltage_level", 0);
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+
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+ if (!dev->voltage_level)
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+ dev->voltage_level = DEF_VOLTAGE_LEVEL;
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+
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+ debug("DP: LVDS -> %s, voltage LV:0x%x\n",
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+ dev->lvds_format == DP_LVDS_FORMAT_VESA ? "VESA" :
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+ dev->lvds_format == DP_LVDS_FORMAT_JEIDA ? "JEIDA" : "LOC",
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+ dev->voltage_level);
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+ debug("pol inv hs:%d, vs:%d, de:%d, ck:%d\n",
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+ dev->pol_inv_hs, dev->pol_inv_vs,
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+ dev->pol_inv_de, dev->pol_inv_ck);
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+
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+ return 0;
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+}
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+
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+static int nx_display_parse_dp_rgb(ofnode node, struct nx_display_dev *dp)
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+{
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+ struct dp_rgb_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
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+
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+ if (!dev) {
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+ printf("failed to allocate display RGB LCD object.\n");
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+ return -ENOMEM;
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+ }
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+ dp->device = dev;
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+
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+ dev->lcd_mpu_type = ofnode_read_s32_default(node, "lcd_mpu_type", 0);
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+
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+ debug("DP: RGB -> MPU[%s]\n", dev->lcd_mpu_type ? "O" : "X");
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+ return 0;
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+}
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+
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+static int nx_display_parse_dp_mipi(ofnode node, struct nx_display_dev *dp)
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+{
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+ struct dp_mipi_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
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+
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+ if (!dev) {
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+ printf("failed to allocate display MiPi object.\n");
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+ return -ENOMEM;
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+ }
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+ dp->device = dev;
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+
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+ dev->lp_bitrate = ofnode_read_s32_default(node, "lp_bitrate", 0);
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+ dev->hs_bitrate = ofnode_read_s32_default(node, "hs_bitrate", 0);
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+ dev->lpm_trans = 1;
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+ dev->command_mode = 0;
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+
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+ debug("DP: MIPI ->\n");
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+ debug("lp:%dmhz, hs:%dmhz\n", dev->lp_bitrate, dev->hs_bitrate);
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+
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+ return 0;
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+}
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+
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+static int nx_display_parse_dp_hdmi(ofnode node, struct nx_display_dev *dp)
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+{
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+ struct dp_hdmi_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
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+
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+ if (!dev) {
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+ printf("failed to allocate display HDMI object.\n");
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+ return -ENOMEM;
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+ }
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+ dp->device = dev;
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+
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+ dev->preset = ofnode_read_s32_default(node, "preset", 0);
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+
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+ debug("DP: HDMI -> %d\n", dev->preset);
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+
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+ return 0;
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+}
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+
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+static int nx_display_parse_dp_lcds(ofnode node, const char *type,
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+ struct nx_display_dev *dp)
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+{
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+ if (strcmp(type, "lvds") == 0) {
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+ dp->dev_type = DP_DEVICE_LVDS;
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+ return nx_display_parse_dp_lvds(node, dp);
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+ } else if (strcmp(type, "rgb") == 0) {
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+ dp->dev_type = DP_DEVICE_RGBLCD;
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+ return nx_display_parse_dp_rgb(node, dp);
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+ } else if (strcmp(type, "mipi") == 0) {
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+ dp->dev_type = DP_DEVICE_MIPI;
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+ return nx_display_parse_dp_mipi(node, dp);
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+ } else if (strcmp(type, "hdmi") == 0) {
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+ dp->dev_type = DP_DEVICE_HDMI;
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+ return nx_display_parse_dp_hdmi(node, dp);
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+ }
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+
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+ printf("%s: node %s unknown display type\n", __func__,
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+ ofnode_get_name(node));
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+ return -EINVAL;
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+
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+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+#define DT_SYNC (1 << 0)
|
|
|
+#define DT_CTRL (1 << 1)
|
|
|
+#define DT_PLANES (1 << 2)
|
|
|
+#define DT_DEVICE (1 << 3)
|
|
|
+
|
|
|
+static int nx_display_parse_dt(struct udevice *dev,
|
|
|
+ struct nx_display_dev *dp,
|
|
|
+ struct video_uc_platdata *plat)
|
|
|
+{
|
|
|
+ const char *name, *dtype;
|
|
|
+ int ret = 0;
|
|
|
+ unsigned int dt_status = 0;
|
|
|
+ ofnode subnode;
|
|
|
+
|
|
|
+ if (!dev)
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ dp->module = dev_read_s32_default(dev, "module", -1);
|
|
|
+ if (dp->module == -1)
|
|
|
+ dp->module = dev_read_s32_default(dev, "index", 0);
|
|
|
+
|
|
|
+ dtype = dev_read_string(dev, "lcd-type");
|
|
|
+
|
|
|
+ ofnode_for_each_subnode(subnode, dev_ofnode(dev)) {
|
|
|
+ name = ofnode_get_name(subnode);
|
|
|
+
|
|
|
+ if (strcmp("dp-sync", name) == 0) {
|
|
|
+ dt_status |= DT_SYNC;
|
|
|
+ nx_display_parse_dp_sync(subnode, &dp->sync);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (strcmp("dp-ctrl", name) == 0) {
|
|
|
+ dt_status |= DT_CTRL;
|
|
|
+ nx_display_parse_dp_ctrl(subnode, &dp->ctrl);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (strcmp("dp-planes", name) == 0) {
|
|
|
+ dt_status |= DT_PLANES;
|
|
|
+ nx_display_parse_dp_planes(subnode, dp, plat);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (strcmp("dp-device", name) == 0) {
|
|
|
+ dt_status |= DT_DEVICE;
|
|
|
+ ret = nx_display_parse_dp_lcds(subnode, dtype, dp);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (dt_status != (DT_SYNC | DT_CTRL | DT_PLANES | DT_DEVICE)) {
|
|
|
+ printf("Not enough DT config for display [0x%x]\n", dt_status);
|
|
|
+ return -ENODEV;
|
|
|
+ }
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+__weak int nx_display_fixup_dp(struct nx_display_dev *dp)
|
|
|
+{
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static struct nx_display_dev *nx_display_setup(void)
|
|
|
+{
|
|
|
+ struct nx_display_dev *dp;
|
|
|
+ int i, ret;
|
|
|
+ int node = 0;
|
|
|
+ struct video_uc_platdata *plat = NULL;
|
|
|
+
|
|
|
+ struct udevice *dev;
|
|
|
+
|
|
|
+ /* call driver probe */
|
|
|
+ debug("DT: uclass device call...\n");
|
|
|
+
|
|
|
+ ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
|
|
|
+ if (ret) {
|
|
|
+ debug("%s(): uclass_get_device(UCLASS_VIDEO, 0, &dev) != 0 --> return NULL\n",
|
|
|
+ __func__);
|
|
|
+ return NULL;
|
|
|
+ }
|
|
|
+ plat = dev_get_uclass_platdata(dev);
|
|
|
+ if (!dev) {
|
|
|
+ debug("%s(): dev_get_uclass_platdata(dev) == NULL --> return NULL\n",
|
|
|
+ __func__);
|
|
|
+ return NULL;
|
|
|
+ }
|
|
|
+ dp = dev_get_priv(dev);
|
|
|
+ if (!dp) {
|
|
|
+ debug("%s(): dev_get_priv(dev) == NULL --> return NULL\n",
|
|
|
+ __func__);
|
|
|
+ return NULL;
|
|
|
+ }
|
|
|
+ node = dev->node.of_offset;
|
|
|
+
|
|
|
+ if (CONFIG_IS_ENABLED(OF_CONTROL)) {
|
|
|
+ ret = nx_display_parse_dt(dev, dp, plat);
|
|
|
+ if (ret)
|
|
|
+ goto err_setup;
|
|
|
+ }
|
|
|
+
|
|
|
+ nx_display_fixup_dp(dp);
|
|
|
+
|
|
|
+ for (i = 0; dp->top.plane_num > i; i++) {
|
|
|
+ dp->planes[i].layer = i;
|
|
|
+ if (dp->planes[i].enable && !dp->fb_plane) {
|
|
|
+ dp->fb_plane = &dp->planes[i];
|
|
|
+ dp->fb_addr = dp->fb_plane->fb_base;
|
|
|
+ dp->depth = dp->fb_plane->pixel_byte;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ switch (dp->dev_type) {
|
|
|
+#ifdef CONFIG_VIDEO_NX_RGB
|
|
|
+ case DP_DEVICE_RGBLCD:
|
|
|
+ nx_rgb_display(dp->module,
|
|
|
+ &dp->sync, &dp->ctrl, &dp->top,
|
|
|
+ dp->planes, (struct dp_rgb_dev *)dp->device);
|
|
|
+ break;
|
|
|
+#endif
|
|
|
+#ifdef CONFIG_VIDEO_NX_LVDS
|
|
|
+ case DP_DEVICE_LVDS:
|
|
|
+ nx_lvds_display(dp->module,
|
|
|
+ &dp->sync, &dp->ctrl, &dp->top,
|
|
|
+ dp->planes, (struct dp_lvds_dev *)dp->device);
|
|
|
+ break;
|
|
|
+#endif
|
|
|
+#ifdef CONFIG_VIDEO_NX_MIPI
|
|
|
+ case DP_DEVICE_MIPI:
|
|
|
+ nx_mipi_display(dp->module,
|
|
|
+ &dp->sync, &dp->ctrl, &dp->top,
|
|
|
+ dp->planes, (struct dp_mipi_dev *)dp->device);
|
|
|
+ break;
|
|
|
+#endif
|
|
|
+#ifdef CONFIG_VIDEO_NX_HDMI
|
|
|
+ case DP_DEVICE_HDMI:
|
|
|
+ nx_hdmi_display(dp->module,
|
|
|
+ &dp->sync, &dp->ctrl, &dp->top,
|
|
|
+ dp->planes, (struct dp_hdmi_dev *)dp->device);
|
|
|
+ break;
|
|
|
+#endif
|
|
|
+ default:
|
|
|
+ printf("fail : not support lcd type %d !!!\n", dp->dev_type);
|
|
|
+ goto err_setup;
|
|
|
+ };
|
|
|
+
|
|
|
+ printf("LCD: [%s] dp.%d.%d %dx%d %dbpp FB:0x%08x\n",
|
|
|
+ dp_dev_str[dp->dev_type], dp->module, dp->fb_plane->layer,
|
|
|
+ dp->fb_plane->width, dp->fb_plane->height, dp->depth * 8,
|
|
|
+ dp->fb_addr);
|
|
|
+
|
|
|
+ return dp;
|
|
|
+
|
|
|
+err_setup:
|
|
|
+ kfree(dp);
|
|
|
+
|
|
|
+ return NULL;
|
|
|
+}
|
|
|
+
|
|
|
+#if defined CONFIG_LCD
|
|
|
+
|
|
|
+/* default lcd */
|
|
|
+struct vidinfo panel_info = {
|
|
|
+ .vl_col = 320, .vl_row = 240, .vl_bpix = 32,
|
|
|
+};
|
|
|
+
|
|
|
+void lcd_ctrl_init(void *lcdbase)
|
|
|
+{
|
|
|
+ vidinfo_t *pi = &panel_info;
|
|
|
+ struct nx_display_dev *dp;
|
|
|
+ int bpix;
|
|
|
+
|
|
|
+ dp = nx_display_setup();
|
|
|
+ if (!dp)
|
|
|
+ return NULL;
|
|
|
+
|
|
|
+ switch (dp->depth) {
|
|
|
+ case 2:
|
|
|
+ bpix = LCD_COLOR16;
|
|
|
+ break;
|
|
|
+ case 3:
|
|
|
+ case 4:
|
|
|
+ bpix = LCD_COLOR32;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ printf("fail : not support LCD bit per pixel %d\n",
|
|
|
+ dp->depth * 8);
|
|
|
+ return NULL;
|
|
|
+ }
|
|
|
+
|
|
|
+ dp->panel_info = pi;
|
|
|
+
|
|
|
+ /* set resolution with config */
|
|
|
+ pi->vl_bpix = bpix;
|
|
|
+ pi->vl_col = dp->fb_plane->width;
|
|
|
+ pi->vl_row = dp->fb_plane->height;
|
|
|
+ pi->priv = dp;
|
|
|
+ gd->fb_base = dp->fb_addr;
|
|
|
+}
|
|
|
+
|
|
|
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
|
|
|
+{
|
|
|
+}
|
|
|
+
|
|
|
+__weak void lcd_enable(void)
|
|
|
+{
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+static int nx_display_probe(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
|
|
|
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
|
|
|
+ struct nx_display_platdata *plat = dev_get_platdata(dev);
|
|
|
+ static GraphicDevice *graphic_device;
|
|
|
+ char addr[64];
|
|
|
+
|
|
|
+ debug("%s()\n", __func__);
|
|
|
+
|
|
|
+ if (!dev)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ if (!uc_plat) {
|
|
|
+ debug("%s(): video_uc_platdata *plat == NULL --> return -EINVAL\n",
|
|
|
+ __func__);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!uc_priv) {
|
|
|
+ debug("%s(): video_priv *uc_priv == NULL --> return -EINVAL\n",
|
|
|
+ __func__);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!plat) {
|
|
|
+ debug("%s(): nx_display_platdata *plat == NULL --> return -EINVAL\n",
|
|
|
+ __func__);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ struct nx_display_dev *dp;
|
|
|
+ unsigned int pp_index = 0;
|
|
|
+
|
|
|
+ dp = nx_display_setup();
|
|
|
+ if (!dp) {
|
|
|
+ debug("%s(): nx_display_setup() == 0 --> return -EINVAL\n",
|
|
|
+ __func__);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ switch (dp->depth) {
|
|
|
+ case 2:
|
|
|
+ pp_index = GDF_16BIT_565RGB;
|
|
|
+ uc_priv->bpix = VIDEO_BPP16;
|
|
|
+ break;
|
|
|
+ case 3:
|
|
|
+ /* There is no VIDEO_BPP24 because these values are of
|
|
|
+ * type video_log2_bpp
|
|
|
+ */
|
|
|
+ case 4:
|
|
|
+ pp_index = GDF_32BIT_X888RGB;
|
|
|
+ uc_priv->bpix = VIDEO_BPP32;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ printf("fail : not support LCD bit per pixel %d\n",
|
|
|
+ dp->depth * 8);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ uc_priv->xsize = dp->fb_plane->width;
|
|
|
+ uc_priv->ysize = dp->fb_plane->height;
|
|
|
+ uc_priv->rot = 0;
|
|
|
+
|
|
|
+ graphic_device = &dp->graphic_device;
|
|
|
+ graphic_device->frameAdrs = dp->fb_addr;
|
|
|
+ graphic_device->gdfIndex = pp_index;
|
|
|
+ graphic_device->gdfBytesPP = dp->depth;
|
|
|
+ graphic_device->winSizeX = dp->fb_plane->width;
|
|
|
+ graphic_device->winSizeY = dp->fb_plane->height;
|
|
|
+ graphic_device->plnSizeX =
|
|
|
+ graphic_device->winSizeX * graphic_device->gdfBytesPP;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * set environment variable "fb_addr" (frame buffer address), required
|
|
|
+ * for splash image. Because drv_video_init() in common/stdio.c is only
|
|
|
+ * called when CONFIG_VIDEO is set (and not if CONFIG_DM_VIDEO is set).
|
|
|
+ */
|
|
|
+ sprintf(addr, "0x%x", dp->fb_addr);
|
|
|
+ debug("%s(): env_set(\"fb_addr\", %s) ...\n", __func__, addr);
|
|
|
+ env_set("fb_addr", addr);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int nx_display_bind(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
|
|
|
+
|
|
|
+ debug("%s()\n", __func__);
|
|
|
+
|
|
|
+ /* Datasheet S5p4418:
|
|
|
+ * Resolution up to 2048 x 1280, up to 12 Bit per color (HDMI)
|
|
|
+ * Actual (max.) size is 0x1000000 because in U-Boot nanopi2-2016.01
|
|
|
+ * "#define CONFIG_FB_ADDR 0x77000000" and next address is
|
|
|
+ * "#define BMP_LOAD_ADDR 0x78000000"
|
|
|
+ */
|
|
|
+ plat->size = 0x1000000;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static const struct udevice_id nx_display_ids[] = {
|
|
|
+ {.compatible = "nexell,nexell-display", },
|
|
|
+ {}
|
|
|
+};
|
|
|
+
|
|
|
+U_BOOT_DRIVER(nexell_display) = {
|
|
|
+ .name = "nexell-display",
|
|
|
+ .id = UCLASS_VIDEO,
|
|
|
+ .of_match = nx_display_ids,
|
|
|
+ .platdata_auto_alloc_size =
|
|
|
+ sizeof(struct nx_display_platdata),
|
|
|
+ .bind = nx_display_bind,
|
|
|
+ .probe = nx_display_probe,
|
|
|
+ .priv_auto_alloc_size = sizeof(struct nx_display_dev),
|
|
|
+};
|