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@@ -136,7 +136,8 @@ enum mtk_switch {
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enum mtk_soc {
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SOC_MT7623,
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- SOC_MT7629
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+ SOC_MT7629,
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+ SOC_MT7622
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};
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struct mtk_eth_priv {
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@@ -151,6 +152,7 @@ struct mtk_eth_priv {
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void __iomem *fe_base;
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void __iomem *gmac_base;
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void __iomem *ethsys_base;
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+ void __iomem *sgmii_base;
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struct mii_dev *mdio_bus;
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int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
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@@ -750,6 +752,24 @@ static int mtk_phy_probe(struct udevice *dev)
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return 0;
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}
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+static void mtk_sgmii_init(struct mtk_eth_priv *priv)
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+{
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+ /* Set SGMII GEN2 speed(2.5G) */
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+ clrsetbits_le32(priv->sgmii_base + SGMSYS_GEN2_SPEED,
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+ SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
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+
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+ /* Disable SGMII AN */
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+ clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
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+ SGMII_AN_ENABLE, 0);
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+
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+ /* SGMII force mode setting */
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+ writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
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+
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+ /* Release PHYA power down state */
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+ clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
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+ SGMII_PHYA_PWD, 0);
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+}
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+
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static void mtk_mac_init(struct mtk_eth_priv *priv)
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{
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int i, ge_mode = 0;
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@@ -758,8 +778,13 @@ static void mtk_mac_init(struct mtk_eth_priv *priv)
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switch (priv->phy_interface) {
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII:
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+ ge_mode = GE_MODE_RGMII;
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+ break;
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case PHY_INTERFACE_MODE_SGMII:
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ge_mode = GE_MODE_RGMII;
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+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
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+ SYSCFG0_SGMII_SEL(priv->gmac_id));
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+ mtk_sgmii_init(priv);
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break;
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case PHY_INTERFACE_MODE_MII:
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case PHY_INTERFACE_MODE_GMII:
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@@ -828,7 +853,8 @@ static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
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memset(priv->rx_ring_noc, 0, NUM_RX_DESC * sizeof(struct pdma_rxdesc));
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memset(priv->pkt_pool, 0, TOTAL_PKT_BUF_SIZE);
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- flush_dcache_range((u32)pkt_base, (u32)(pkt_base + TOTAL_PKT_BUF_SIZE));
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+ flush_dcache_range((ulong)pkt_base,
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+ (ulong)(pkt_base + TOTAL_PKT_BUF_SIZE));
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priv->rx_dma_owner_idx0 = 0;
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priv->tx_cpu_owner_idx0 = 0;
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@@ -940,7 +966,7 @@ static int mtk_eth_send(struct udevice *dev, void *packet, int length)
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pkt_base = (void *)phys_to_virt(priv->tx_ring_noc[idx].txd_info1.SDP0);
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memcpy(pkt_base, packet, length);
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- flush_dcache_range((u32)pkt_base, (u32)pkt_base +
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+ flush_dcache_range((ulong)pkt_base, (ulong)pkt_base +
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roundup(length, ARCH_DMA_MINALIGN));
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priv->tx_ring_noc[idx].txd_info2.SDL0 = length;
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@@ -966,7 +992,7 @@ static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp)
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length = priv->rx_ring_noc[idx].rxd_info2.PLEN0;
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pkt_base = (void *)phys_to_virt(priv->rx_ring_noc[idx].rxd_info1.PDP0);
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- invalidate_dcache_range((u32)pkt_base, (u32)pkt_base +
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+ invalidate_dcache_range((ulong)pkt_base, (ulong)pkt_base +
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roundup(length, ARCH_DMA_MINALIGN));
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if (packetp)
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@@ -994,7 +1020,7 @@ static int mtk_eth_probe(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_platdata(dev);
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struct mtk_eth_priv *priv = dev_get_priv(dev);
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- u32 iobase = pdata->iobase;
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+ ulong iobase = pdata->iobase;
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int ret;
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/* Frame Engine Register Base */
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@@ -1104,6 +1130,26 @@ static int mtk_eth_ofdata_to_platdata(struct udevice *dev)
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}
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}
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+ if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) {
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+ /* get corresponding sgmii phandle */
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+ ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys",
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+ NULL, 0, 0, &args);
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+ if (ret)
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+ return ret;
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+
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+ regmap = syscon_node_to_regmap(args.node);
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+
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+ if (IS_ERR(regmap))
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+ return PTR_ERR(regmap);
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+
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+ priv->sgmii_base = regmap_get_range(regmap, 0);
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+
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+ if (!priv->sgmii_base) {
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+ dev_err(dev, "Unable to find sgmii\n");
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+ return -ENODEV;
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+ }
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+ }
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+
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/* check for switch first, otherwise phy will be used */
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priv->sw = SW_NONE;
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priv->switch_init = NULL;
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@@ -1151,6 +1197,7 @@ static int mtk_eth_ofdata_to_platdata(struct udevice *dev)
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static const struct udevice_id mtk_eth_ids[] = {
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{ .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 },
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{ .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 },
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+ { .compatible = "mediatek,mt7622-eth", .data = SOC_MT7622 },
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{}
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};
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