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@@ -14,6 +14,11 @@
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#include <asm/io.h>
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#include <asm/armv8/mmu.h>
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#include <linux/sizes.h>
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+#include <usb.h>
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+#include <linux/usb/otg.h>
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+#include <asm/arch/usb-gx.h>
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+#include <usb/dwc2_udc.h>
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+#include <clk.h>
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#include <phy.h>
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DECLARE_GLOBAL_DATA_PTR;
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@@ -149,3 +154,116 @@ void meson_eth_init(phy_interface_t mode, unsigned int flags)
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/* Enable power gate */
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clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
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}
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+
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+#if CONFIG_IS_ENABLED(USB_XHCI_DWC3_OF_SIMPLE) && \
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+ CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
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+static struct dwc2_plat_otg_data meson_gx_dwc2_data;
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+static struct phy usb_phys[2];
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+
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+int board_usb_init(int index, enum usb_init_type init)
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+{
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+ struct ofnode_phandle_args args;
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+ struct udevice *clk_dev;
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+ ofnode dwc2_node;
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+ struct clk clk;
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+ int ret, i;
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+ u32 val;
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+
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+ /* find the dwc2 node */
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+ dwc2_node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
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+ if (!ofnode_valid(dwc2_node)) {
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+ debug("Not found dwc2 node\n");
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+ return -ENODEV;
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+ }
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+
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+ if (!ofnode_is_available(dwc2_node)) {
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+ debug("dwc2 is disabled in the device tree\n");
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+ return -ENODEV;
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+ }
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+
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+ /* get the PHYs */
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+ for (i = 0; i < 2; i++) {
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+ ret = generic_phy_get_by_node(dwc2_node, i, &usb_phys[i]);
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+ if (ret && ret != -ENOENT) {
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+ pr_err("Failed to get USB PHY%d for %s\n",
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+ i, ofnode_get_name(dwc2_node));
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+ return ret;
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+ }
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+ }
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+
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+ for (i = 0; i < 2; i++) {
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+ ret = generic_phy_init(&usb_phys[i]);
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+ if (ret) {
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+ pr_err("Can't init USB PHY%d for %s\n",
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+ i, ofnode_get_name(dwc2_node));
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+ return ret;
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+ }
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+ }
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+
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+ for (i = 0; i < 2; i++) {
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+ ret = generic_phy_power_on(&usb_phys[i]);
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+ if (ret) {
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+ pr_err("Can't power USB PHY%d for %s\n",
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+ i, ofnode_get_name(dwc2_node));
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+ return ret;
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+ }
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+ }
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+
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+ phy_meson_gxl_usb3_set_mode(&usb_phys[0], USB_DR_MODE_PERIPHERAL);
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+ phy_meson_gxl_usb2_set_mode(&usb_phys[1], USB_DR_MODE_PERIPHERAL);
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+
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+ meson_gx_dwc2_data.regs_otg = ofnode_get_addr(dwc2_node);
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+ if (meson_gx_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
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+ debug("usbotg: can't get base address\n");
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+ return -ENODATA;
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+ }
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+
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+ /* Enable clock */
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+ ret = ofnode_parse_phandle_with_args(dwc2_node, "clocks",
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+ "#clock-cells", 0, 0, &args);
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+ if (ret) {
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+ debug("usbotg has no clocks defined in the device tree\n");
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+ return ret;
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+ }
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+
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+ ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &clk_dev);
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+ if (ret)
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+ return ret;
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+
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+ if (args.args_count != 1) {
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+ debug("Can't find clock ID in the device tree\n");
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+ return -ENODATA;
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+ }
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+
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+ clk.dev = clk_dev;
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+ clk.id = args.args[0];
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+
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+ ret = clk_enable(&clk);
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+ if (ret) {
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+ debug("Failed to enable usbotg clock\n");
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+ return ret;
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+ }
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+
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+ ofnode_read_u32(dwc2_node, "g-rx-fifo-size", &val);
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+ meson_gx_dwc2_data.rx_fifo_sz = val;
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+ ofnode_read_u32(dwc2_node, "g-np-tx-fifo-size", &val);
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+ meson_gx_dwc2_data.np_tx_fifo_sz = val;
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+ ofnode_read_u32(dwc2_node, "g-tx-fifo-size", &val);
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+ meson_gx_dwc2_data.tx_fifo_sz = val;
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+
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+ return dwc2_udc_probe(&meson_gx_dwc2_data);
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+}
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+
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+int board_usb_cleanup(int index, enum usb_init_type init)
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+{
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+ int i;
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+
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+ phy_meson_gxl_usb3_set_mode(&usb_phys[0], USB_DR_MODE_HOST);
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+ phy_meson_gxl_usb2_set_mode(&usb_phys[1], USB_DR_MODE_HOST);
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+
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+ for (i = 0; i < 2; i++)
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+ usb_phys[i].dev = NULL;
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+
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+ return 0;
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+}
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+#endif
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