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@@ -15,125 +15,73 @@ void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
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void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
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void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
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-struct socfpga_system_manager {
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- /* System Manager Module */
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- u32 siliconid1; /* 0x00 */
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- u32 siliconid2;
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- u32 wddbg;
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- u32 _pad_0xc;
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- u32 mpu_status; /* 0x10 */
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- u32 mpu_ace;
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- u32 _pad_0x18_0x1c[2];
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- u32 dma; /* 0x20 */
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- u32 dma_periph;
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- /* SDMMC Controller Group */
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- u32 sdmmcgrp_ctrl;
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- u32 sdmmcgrp_l3master;
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- /* NAND Flash Controller Register Group */
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- u32 nandgrp_bootstrap; /* 0x30 */
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- u32 nandgrp_l3master;
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- /* USB Controller Group */
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- u32 usb0_l3master;
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- u32 usb1_l3master;
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- /* EMAC Group */
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- u32 emac_gbl; /* 0x40 */
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- u32 emac0;
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- u32 emac1;
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- u32 emac2;
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- u32 emac0_ace; /* 0x50 */
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- u32 emac1_ace;
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- u32 emac2_ace;
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- u32 nand_axuser;
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- u32 _pad_0x60_0x64[2]; /* 0x60 */
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- /* FPGA interface Group */
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- u32 fpgaintf_en_1;
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- u32 fpgaintf_en_2;
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- u32 fpgaintf_en_3; /* 0x70 */
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- u32 dma_l3master;
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- u32 etr_l3master;
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- u32 _pad_0x7c;
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- u32 sec_ctrl_slt; /* 0x80 */
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- u32 osc_trim;
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- u32 _pad_0x88_0x8c[2];
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- /* ECC Group */
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- u32 ecc_intmask_value; /* 0x90 */
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- u32 ecc_intmask_set;
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- u32 ecc_intmask_clr;
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- u32 ecc_intstatus_serr;
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- u32 ecc_intstatus_derr; /* 0xa0 */
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- u32 _pad_0xa4_0xac[3];
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- u32 noc_addr_remap; /* 0xb0 */
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- u32 hmc_clk;
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- u32 io_pa_ctrl;
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- u32 _pad_0xbc;
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- /* NOC Group */
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- u32 noc_timeout; /* 0xc0 */
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- u32 noc_idlereq_set;
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- u32 noc_idlereq_clr;
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- u32 noc_idlereq_value;
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- u32 noc_idleack; /* 0xd0 */
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- u32 noc_idlestatus;
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- u32 fpga2soc_ctrl;
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- u32 fpga_config;
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- u32 iocsrclk_gate; /* 0xe0 */
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- u32 gpo;
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- u32 gpi;
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- u32 _pad_0xec;
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- u32 mpu; /* 0xf0 */
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- u32 sdm_hps_spare;
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- u32 hps_sdm_spare;
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- u32 _pad_0xfc_0x1fc[65];
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- /* Boot scratch register group */
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- u32 boot_scratch_cold0; /* 0x200 */
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- u32 boot_scratch_cold1;
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- u32 boot_scratch_cold2;
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- u32 boot_scratch_cold3;
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- u32 boot_scratch_cold4; /* 0x210 */
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- u32 boot_scratch_cold5;
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- u32 boot_scratch_cold6;
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- u32 boot_scratch_cold7;
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- u32 boot_scratch_cold8; /* 0x220 */
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- u32 boot_scratch_cold9;
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- u32 _pad_0x228_0xffc[886];
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- /* Pin select and pin control group */
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- u32 pinsel0[40]; /* 0x1000 */
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- u32 _pad_0x10a0_0x10fc[24];
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- u32 pinsel40[8];
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- u32 _pad_0x1120_0x112c[4];
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- u32 ioctrl0[28];
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- u32 _pad_0x11a0_0x11fc[24];
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- u32 ioctrl28[20];
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- u32 _pad_0x1250_0x12fc[44];
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- /* Use FPGA mux */
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- u32 rgmii0usefpga; /* 0x1300 */
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- u32 rgmii1usefpga;
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- u32 rgmii2usefpga;
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- u32 i2c0usefpga;
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- u32 i2c1usefpga;
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- u32 i2c_emac0_usefpga;
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- u32 i2c_emac1_usefpga;
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- u32 i2c_emac2_usefpga;
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- u32 nandusefpga;
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- u32 _pad_0x1324;
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- u32 spim0usefpga;
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- u32 spim1usefpga;
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- u32 spis0usefpga;
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- u32 spis1usefpga;
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- u32 uart0usefpga;
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- u32 uart1usefpga;
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- u32 mdio0usefpga;
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- u32 mdio1usefpga;
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- u32 mdio2usefpga;
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- u32 _pad_0x134c;
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- u32 jtagusefpga;
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- u32 sdmmcusefpga;
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- u32 hps_osc_clk;
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- u32 _pad_0x135c_0x13fc[41];
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- u32 iodelay0[40];
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- u32 _pad_0x14a0_0x14fc[24];
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- u32 iodelay40[8];
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+#define SYSMGR_S10_WDDBG 0x08
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+#define SYSMGR_S10_DMA 0x20
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+#define SYSMGR_S10_DMA_PERIPH 0x24
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+#define SYSMGR_S10_SDMMC 0x28
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+#define SYSMGR_S10_SDMMC_L3MASTER 0x2c
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+#define SYSMGR_S10_EMAC_GLOBAL 0x40
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+#define SYSMGR_S10_EMAC0 0x44
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+#define SYSMGR_S10_EMAC1 0x48
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+#define SYSMGR_S10_EMAC2 0x4c
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+#define SYSMGR_S10_EMAC0_ACE 0x50
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+#define SYSMGR_S10_EMAC1_ACE 0x54
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+#define SYSMGR_S10_EMAC2_ACE 0x58
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+#define SYSMGR_S10_NAND_AXUSER 0x5c
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+#define SYSMGR_S10_FPGAINTF_EN1 0x68
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+#define SYSMGR_S10_FPGAINTF_EN2 0x6c
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+#define SYSMGR_S10_FPGAINTF_EN3 0x70
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+#define SYSMGR_S10_DMA_L3MASTER 0x74
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+#define SYSMGR_S10_HMC_CLK 0xb4
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+#define SYSMGR_S10_IO_PA_CTRL 0xb8
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+#define SYSMGR_S10_NOC_TIMEOUT 0xc0
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+#define SYSMGR_S10_NOC_IDLEREQ_SET 0xc4
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+#define SYSMGR_S10_NOC_IDLEREQ_CLR 0xc8
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+#define SYSMGR_S10_NOC_IDLEREQ_VAL 0xcc
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+#define SYSMGR_S10_NOC_IDLEACK 0xd0
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+#define SYSMGR_S10_NOC_IDLESTATUS 0xd4
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+#define SYSMGR_S10_FPGA2SOC_CTRL 0xd8
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+#define SYSMGR_S10_FPGA_CONFIG 0xdc
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+#define SYSMGR_S10_IOCSRCLK_GATE 0xe0
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+#define SYSMGR_S10_GPO 0xe4
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+#define SYSMGR_S10_GPI 0xe8
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+#define SYSMGR_S10_MPU 0xf0
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+#define SYSMGR_S10_BOOT_SCRATCH_COLD0 0x200
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+#define SYSMGR_S10_BOOT_SCRATCH_COLD1 0x204
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+#define SYSMGR_S10_BOOT_SCRATCH_COLD2 0x208
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+#define SYSMGR_S10_BOOT_SCRATCH_COLD3 0x20c
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+#define SYSMGR_S10_BOOT_SCRATCH_COLD4 0x210
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+#define SYSMGR_S10_BOOT_SCRATCH_COLD5 0x214
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+#define SYSMGR_S10_BOOT_SCRATCH_COLD6 0x218
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+#define SYSMGR_S10_BOOT_SCRATCH_COLD7 0x21c
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+#define SYSMGR_S10_BOOT_SCRATCH_COLD8 0x220
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+#define SYSMGR_S10_BOOT_SCRATCH_COLD9 0x224
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+#define SYSMGR_S10_PINSEL0 0x1000
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+#define SYSMGR_S10_IOCTRL0 0x1130
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+#define SYSMGR_S10_EMAC0_USEFPGA 0x1300
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+#define SYSMGR_S10_EMAC1_USEFPGA 0x1304
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+#define SYSMGR_S10_EMAC2_USEFPGA 0x1308
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+#define SYSMGR_S10_I2C0_USEFPGA 0x130c
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+#define SYSMGR_S10_I2C1_USEFPGA 0x1310
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+#define SYSMGR_S10_I2C_EMAC0_USEFPGA 0x1314
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+#define SYSMGR_S10_I2C_EMAC1_USEFPGA 0x1318
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+#define SYSMGR_S10_I2C_EMAC2_USEFPGA 0x131c
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+#define SYSMGR_S10_NAND_USEFPGA 0x1320
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+#define SYSMGR_S10_SPIM0_USEFPGA 0x1328
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+#define SYSMGR_S10_SPIM1_USEFPGA 0x132c
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+#define SYSMGR_S10_SPIS0_USEFPGA 0x1330
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+#define SYSMGR_S10_SPIS1_USEFPGA 0x1334
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+#define SYSMGR_S10_UART0_USEFPGA 0x1338
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+#define SYSMGR_S10_UART1_USEFPGA 0x133c
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+#define SYSMGR_S10_MDIO0_USEFPGA 0x1340
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+#define SYSMGR_S10_MDIO1_USEFPGA 0x1344
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+#define SYSMGR_S10_MDIO2_USEFPGA 0x1348
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+#define SYSMGR_S10_JTAG_USEFPGA 0x1350
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+#define SYSMGR_S10_SDMMC_USEFPGA 0x1354
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+#define SYSMGR_S10_HPS_OSC_CLK 0x1358
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+#define SYSMGR_S10_IODELAY0 0x1400
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-};
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+#define SYSMGR_SDMMC SYSMGR_S10_SDMMC
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
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