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@@ -1,3 +1,4 @@
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+<<<<<<< HEAD
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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@@ -129,11 +130,96 @@ err_free_reset:
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reset_release_bulk(&priv->rst);
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return ret;
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+=======
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+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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+/*
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+ * Copyright (c) 2021 StarFive Technology Co., Ltd.
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+ */
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+
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+#include <common.h>
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+#include <dm.h>
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+#include <fdtdec.h>
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+#include <init.h>
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+#include <ram.h>
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+#include <syscon.h>
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+#include <asm/global_data.h>
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+#include <asm/io.h>
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+#include <clk.h>
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+#include <wait_bit.h>
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+#include <linux/bitops.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+struct starfive_ddrctl {
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+ volatile u32 ctl_settings[1];
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+};
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+
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+struct starfive_ddrphy {
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+ volatile u32 phy_settings[1];
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+};
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+
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+/**
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+ * struct starfive_ddr_info
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+ *
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+ * @dev: pointer for the device
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+ * @info: UCLASS RAM information
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+ * @clk: clock
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+ * @ctl: controller base address
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+ * @phy: PHY base address
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+ */
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+struct starfive_ddr_info {
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+ struct udevice *dev;
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+ struct ram_info info;
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+ struct clk clk;
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+ struct starfive_ddrctl *ctl;
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+ struct starfive_ddrphy *phy;
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+};
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+
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+struct starfive_ddr_params {
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+ struct starfive_ddrctl ctrl_regs;
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+ struct starfive_ddrphy phy_regs;
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+};
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+
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+struct starfive_ddr_plat {
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+ struct starfive_ddr_params ddr_params;
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+};
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+
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+static int starfive_ddr_probe(struct udevice *dev)
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+{
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+ struct starfive_ddr_info *priv = dev_get_priv(dev);
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+#if defined(CONFIG_SPL_BUILD)
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+ int ret;
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+#endif
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+
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+ debug("starfive_ddr_probe\n");
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+
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+ /* Get memory base and size */
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+ fdtdec_setup_mem_size_base();
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+ priv->info.base = gd->ram_base;
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+ priv->info.size = gd->ram_size;
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+
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+#if defined(CONFIG_SPL_BUILD)
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+ debug("starfive_ddr_probe probing clock and setup ctl/phy settings\n");
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+ priv->dev = dev;
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+
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+ ret = clk_get_by_index(dev, 0, &priv->clk);
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+ if (ret) {
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+ debug("clk_get_by_index error:%d\n", ret);
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+ return ret;
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+ }
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+#endif
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+
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+ return 0;
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+>>>>>>> Add DDR driver framework
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}
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static int starfive_ddr_get_info(struct udevice *dev, struct ram_info *info)
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{
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+<<<<<<< HEAD
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struct starfive_ddr_priv *priv = dev_get_priv(dev);
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+=======
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+ struct starfive_ddr_info *priv = dev_get_priv(dev);
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+>>>>>>> Add DDR driver framework
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*info = priv->info;
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@@ -145,7 +231,11 @@ static struct ram_ops starfive_ddr_ops = {
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};
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static const struct udevice_id starfive_ddr_ids[] = {
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+<<<<<<< HEAD
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{ .compatible = "starfive,jh7110-dmc" },
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+=======
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+ { .compatible = "starfive,dubhe-ddr" },
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+>>>>>>> Add DDR driver framework
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{ }
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};
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@@ -155,5 +245,12 @@ U_BOOT_DRIVER(starfive_ddr) = {
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.of_match = starfive_ddr_ids,
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.ops = &starfive_ddr_ops,
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.probe = starfive_ddr_probe,
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+<<<<<<< HEAD
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.priv_auto = sizeof(struct starfive_ddr_priv),
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+=======
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+ .priv_auto = sizeof(struct starfive_ddr_info),
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+#if defined(CONFIG_SPL_BUILD)
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+ .plat_auto = sizeof(struct starfive_ddr_plat),
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+#endif
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+>>>>>>> Add DDR driver framework
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};
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