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@@ -2,7 +2,7 @@
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/*
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* Texas Instruments K3 SoC PLL clock driver
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*
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- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
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+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
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* Tero Kristo <t-kristo@ti.com>
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*/
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@@ -122,6 +122,7 @@ static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate)
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unsigned long pllm;
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u32 pllfm = 0;
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unsigned long plld;
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+ u32 div_ctrl;
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u32 rem;
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int shift;
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@@ -175,7 +176,15 @@ static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate)
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writel(pllm, pll->reg + PLL_16FFT_FREQ_CTRL0);
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writel(pllfm, pll->reg + PLL_16FFT_FREQ_CTRL1);
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- writel(plld, pll->reg + PLL_16FFT_DIV_CTRL);
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+
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+ /*
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+ * div_ctrl register contains other divider values, so rmw
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+ * only plld and leave existing values alone
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+ */
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+ div_ctrl = readl(pll->reg + PLL_16FFT_DIV_CTRL);
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+ div_ctrl &= ~PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
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+ div_ctrl |= plld;
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+ writel(div_ctrl, pll->reg + PLL_16FFT_DIV_CTRL);
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ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
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ctrl |= PLL_16FFT_CTRL_PLL_EN;
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