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@@ -1,8 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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- * Copyright (C) 2017 Intel Corporation <www.intel.com>
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+ * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
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*/
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-
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#include <asm/io.h>
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#include <asm/arch/fpga_manager.h>
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#include <asm/arch/reset_manager.h>
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@@ -10,8 +9,11 @@
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#include <asm/arch/sdram.h>
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#include <asm/arch/misc.h>
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#include <altera.h>
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+#include <asm/arch/pinmux.h>
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#include <common.h>
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+#include <dm/ofnode.h>
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#include <errno.h>
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+#include <fs_loader.h>
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#include <wait_bit.h>
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#include <watchdog.h>
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@@ -21,6 +23,9 @@
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#define COMPRESSION_OFFSET 229
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#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
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#define FPGA_TIMEOUT_CNT 0x1000000
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+#define DEFAULT_DDR_LOAD_ADDRESS 0x400
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+
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+DECLARE_GLOBAL_DATA_PTR;
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static const struct socfpga_fpga_manager *fpga_manager_base =
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(void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
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@@ -64,7 +69,7 @@ static int wait_for_user_mode(void)
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1, FPGA_TIMEOUT_MSEC, false);
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}
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-static int is_fpgamgr_early_user_mode(void)
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+int is_fpgamgr_early_user_mode(void)
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{
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return (readl(&fpga_manager_base->imgcfg_stat) &
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ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
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@@ -94,7 +99,7 @@ int fpgamgr_wait_early_user_mode(void)
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i++;
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}
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- debug("Additional %i sync word needed\n", i);
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+ debug("FPGA: Additional %i sync word needed\n", i);
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/* restoring original CDRATIO */
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fpgamgr_set_cd_ratio(cd_ratio);
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@@ -172,9 +177,10 @@ static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
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compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
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compress = !compress;
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- debug("header word %d = %08x\n", 69, rbf_data[69]);
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- debug("header word %d = %08x\n", 229, rbf_data[229]);
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- debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
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+ debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
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+ debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
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+ debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
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+ compress);
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/*
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* from the register map description of cdratio in imgcfg_ctrl_02:
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@@ -359,6 +365,7 @@ static int fpgamgr_program_poll_cd(void)
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printf("nstatus == 0 while waiting for condone\n");
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return -EPERM;
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}
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+ WATCHDOG_RESET();
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}
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if (i == FPGA_TIMEOUT_CNT)
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@@ -432,7 +439,6 @@ int fpgamgr_program_finish(void)
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printf("FPGA: Poll CD failed with error code %d\n", status);
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return -EPERM;
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}
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- WATCHDOG_RESET();
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/* Ensure the FPGA entering user mode */
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status = fpgamgr_program_poll_usermode();
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@@ -447,27 +453,493 @@ int fpgamgr_program_finish(void)
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return 0;
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}
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-/*
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- * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
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- * Return 0 for sucess, non-zero for error.
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- */
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+ofnode get_fpga_mgr_ofnode(ofnode from)
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+{
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+ return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-mgr");
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+}
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+
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+const char *get_fpga_filename(void)
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+{
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+ const char *fpga_filename = NULL;
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+
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+ ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
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+
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+ if (ofnode_valid(fpgamgr_node))
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+ fpga_filename = ofnode_read_string(fpgamgr_node,
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+ "altr,bitstream");
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+
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+ return fpga_filename;
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+}
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+
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+static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
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+{
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+ /*
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+ * Magic ID starting at:
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+ * -> 1st dword[15:0] in periph.rbf
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+ * -> 2nd dword[15:0] in core.rbf
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+ * Note: dword == 32 bits
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+ */
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+ u32 word_reading_max = 2;
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+ u32 i;
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+
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+ for (i = 0; i < word_reading_max; i++) {
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+ if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
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+ rbf->security = unencrypted;
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+ } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
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+ rbf->security = encrypted;
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+ } else if (*(buffer + i + 1) ==
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+ FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
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+ rbf->security = unencrypted;
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+ } else if (*(buffer + i + 1) ==
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+ FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
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+ rbf->security = encrypted;
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+ } else {
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+ rbf->security = invalid;
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+ continue;
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+ }
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+
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+ /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
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+ if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
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+ rbf->section = periph_section;
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+ break;
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+ } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) {
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+ rbf->section = core_section;
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+ break;
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+ } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
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+ rbf->section = periph_section;
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+ break;
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+ } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) {
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+ rbf->section = core_section;
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+ break;
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+ }
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+
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+ rbf->section = unknown;
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+ break;
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+
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+ WATCHDOG_RESET();
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+ }
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+}
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+
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+#ifdef CONFIG_FS_LOADER
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+static int first_loading_rbf_to_buffer(struct udevice *dev,
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+ struct fpga_loadfs_info *fpga_loadfs,
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+ u32 *buffer, size_t *buffer_bsize)
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+{
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+ u32 *buffer_p = (u32 *)*buffer;
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+ u32 *loadable = buffer_p;
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+ size_t buffer_size = *buffer_bsize;
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+ size_t fit_size;
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+ int ret, i, count, confs_noffset, images_noffset, rbf_offset, rbf_size;
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+ const char *fpga_node_name = NULL;
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+ const char *uname = NULL;
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+
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+ /* Load image header into buffer */
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+ ret = request_firmware_into_buf(dev,
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+ fpga_loadfs->fpga_fsinfo->filename,
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+ buffer_p, sizeof(struct image_header),
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+ 0);
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+ if (ret < 0) {
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+ debug("FPGA: Failed to read image header from flash.\n");
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+ return -ENOENT;
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+ }
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+
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+ if (image_get_magic((struct image_header *)buffer_p) != FDT_MAGIC) {
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+ debug("FPGA: No FDT magic was found.\n");
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+ return -EBADF;
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+ }
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+
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+ fit_size = fdt_totalsize(buffer_p);
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+
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+ if (fit_size > buffer_size) {
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+ debug("FPGA: FIT image is larger than available buffer.\n");
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+ debug("Please use FIT external data or increasing buffer.\n");
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+ return -ENOMEM;
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+ }
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+
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+ /* Load entire FIT into buffer */
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+ ret = request_firmware_into_buf(dev,
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+ fpga_loadfs->fpga_fsinfo->filename,
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+ buffer_p, fit_size, 0);
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = fit_check_format(buffer_p);
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+ if (!ret) {
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+ debug("FPGA: No valid FIT image was found.\n");
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+ return -EBADF;
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+ }
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+
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+ confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
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+ images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH);
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+ if (confs_noffset < 0 || images_noffset < 0) {
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+ debug("FPGA: No Configurations or images nodes were found.\n");
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+ return -ENOENT;
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+ }
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+
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+ /* Get default configuration unit name from default property */
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+ confs_noffset = fit_conf_get_node(buffer_p, NULL);
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+ if (confs_noffset < 0) {
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+ debug("FPGA: No default configuration was found in config.\n");
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+ return -ENOENT;
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+ }
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+
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+ count = fit_conf_get_prop_node_count(buffer_p, confs_noffset,
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+ FIT_FPGA_PROP);
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+ if (count < 0) {
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+ debug("FPGA: Invalid configuration format for FPGA node.\n");
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+ return count;
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+ }
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+ debug("FPGA: FPGA node count: %d\n", count);
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+
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+ for (i = 0; i < count; i++) {
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+ images_noffset = fit_conf_get_prop_node_index(buffer_p,
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+ confs_noffset,
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+ FIT_FPGA_PROP, i);
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+ uname = fit_get_name(buffer_p, images_noffset, NULL);
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+ if (uname) {
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+ debug("FPGA: %s\n", uname);
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+
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+ if (strstr(uname, "fpga-periph") &&
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+ (!is_fpgamgr_early_user_mode() ||
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+ is_fpgamgr_user_mode())) {
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+ fpga_node_name = uname;
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+ printf("FPGA: Start to program ");
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+ printf("peripheral/full bitstream ...\n");
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+ break;
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+ } else if (strstr(uname, "fpga-core") &&
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+ (is_fpgamgr_early_user_mode() &&
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+ !is_fpgamgr_user_mode())) {
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+ fpga_node_name = uname;
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+ printf("FPGA: Start to program core ");
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+ printf("bitstream ...\n");
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+ break;
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+ }
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+ }
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+ WATCHDOG_RESET();
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+ }
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+
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+ if (!fpga_node_name) {
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+ debug("FPGA: No suitable bitstream was found, count: %d.\n", i);
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+ return 1;
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+ }
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+
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+ images_noffset = fit_image_get_node(buffer_p, fpga_node_name);
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+ if (images_noffset < 0) {
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+ debug("FPGA: No node '%s' was found in FIT.\n",
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+ fpga_node_name);
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+ return -ENOENT;
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+ }
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+
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+ if (!fit_image_get_data_position(buffer_p, images_noffset,
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+ &rbf_offset)) {
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+ debug("FPGA: Data position was found.\n");
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+ } else if (!fit_image_get_data_offset(buffer_p, images_noffset,
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+ &rbf_offset)) {
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+ /*
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+ * For FIT with external data, figure out where
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+ * the external images start. This is the base
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+ * for the data-offset properties in each image.
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+ */
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+ rbf_offset += ((fdt_totalsize(buffer_p) + 3) & ~3);
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+ debug("FPGA: Data offset was found.\n");
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+ } else {
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+ debug("FPGA: No data position/offset was found.\n");
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+ return -ENOENT;
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+ }
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+
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+ ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size);
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+ if (ret < 0) {
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+ debug("FPGA: No data size was found (err=%d).\n", ret);
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+ return -ENOENT;
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+ }
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+
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+ if (gd->ram_size < rbf_size) {
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+ debug("FPGA: Using default OCRAM buffer and size.\n");
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+ } else {
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+ ret = fit_image_get_load(buffer_p, images_noffset,
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+ (ulong *)loadable);
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+ if (ret < 0) {
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+ buffer_p = (u32 *)DEFAULT_DDR_LOAD_ADDRESS;
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+ debug("FPGA: No loadable was found.\n");
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+ debug("FPGA: Using default DDR load address: 0x%x .\n",
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+ DEFAULT_DDR_LOAD_ADDRESS);
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+ } else {
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+ buffer_p = (u32 *)*loadable;
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+ debug("FPGA: Found loadable address = 0x%x.\n",
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+ *loadable);
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+ }
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+
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+ buffer_size = rbf_size;
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+ }
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+
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+ debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
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+ rbf_offset, rbf_size);
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+
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+ fpga_loadfs->remaining = rbf_size;
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+
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+ /*
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+ * Determine buffer size vs bitstream size, and calculating number of
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+ * chunk by chunk transfer is required due to smaller buffer size
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+ * compare to bitstream
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+ */
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+ if (rbf_size <= buffer_size) {
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+ /* Loading whole bitstream into buffer */
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+ buffer_size = rbf_size;
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+ fpga_loadfs->remaining = 0;
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+ } else {
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+ fpga_loadfs->remaining -= buffer_size;
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+ }
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+
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+ fpga_loadfs->offset = rbf_offset;
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+ /* Loading bitstream into buffer */
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+ ret = request_firmware_into_buf(dev,
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+ fpga_loadfs->fpga_fsinfo->filename,
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+ buffer_p, buffer_size,
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+ fpga_loadfs->offset);
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+ if (ret < 0) {
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+ debug("FPGA: Failed to read bitstream from flash.\n");
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+ return -ENOENT;
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+ }
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+
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+ /* Getting info about bitstream types */
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+ get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p);
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+
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+ /* Update next reading bitstream offset */
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+ fpga_loadfs->offset += buffer_size;
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+
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+ /* Update the final addr for bitstream */
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+ *buffer = (u32)buffer_p;
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+
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+ /* Update the size of bitstream to be programmed into FPGA */
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+ *buffer_bsize = buffer_size;
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+
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+ return 0;
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+}
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+
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+static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
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+ struct fpga_loadfs_info *fpga_loadfs,
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+ u32 *buffer, size_t *buffer_bsize)
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+{
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+ int ret = 0;
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+ u32 *buffer_p = (u32 *)*buffer;
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+
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+ /* Read the bitstream chunk by chunk. */
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+ if (fpga_loadfs->remaining > *buffer_bsize) {
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+ fpga_loadfs->remaining -= *buffer_bsize;
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+ } else {
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+ *buffer_bsize = fpga_loadfs->remaining;
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+ fpga_loadfs->remaining = 0;
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+ }
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+
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+ ret = request_firmware_into_buf(dev,
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+ fpga_loadfs->fpga_fsinfo->filename,
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+ buffer_p, *buffer_bsize,
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+ fpga_loadfs->offset);
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+ if (ret < 0) {
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+ debug("FPGA: Failed to read bitstream from flash.\n");
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+ return -ENOENT;
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+ }
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+
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+ /* Update next reading bitstream offset */
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+ fpga_loadfs->offset += *buffer_bsize;
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+
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+ return 0;
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+}
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+
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+int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
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+ u32 offset)
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+{
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+ struct fpga_loadfs_info fpga_loadfs;
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+ struct udevice *dev;
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+ int status, ret, size;
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+ u32 buffer = (uintptr_t)buf;
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+ size_t buffer_sizebytes = bsize;
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+ size_t buffer_sizebytes_ori = bsize;
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|
|
+ size_t total_sizeof_image = 0;
|
|
|
+ ofnode node;
|
|
|
+ const fdt32_t *phandle_p;
|
|
|
+ u32 phandle;
|
|
|
+
|
|
|
+ node = get_fpga_mgr_ofnode(ofnode_null());
|
|
|
+
|
|
|
+ if (ofnode_valid(node)) {
|
|
|
+ phandle_p = ofnode_get_property(node, "firmware-loader", &size);
|
|
|
+ if (!phandle_p) {
|
|
|
+ node = ofnode_path("/chosen");
|
|
|
+ if (!ofnode_valid(node)) {
|
|
|
+ debug("FPGA: /chosen node was not found.\n");
|
|
|
+ return -ENOENT;
|
|
|
+ }
|
|
|
+
|
|
|
+ phandle_p = ofnode_get_property(node, "firmware-loader",
|
|
|
+ &size);
|
|
|
+ if (!phandle_p) {
|
|
|
+ debug("FPGA: firmware-loader property was not");
|
|
|
+ debug(" found.\n");
|
|
|
+ return -ENOENT;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ debug("FPGA: FPGA manager node was not found.\n");
|
|
|
+ return -ENOENT;
|
|
|
+ }
|
|
|
+
|
|
|
+ phandle = fdt32_to_cpu(*phandle_p);
|
|
|
+ ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
|
|
|
+ phandle, &dev);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
|
|
|
+
|
|
|
+ fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
|
|
|
+ fpga_loadfs.offset = offset;
|
|
|
+
|
|
|
+ printf("FPGA: Checking FPGA configuration setting ...\n");
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Note: Both buffer and buffer_sizebytes values can be altered by
|
|
|
+ * function below.
|
|
|
+ */
|
|
|
+ ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
|
|
|
+ &buffer_sizebytes);
|
|
|
+ if (ret == 1) {
|
|
|
+ printf("FPGA: Skipping configuration ...\n");
|
|
|
+ return 0;
|
|
|
+ } else if (ret) {
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (fpga_loadfs.rbfinfo.section == core_section &&
|
|
|
+ !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
|
|
|
+ debug("FPGA : Must be in Early Release mode to program ");
|
|
|
+ debug("core bitstream.\n");
|
|
|
+ return -EPERM;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Disable all signals from HPS peripheral controller to FPGA */
|
|
|
+ writel(0, &system_manager_base->fpgaintf_en_global);
|
|
|
+
|
|
|
+ /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
|
|
|
+ socfpga_bridges_reset();
|
|
|
+
|
|
|
+ if (fpga_loadfs.rbfinfo.section == periph_section) {
|
|
|
+ /* Initialize the FPGA Manager */
|
|
|
+ status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
|
|
|
+ if (status) {
|
|
|
+ debug("FPGA: Init with peripheral bitstream failed.\n");
|
|
|
+ return -EPERM;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Transfer bitstream to FPGA Manager */
|
|
|
+ fpgamgr_program_write((void *)buffer, buffer_sizebytes);
|
|
|
+
|
|
|
+ total_sizeof_image += buffer_sizebytes;
|
|
|
+
|
|
|
+ while (fpga_loadfs.remaining) {
|
|
|
+ ret = subsequent_loading_rbf_to_buffer(dev,
|
|
|
+ &fpga_loadfs,
|
|
|
+ &buffer,
|
|
|
+ &buffer_sizebytes_ori);
|
|
|
+
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ /* Transfer data to FPGA Manager */
|
|
|
+ fpgamgr_program_write((void *)buffer,
|
|
|
+ buffer_sizebytes_ori);
|
|
|
+
|
|
|
+ total_sizeof_image += buffer_sizebytes_ori;
|
|
|
+
|
|
|
+ WATCHDOG_RESET();
|
|
|
+ }
|
|
|
+
|
|
|
+ if (fpga_loadfs.rbfinfo.section == periph_section) {
|
|
|
+ if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
|
|
|
+ config_pins(gd->fdt_blob, "shared");
|
|
|
+ puts("FPGA: Early Release Succeeded.\n");
|
|
|
+ } else {
|
|
|
+ debug("FPGA: Failed to see Early Release.\n");
|
|
|
+ return -EIO;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* For monolithic bitstream */
|
|
|
+ if (is_fpgamgr_user_mode()) {
|
|
|
+ /* Ensure the FPGA entering config done */
|
|
|
+ status = fpgamgr_program_finish();
|
|
|
+ if (status)
|
|
|
+ return status;
|
|
|
+
|
|
|
+ config_pins(gd->fdt_blob, "fpga");
|
|
|
+ puts("FPGA: Enter user mode.\n");
|
|
|
+ }
|
|
|
+ } else if (fpga_loadfs.rbfinfo.section == core_section) {
|
|
|
+ /* Ensure the FPGA entering config done */
|
|
|
+ status = fpgamgr_program_finish();
|
|
|
+ if (status)
|
|
|
+ return status;
|
|
|
+
|
|
|
+ config_pins(gd->fdt_blob, "fpga");
|
|
|
+ puts("FPGA: Enter user mode.\n");
|
|
|
+ } else {
|
|
|
+ debug("FPGA: Config Error: Unsupported bitstream type.\n");
|
|
|
+ return -ENOEXEC;
|
|
|
+ }
|
|
|
+
|
|
|
+ return (int)total_sizeof_image;
|
|
|
+}
|
|
|
+
|
|
|
+void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
|
|
|
+{
|
|
|
+ fpga_fs_info fpga_fsinfo;
|
|
|
+
|
|
|
+ fpga_fsinfo.filename = get_fpga_filename();
|
|
|
+
|
|
|
+ if (fpga_fsinfo.filename)
|
|
|
+ socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+/* This function is used to load the core bitstream from the OCRAM. */
|
|
|
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
|
|
|
{
|
|
|
- int status;
|
|
|
+ unsigned long status;
|
|
|
+ struct rbf_info rbfinfo;
|
|
|
|
|
|
- /* disable all signals from hps peripheral controller to fpga */
|
|
|
+ memset(&rbfinfo, 0, sizeof(rbfinfo));
|
|
|
+
|
|
|
+ /* Disable all signals from hps peripheral controller to fpga */
|
|
|
writel(0, &system_manager_base->fpgaintf_en_global);
|
|
|
|
|
|
- /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
|
|
|
+ /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
|
|
|
socfpga_bridges_reset();
|
|
|
|
|
|
- /* Initialize the FPGA Manager */
|
|
|
- status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
|
|
|
- if (status)
|
|
|
- return status;
|
|
|
+ /* Getting info about bitstream types */
|
|
|
+ get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
|
|
|
+
|
|
|
+ if (rbfinfo.section == periph_section) {
|
|
|
+ /* Initialize the FPGA Manager */
|
|
|
+ status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
|
|
|
+ if (status)
|
|
|
+ return status;
|
|
|
+ }
|
|
|
|
|
|
- /* Write the RBF data to FPGA Manager */
|
|
|
+ if (rbfinfo.section == core_section &&
|
|
|
+ !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
|
|
|
+ debug("FPGA : Must be in early release mode to program ");
|
|
|
+ debug("core bitstream.\n");
|
|
|
+ return -EPERM;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Write the bitstream to FPGA Manager */
|
|
|
fpgamgr_program_write(rbf_data, rbf_size);
|
|
|
|
|
|
- return fpgamgr_program_finish();
|
|
|
+ status = fpgamgr_program_finish();
|
|
|
+ if (status) {
|
|
|
+ config_pins(gd->fdt_blob, "fpga");
|
|
|
+ puts("FPGA: Enter user mode.\n");
|
|
|
+ }
|
|
|
+
|
|
|
+ return status;
|
|
|
}
|