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@@ -1,5 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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+ * Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
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* Copyright (C) 2012
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* David Purdy <david.c.purdy@gmail.com>
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*
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@@ -12,16 +13,21 @@
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#include <common.h>
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#include <init.h>
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#include <log.h>
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-#include <miiphy.h>
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-#include <net.h>
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+#include <netdev.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include <asm/global_data.h>
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-#include "pogo_e02.h"
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+#include <linux/bitops.h>
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DECLARE_GLOBAL_DATA_PTR;
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+/* GPIO configuration */
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+#define POGO_E02_OE_LOW (~(0))
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+#define POGO_E02_OE_HIGH (~(0))
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+#define POGO_E02_OE_VAL_LOW BIT(29)
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+#define POGO_E02_OE_VAL_HIGH 0
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+
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int board_early_init_f(void)
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{
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/*
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@@ -64,6 +70,11 @@ int board_early_init_f(void)
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return 0;
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}
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+int board_eth_init(struct bd_info *bis)
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+{
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+ return cpu_eth_init(bis);
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+}
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+
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int board_init(void)
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{
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/* Boot parameters address */
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@@ -71,37 +82,3 @@ int board_init(void)
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return 0;
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}
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-
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-#ifdef CONFIG_RESET_PHY_R
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-/* Configure and initialize PHY */
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-void reset_phy(void)
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-{
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- u16 reg;
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- u16 devadr;
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- char *name = "egiga0";
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-
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- if (miiphy_set_current_dev(name))
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- return;
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-
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- /* command to read PHY dev address */
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- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
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- printf("Err..(%s) could not read PHY dev address\n", __func__);
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- return;
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- }
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-
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- /*
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- * Enable RGMII delay on Tx and Rx for CPU port
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- * Ref: sec 4.7.2 of chip datasheet
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- */
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- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
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- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
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- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
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- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
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-
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- /* reset the phy */
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- miiphy_reset(name, devadr);
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-
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- debug("88E1116 Initialized on %s\n", name);
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-}
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-#endif /* CONFIG_RESET_PHY_R */
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