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@@ -680,12 +680,23 @@ struct mx31_weim {
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/* Register offsets based on IOMUXC_BASE */
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/* 0x00 .. 0x7b */
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+#define MUX_CTL_CSPI3_MISO 0x0c
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+#define MUX_CTL_CSPI3_SCLK 0x0d
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+#define MUX_CTL_CSPI3_SPI_RDY 0x0e
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+#define MUX_CTL_CSPI3_MOSI 0x13
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+
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#define MUX_CTL_USBH2_DATA1 0x40
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#define MUX_CTL_USBH2_DIR 0x44
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#define MUX_CTL_USBH2_STP 0x45
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#define MUX_CTL_USBH2_NXT 0x46
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#define MUX_CTL_USBH2_DATA0 0x47
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#define MUX_CTL_USBH2_CLK 0x4B
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+
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+#define MUX_CTL_TXD2 0x70
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+#define MUX_CTL_RTS2 0x71
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+#define MUX_CTL_CTS2 0x72
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+#define MUX_CTL_RXD2 0x77
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+
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#define MUX_CTL_RTS1 0x7c
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#define MUX_CTL_CTS1 0x7d
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#define MUX_CTL_DTR_DCE1 0x7e
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@@ -743,6 +754,11 @@ struct mx31_weim {
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#define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
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#define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
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+#define MUX_RXD2__UART2_RXD_MUX IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC)
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+#define MUX_TXD2__UART2_TXD_MUX IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC)
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+#define MUX_RTS2__UART2_RTS_B IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC)
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+#define MUX_CTS2__UART2_CTS_B IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC)
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+
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#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
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#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
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#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
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