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+/*
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+ * Driver for Marvell SOC Platform Group Xenon SDHC as a platform device
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+ *
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+ * Copyright (C) 2016 Marvell, All Rights Reserved.
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+ *
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+ * Author: Victor Gu <xigu@marvell.com>
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+ * Date: 2016-8-24
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+ *
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+ * Included parts of the Linux driver version which was written by:
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+ * Hu Ziji <huziji@marvell.com>
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+ *
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+ * Ported to from Marvell 2015.01 to mainline U-Boot 2017.01:
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+ * Stefan Roese <sr@denx.de>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0
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+ */
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+
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+#include <common.h>
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+#include <dm.h>
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+#include <fdtdec.h>
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+#include <libfdt.h>
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+#include <malloc.h>
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+#include <sdhci.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+/* Register Offset of SD Host Controller SOCP self-defined register */
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+#define SDHC_SYS_CFG_INFO 0x0104
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+#define SLOT_TYPE_SDIO_SHIFT 24
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+#define SLOT_TYPE_EMMC_MASK 0xFF
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+#define SLOT_TYPE_EMMC_SHIFT 16
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+#define SLOT_TYPE_SD_SDIO_MMC_MASK 0xFF
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+#define SLOT_TYPE_SD_SDIO_MMC_SHIFT 8
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+#define NR_SUPPORTED_SLOT_MASK 0x7
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+
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+#define SDHC_SYS_OP_CTRL 0x0108
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+#define AUTO_CLKGATE_DISABLE_MASK BIT(20)
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+#define SDCLK_IDLEOFF_ENABLE_SHIFT 8
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+#define SLOT_ENABLE_SHIFT 0
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+
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+#define SDHC_SYS_EXT_OP_CTRL 0x010C
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+#define MASK_CMD_CONFLICT_ERROR BIT(8)
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+
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+#define SDHC_SLOT_RETUNING_REQ_CTRL 0x0144
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+/* retuning compatible */
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+#define RETUNING_COMPATIBLE 0x1
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+
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+/* Xenon specific Mode Select value */
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+#define XENON_SDHCI_CTRL_HS200 0x5
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+#define XENON_SDHCI_CTRL_HS400 0x6
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+
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+#define EMMC_PHY_REG_BASE 0x170
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+#define EMMC_PHY_TIMING_ADJUST EMMC_PHY_REG_BASE
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+#define OUTPUT_QSN_PHASE_SELECT BIT(17)
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+#define SAMPL_INV_QSP_PHASE_SELECT BIT(18)
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+#define SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18
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+#define EMMC_PHY_SLOW_MODE BIT(29)
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+#define PHY_INITIALIZAION BIT(31)
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+#define WAIT_CYCLE_BEFORE_USING_MASK 0xf
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+#define WAIT_CYCLE_BEFORE_USING_SHIFT 12
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+#define FC_SYNC_EN_DURATION_MASK 0xf
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+#define FC_SYNC_EN_DURATION_SHIFT 8
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+#define FC_SYNC_RST_EN_DURATION_MASK 0xf
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+#define FC_SYNC_RST_EN_DURATION_SHIFT 4
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+#define FC_SYNC_RST_DURATION_MASK 0xf
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+#define FC_SYNC_RST_DURATION_SHIFT 0
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+
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+#define EMMC_PHY_FUNC_CONTROL (EMMC_PHY_REG_BASE + 0x4)
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+#define DQ_ASYNC_MODE BIT(4)
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+#define DQ_DDR_MODE_SHIFT 8
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+#define DQ_DDR_MODE_MASK 0xff
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+#define CMD_DDR_MODE BIT(16)
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+
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+#define EMMC_PHY_PAD_CONTROL (EMMC_PHY_REG_BASE + 0x8)
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+#define REC_EN_SHIFT 24
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+#define REC_EN_MASK 0xf
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+#define FC_DQ_RECEN BIT(24)
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+#define FC_CMD_RECEN BIT(25)
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+#define FC_QSP_RECEN BIT(26)
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+#define FC_QSN_RECEN BIT(27)
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+#define OEN_QSN BIT(28)
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+#define AUTO_RECEN_CTRL BIT(30)
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+
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+#define EMMC_PHY_PAD_CONTROL1 (EMMC_PHY_REG_BASE + 0xc)
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+#define EMMC5_1_FC_QSP_PD BIT(9)
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+#define EMMC5_1_FC_QSP_PU BIT(25)
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+#define EMMC5_1_FC_CMD_PD BIT(8)
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+#define EMMC5_1_FC_CMD_PU BIT(24)
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+#define EMMC5_1_FC_DQ_PD 0xff
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+#define EMMC5_1_FC_DQ_PU (0xff << 16)
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+
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+#define SDHCI_RETUNE_EVT_INTSIG 0x00001000
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+
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+/* Hyperion only have one slot 0 */
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+#define XENON_MMC_SLOT_ID_HYPERION 0
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+
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+#define MMC_TIMING_LEGACY 0
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+#define MMC_TIMING_MMC_HS 1
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+#define MMC_TIMING_SD_HS 2
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+#define MMC_TIMING_UHS_SDR12 3
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+#define MMC_TIMING_UHS_SDR25 4
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+#define MMC_TIMING_UHS_SDR50 5
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+#define MMC_TIMING_UHS_SDR104 6
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+#define MMC_TIMING_UHS_DDR50 7
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+#define MMC_TIMING_MMC_DDR52 8
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+#define MMC_TIMING_MMC_HS200 9
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+#define MMC_TIMING_MMC_HS400 10
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+
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+#define XENON_MMC_MAX_CLK 400000000
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+
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+enum soc_pad_ctrl_type {
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+ SOC_PAD_SD,
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+ SOC_PAD_FIXED_1_8V,
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+};
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+
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+struct xenon_sdhci_plat {
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+ struct mmc_config cfg;
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+ struct mmc mmc;
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+};
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+
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+struct xenon_sdhci_priv {
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+ struct sdhci_host host;
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+
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+ u8 timing;
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+
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+ unsigned int clock;
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+
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+ void *pad_ctrl_reg;
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+ int pad_type;
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+};
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+
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+static int xenon_mmc_phy_init(struct sdhci_host *host)
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+{
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+ struct xenon_sdhci_priv *priv = host->mmc->priv;
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+ u32 clock = priv->clock;
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+ u32 time;
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+ u32 var;
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+
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+ /* Enable QSP PHASE SELECT */
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+ var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
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+ var |= SAMPL_INV_QSP_PHASE_SELECT;
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+ if ((priv->timing == MMC_TIMING_UHS_SDR50) ||
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+ (priv->timing == MMC_TIMING_UHS_SDR25) ||
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+ (priv->timing == MMC_TIMING_UHS_SDR12) ||
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+ (priv->timing == MMC_TIMING_SD_HS) ||
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+ (priv->timing == MMC_TIMING_LEGACY))
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+ var |= EMMC_PHY_SLOW_MODE;
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+ sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
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+
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+ /* Poll for host MMC PHY clock init to be stable */
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+ /* Wait up to 10ms */
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+ time = 100;
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+ while (time--) {
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+ var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
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+ if (var & SDHCI_CLOCK_INT_STABLE)
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+ break;
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+
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+ udelay(100);
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+ }
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+
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+ if (time <= 0) {
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+ error("Failed to enable MMC internal clock in time\n");
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+ return -ETIMEDOUT;
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+ }
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+
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+ /* Init PHY */
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+ var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
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+ var |= PHY_INITIALIZAION;
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+ sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
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+
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+ if (clock == 0) {
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+ /* Use the possibly slowest bus frequency value */
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+ clock = 100000;
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+ }
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+
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+ /* Poll for host eMMC PHY init to complete */
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+ /* Wait up to 10ms */
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+ time = 100;
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+ while (time--) {
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+ var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
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+ var &= PHY_INITIALIZAION;
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+ if (!var)
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+ break;
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+
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+ /* wait for host eMMC PHY init to complete */
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+ udelay(100);
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+ }
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+
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+ if (time <= 0) {
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+ error("Failed to init MMC PHY in time\n");
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+ return -ETIMEDOUT;
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+ }
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+
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+ return 0;
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+}
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+
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+#define ARMADA_3700_SOC_PAD_1_8V 0x1
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+#define ARMADA_3700_SOC_PAD_3_3V 0x0
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+
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+static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host)
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+{
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+ struct xenon_sdhci_priv *priv = host->mmc->priv;
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+
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+ if (priv->pad_type == SOC_PAD_FIXED_1_8V)
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+ writel(ARMADA_3700_SOC_PAD_1_8V, priv->pad_ctrl_reg);
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+ else if (priv->pad_type == SOC_PAD_SD)
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+ writel(ARMADA_3700_SOC_PAD_3_3V, priv->pad_ctrl_reg);
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+}
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+
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+static void xenon_mmc_phy_set(struct sdhci_host *host)
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+{
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+ struct xenon_sdhci_priv *priv = host->mmc->priv;
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+ u32 var;
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+
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+ /* Setup pad, set bit[30], bit[28] and bits[26:24] */
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+ var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL);
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+ var |= AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN |
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+ FC_CMD_RECEN | FC_DQ_RECEN;
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+ sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL);
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+
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+ /* Set CMD and DQ Pull Up */
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+ var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL1);
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+ var |= (EMMC5_1_FC_CMD_PU | EMMC5_1_FC_DQ_PU);
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+ var &= ~(EMMC5_1_FC_CMD_PD | EMMC5_1_FC_DQ_PD);
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+ sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1);
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+
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+ /*
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+ * If timing belongs to high speed, set bit[17] of
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+ * EMMC_PHY_TIMING_ADJUST register
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+ */
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+ if ((priv->timing == MMC_TIMING_MMC_HS400) ||
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+ (priv->timing == MMC_TIMING_MMC_HS200) ||
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+ (priv->timing == MMC_TIMING_UHS_SDR50) ||
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+ (priv->timing == MMC_TIMING_UHS_SDR104) ||
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+ (priv->timing == MMC_TIMING_UHS_DDR50) ||
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+ (priv->timing == MMC_TIMING_UHS_SDR25) ||
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+ (priv->timing == MMC_TIMING_MMC_DDR52)) {
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+ var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
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+ var |= OUTPUT_QSN_PHASE_SELECT;
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+ sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
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+ }
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+
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+ /*
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+ * When setting EMMC_PHY_FUNC_CONTROL register,
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+ * SD clock should be disabled
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+ */
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+ var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
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+ var &= ~SDHCI_CLOCK_CARD_EN;
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+ sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
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+
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+ var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL);
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+ if (host->mmc->ddr_mode) {
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+ var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE;
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+ } else {
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+ var &= ~((DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) |
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+ CMD_DDR_MODE);
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+ }
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+ sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL);
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+
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+ /* Enable bus clock */
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+ var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
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+ var |= SDHCI_CLOCK_CARD_EN;
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+ sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
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+
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+ xenon_mmc_phy_init(host);
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+}
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+
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+/* Enable/Disable the Auto Clock Gating function of this slot */
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+static void xenon_mmc_set_acg(struct sdhci_host *host, bool enable)
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+{
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+ u32 var;
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+
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+ var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
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+ if (enable)
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+ var &= ~AUTO_CLKGATE_DISABLE_MASK;
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+ else
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+ var |= AUTO_CLKGATE_DISABLE_MASK;
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+
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+ sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
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+}
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+
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+#define SLOT_MASK(slot) BIT(slot)
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+
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+/* Enable specific slot */
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+static void xenon_mmc_enable_slot(struct sdhci_host *host, u8 slot)
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+{
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+ u32 var;
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+
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+ var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
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+ var |= SLOT_MASK(slot) << SLOT_ENABLE_SHIFT;
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+ sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
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+}
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+
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+/* Enable Parallel Transfer Mode */
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+static void xenon_mmc_enable_parallel_tran(struct sdhci_host *host, u8 slot)
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+{
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+ u32 var;
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+
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+ var = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);
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+ var |= SLOT_MASK(slot);
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+ sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL);
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+}
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+
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+static void xenon_mmc_disable_tuning(struct sdhci_host *host, u8 slot)
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+{
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+ u32 var;
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+
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+ /* Clear the Re-Tuning Request functionality */
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+ var = sdhci_readl(host, SDHC_SLOT_RETUNING_REQ_CTRL);
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+ var &= ~RETUNING_COMPATIBLE;
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+ sdhci_writel(host, var, SDHC_SLOT_RETUNING_REQ_CTRL);
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+
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+ /* Clear the Re-tuning Event Signal Enable */
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+ var = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
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+ var &= ~SDHCI_RETUNE_EVT_INTSIG;
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+ sdhci_writel(host, var, SDHCI_SIGNAL_ENABLE);
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+}
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+
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+/* Mask command conflict error */
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+static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
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+{
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+ u32 reg;
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+
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+ reg = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);
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+ reg |= MASK_CMD_CONFLICT_ERROR;
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+ sdhci_writel(host, reg, SDHC_SYS_EXT_OP_CTRL);
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+}
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+
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+/* Platform specific function for post set_ios configuration */
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+static void xenon_sdhci_set_ios_post(struct sdhci_host *host)
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+{
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+ struct xenon_sdhci_priv *priv = host->mmc->priv;
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+ uint speed = host->mmc->tran_speed;
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+ int pwr_18v = 0;
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+
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+ if ((sdhci_readb(host, SDHCI_POWER_CONTROL) & ~SDHCI_POWER_ON) ==
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+ SDHCI_POWER_180)
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+ pwr_18v = 1;
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+
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+ /* Set timing variable according to the configured speed */
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+ if (IS_SD(host->mmc)) {
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+ /* SD/SDIO */
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+ if (pwr_18v) {
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+ if (host->mmc->ddr_mode)
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+ priv->timing = MMC_TIMING_UHS_DDR50;
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+ else if (speed <= 25000000)
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+ priv->timing = MMC_TIMING_UHS_SDR25;
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+ else
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+ priv->timing = MMC_TIMING_UHS_SDR50;
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+ } else {
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+ if (speed <= 25000000)
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+ priv->timing = MMC_TIMING_LEGACY;
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+ else
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+ priv->timing = MMC_TIMING_SD_HS;
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+ }
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+ } else {
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+ /* eMMC */
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+ if (host->mmc->ddr_mode)
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+ priv->timing = MMC_TIMING_MMC_DDR52;
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+ else if (speed <= 26000000)
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+ priv->timing = MMC_TIMING_LEGACY;
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+ else
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+ priv->timing = MMC_TIMING_MMC_HS;
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+ }
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+
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+ /* Re-init the PHY */
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+ xenon_mmc_phy_set(host);
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+}
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+
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+/* Install a driver specific handler for post set_ios configuration */
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+static const struct sdhci_ops xenon_sdhci_ops = {
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+ .set_ios_post = xenon_sdhci_set_ios_post
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+};
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+
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+static int xenon_sdhci_probe(struct udevice *dev)
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+{
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+ struct xenon_sdhci_plat *plat = dev_get_platdata(dev);
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+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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+ struct xenon_sdhci_priv *priv = dev_get_priv(dev);
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+ struct sdhci_host *host = dev_get_priv(dev);
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+ int ret;
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+
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+ host->mmc = &plat->mmc;
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+ host->mmc->priv = host;
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+ host->mmc->dev = dev;
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+ upriv->mmc = host->mmc;
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+
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+ /* Set quirks */
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+ host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR;
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+
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+ /* Set default timing */
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+ priv->timing = MMC_TIMING_LEGACY;
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+
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+ /* Disable auto clock gating during init */
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+ xenon_mmc_set_acg(host, false);
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+
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+ /* Enable slot */
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+ xenon_mmc_enable_slot(host, XENON_MMC_SLOT_ID_HYPERION);
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+
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+ /*
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+ * Set default power on SoC PHY PAD register (currently only
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+ * available on the Armada 3700)
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+ */
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+ if (priv->pad_ctrl_reg)
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+ armada_3700_soc_pad_voltage_set(host);
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+
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+ host->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_DDR_52MHz;
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+ switch (fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width", 1)) {
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|
|
+ case 8:
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|
+ host->host_caps |= MMC_MODE_8BIT;
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+ break;
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|
+ case 4:
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+ host->host_caps |= MMC_MODE_4BIT;
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+ break;
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|
+ case 1:
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|
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+ break;
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|
|
+ default:
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|
|
+ printf("Invalid \"bus-width\" value\n");
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|
|
+ return -EINVAL;
|
|
|
+ }
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|
|
+
|
|
|
+ host->ops = &xenon_sdhci_ops;
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|
|
+
|
|
|
+ ret = sdhci_setup_cfg(&plat->cfg, host, XENON_MMC_MAX_CLK, 0);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ ret = sdhci_probe(dev);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ /* Enable parallel transfer */
|
|
|
+ xenon_mmc_enable_parallel_tran(host, XENON_MMC_SLOT_ID_HYPERION);
|
|
|
+
|
|
|
+ /* Disable tuning functionality of this slot */
|
|
|
+ xenon_mmc_disable_tuning(host, XENON_MMC_SLOT_ID_HYPERION);
|
|
|
+
|
|
|
+ /* Enable auto clock gating after init */
|
|
|
+ xenon_mmc_set_acg(host, true);
|
|
|
+
|
|
|
+ xenon_mask_cmd_conflict_err(host);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int xenon_sdhci_ofdata_to_platdata(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct sdhci_host *host = dev_get_priv(dev);
|
|
|
+ struct xenon_sdhci_priv *priv = dev_get_priv(dev);
|
|
|
+ const char *name;
|
|
|
+
|
|
|
+ host->name = dev->name;
|
|
|
+ host->ioaddr = (void *)dev_get_addr(dev);
|
|
|
+
|
|
|
+ if (of_device_is_compatible(dev, "marvell,armada-3700-sdhci"))
|
|
|
+ priv->pad_ctrl_reg = (void *)dev_get_addr_index(dev, 1);
|
|
|
+
|
|
|
+ name = fdt_getprop(gd->fdt_blob, dev->of_offset, "marvell,pad-type",
|
|
|
+ NULL);
|
|
|
+ if (name) {
|
|
|
+ if (0 == strncmp(name, "sd", 2)) {
|
|
|
+ priv->pad_type = SOC_PAD_SD;
|
|
|
+ } else if (0 == strncmp(name, "fixed-1-8v", 10)) {
|
|
|
+ priv->pad_type = SOC_PAD_FIXED_1_8V;
|
|
|
+ } else {
|
|
|
+ printf("Unsupported SOC PHY PAD ctrl type %s\n", name);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int xenon_sdhci_bind(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct xenon_sdhci_plat *plat = dev_get_platdata(dev);
|
|
|
+
|
|
|
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
|
|
|
+}
|
|
|
+
|
|
|
+static const struct udevice_id xenon_sdhci_ids[] = {
|
|
|
+ { .compatible = "marvell,armada-8k-sdhci",},
|
|
|
+ { .compatible = "marvell,armada-3700-sdhci",},
|
|
|
+ { }
|
|
|
+};
|
|
|
+
|
|
|
+U_BOOT_DRIVER(xenon_sdhci_drv) = {
|
|
|
+ .name = "xenon_sdhci",
|
|
|
+ .id = UCLASS_MMC,
|
|
|
+ .of_match = xenon_sdhci_ids,
|
|
|
+ .ofdata_to_platdata = xenon_sdhci_ofdata_to_platdata,
|
|
|
+ .ops = &sdhci_ops,
|
|
|
+ .bind = xenon_sdhci_bind,
|
|
|
+ .probe = xenon_sdhci_probe,
|
|
|
+ .priv_auto_alloc_size = sizeof(struct xenon_sdhci_priv),
|
|
|
+ .platdata_auto_alloc_size = sizeof(struct xenon_sdhci_plat),
|
|
|
+};
|