Browse Source

Merge branch 'next'

Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini 1 year ago
parent
commit
cebdfc22da
100 changed files with 11178 additions and 1653 deletions
  1. 12 31
      .azure-pipelines.yml
  2. 1 1
      .checkpatch.conf
  3. 9 26
      .gitlab-ci.yml
  4. 3 3
      Kconfig
  5. 2 0
      MAINTAINERS
  6. 18 22
      Makefile
  7. 57 220
      README
  8. 19 0
      api/Kconfig
  9. 5 2
      arch/Kconfig
  10. 20 0
      arch/Kconfig.nxp
  11. 0 3
      arch/arc/config.mk
  12. 2 2
      arch/arc/lib/cache.c
  13. 1 1
      arch/arc/lib/cpu.c
  14. 11 13
      arch/arm/Kconfig
  15. 0 8
      arch/arm/config.mk
  16. 1 1
      arch/arm/cpu/arm1176/start.S
  17. 0 8
      arch/arm/cpu/arm920t/imx/Makefile
  18. 0 76
      arch/arm/cpu/arm920t/imx/generic.c
  19. 0 86
      arch/arm/cpu/arm920t/imx/speed.c
  20. 0 100
      arch/arm/cpu/arm920t/imx/timer.c
  21. 0 1
      arch/arm/cpu/arm926ejs/Makefile
  22. 0 7
      arch/arm/cpu/arm926ejs/mx27/Makefile
  23. 0 378
      arch/arm/cpu/arm926ejs/mx27/generic.c
  24. 0 50
      arch/arm/cpu/arm926ejs/mx27/relocate.S
  25. 0 41
      arch/arm/cpu/arm926ejs/mx27/reset.c
  26. 0 166
      arch/arm/cpu/arm926ejs/mx27/timer.c
  27. 1 1
      arch/arm/cpu/arm926ejs/start.S
  28. 3 3
      arch/arm/cpu/armv7/arch_timer.c
  29. 11 0
      arch/arm/cpu/armv7/ls102xa/Kconfig
  30. 10 19
      arch/arm/cpu/armv7/ls102xa/cpu.c
  31. 2 2
      arch/arm/cpu/armv7/ls102xa/fdt.c
  32. 3 3
      arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
  33. 5 6
      arch/arm/cpu/armv7/nonsec_virt.S
  34. 26 51
      arch/arm/cpu/armv7/psci.S
  35. 5 6
      arch/arm/cpu/armv7/s5p-common/pwm.c
  36. 3 7
      arch/arm/cpu/armv7/s5p-common/timer.c
  37. 0 29
      arch/arm/cpu/armv7/s5p4418/cpu.c
  38. 2 4
      arch/arm/cpu/armv7/start.S
  39. 2 2
      arch/arm/cpu/armv7/stv0991/timer.c
  40. 2 2
      arch/arm/cpu/armv7/virt-v7.c
  41. 4 4
      arch/arm/cpu/armv7m/systick-timer.c
  42. 3 0
      arch/arm/cpu/armv8/fsl-layerscape/Kconfig
  43. 56 59
      arch/arm/cpu/armv8/fsl-layerscape/cpu.c
  44. 2 2
      arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
  45. 1 1
      arch/arm/cpu/armv8/fsl-layerscape/fdt.c
  46. 2 6
      arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
  47. 1 1
      arch/arm/cpu/armv8/fsl-layerscape/icid.c
  48. 2 2
      arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
  49. 2 2
      arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
  50. 3 3
      arch/arm/cpu/armv8/fsl-layerscape/soc.c
  51. 1 1
      arch/arm/cpu/armv8/fsl-layerscape/spl.c
  52. 4 8
      arch/arm/cpu/armv8/psci.S
  53. 2 2
      arch/arm/cpu/armv8/sec_firmware.c
  54. 3 0
      arch/arm/dts/Makefile
  55. 21 0
      arch/arm/dts/at91-sam9x60_curiosity.dts
  56. 25 0
      arch/arm/dts/at91-sama5d27_wlsom1_ek.dts
  57. 22 0
      arch/arm/dts/at91-sama5d2_icp.dts
  58. 108 0
      arch/arm/dts/at91-sama7g5ek-u-boot.dtsi
  59. 11 12
      arch/arm/dts/at91-sama7g5ek.dts
  60. 54 0
      arch/arm/dts/k3-am62-main.dtsi
  61. 28 0
      arch/arm/dts/k3-am62-mcu.dtsi
  62. 1 0
      arch/arm/dts/k3-am62.dtsi
  63. 5 0
      arch/arm/dts/k3-am625-r5-sk.dts
  64. 24 0
      arch/arm/dts/k3-am625-sk-u-boot.dtsi
  65. 354 0
      arch/arm/dts/k3-am625-sk.dts
  66. 2798 0
      arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi
  67. 2814 0
      arch/arm/dts/k3-am62a-ddr.dtsi
  68. 298 0
      arch/arm/dts/k3-am62a-main.dtsi
  69. 39 0
      arch/arm/dts/k3-am62a-mcu.dtsi
  70. 54 0
      arch/arm/dts/k3-am62a-wakeup.dtsi
  71. 122 0
      arch/arm/dts/k3-am62a.dtsi
  72. 143 0
      arch/arm/dts/k3-am62a7-r5-sk.dts
  73. 140 0
      arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
  74. 223 0
      arch/arm/dts/k3-am62a7-sk.dts
  75. 103 0
      arch/arm/dts/k3-am62a7.dtsi
  76. 8 0
      arch/arm/dts/k3-am64-mcu.dtsi
  77. 92 0
      arch/arm/dts/nuvoton-common-npcm8xx.dtsi
  78. 8 8
      arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi
  79. 129 0
      arch/arm/dts/nuvoton-npcm845-evb.dts
  80. 2007 0
      arch/arm/dts/nuvoton-npcm845-pincfg.dtsi
  81. 824 8
      arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
  82. 8 0
      arch/arm/dts/omap4-u-boot.dtsi
  83. 2 2
      arch/arm/dts/rockchip-optee.dtsi
  84. 6 0
      arch/arm/dts/s5p4418-nanopi2.dts
  85. 71 0
      arch/arm/dts/s5p4418-pinctrl.dtsi
  86. 40 0
      arch/arm/dts/s5p4418.dtsi
  87. 85 0
      arch/arm/dts/sam9x60.dtsi
  88. 124 0
      arch/arm/dts/sam9x60ek.dts
  89. 0 1
      arch/arm/dts/sama5d2.dtsi
  90. 16 11
      arch/arm/dts/sama7g5.dtsi
  91. 1 3
      arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi
  92. 1 1
      arch/arm/dts/synquacer-sc2a11-developerbox.dts
  93. 35 36
      arch/arm/dts/synquacer-sc2a11.dtsi
  94. 4 0
      arch/arm/dts/uniphier-v7-u-boot.dtsi
  95. 1 1
      arch/arm/include/asm/arch-am33xx/clock.h
  96. 6 30
      arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
  97. 0 2
      arch/arm/include/asm/arch-am33xx/hardware.h
  98. 0 60
      arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
  99. 1 4
      arch/arm/include/asm/arch-am33xx/mmc_host_def.h
  100. 0 2
      arch/arm/include/asm/arch-am33xx/mux.h

+ 12 - 31
.azure-pipelines.yml

@@ -2,7 +2,7 @@ variables:
   windows_vm: windows-2019
   ubuntu_vm: ubuntu-22.04
   macos_vm: macOS-12
-  ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20221003-17Oct2022
+  ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20221101-22Nov2022
   # Add '-u 0' options for Azure pipelines, otherwise we get "permission
   # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
   # since our $(ci_runner_image) user is not root.
@@ -30,7 +30,7 @@ stages:
           %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel libgnutls-devel libutil-linux-devel"
         displayName: 'Install Toolchain'
       - script: |
-          echo make tools-only_defconfig tools-only NO_SDL=1 > build-tools.sh
+          echo make tools-only_defconfig tools-only > build-tools.sh
           %CD:~0,2%\msys64\usr\bin\bash -lc "bash build-tools.sh"
         displayName: 'Build Host Tools'
         env:
@@ -47,43 +47,24 @@ stages:
       - script: brew install make ossp-uuid
         displayName: Brew install dependencies
       - script: |
-          gmake tools-only_config tools-only NO_SDL=1 \
+          gmake tools-only_config tools-only \
             HOSTCFLAGS="-I/usr/local/opt/openssl@1.1/include" \
             HOSTLDFLAGS="-L/usr/local/opt/openssl@1.1/lib" \
             -j$(sysctl -n hw.logicalcpu)
         displayName: 'Perform tools-only build'
 
-  - job: check_for_migrated_symbols_in_board_header
-    displayName: 'Check for migrated symbols in board header'
+  - job: check_for_new_CONFIG_symbols_outside_Kconfig
+    displayName: 'Check for new CONFIG symbols outside Kconfig'
     pool:
       vmImage: $(ubuntu_vm)
     container:
       image: $(ci_runner_image)
       options: $(container_option)
     steps:
-      - script: |
-          KSYMLST=`mktemp`
-          KUSEDLST=`mktemp`
-          RET=0
-          cat `find . -name "Kconfig*"` | \
-             sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
-             -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
-             | sort -u > $KSYMLST
-          for CFG in `find include/configs -name "*.h"`; do
-             (grep '#define[[:blank:]]CONFIG_' $CFG | \
-                sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' ; \
-                grep '#undef[[:blank:]]CONFIG_' $CFG | \
-                sed -n 's/#undef.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p') | \
-                sort -u > ${KUSEDLST} || true
-             NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} | \
-                cut -d , -f 3`
-             if [[ $NUM -ne 0 ]]; then
-                echo "Unmigrated symbols found in $CFG:"
-                comm -12 ${KSYMLST} ${KUSEDLST}
-                RET=1
-             fi
-          done
-          exit $RET
+      # If grep succeeds and finds a match the test fails as we should
+      # have no matches.
+      - script: git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_'
+                  include/configs `find arch -name config.h` && exit 1 || exit 0
 
   - job: cppcheck
     displayName: 'Static code analysis with cppcheck'
@@ -204,7 +185,7 @@ stages:
       options: $(container_option)
     steps:
       - script: |
-          export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH
+          export PATH=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin:$PATH
           test/nokia_rx51_test.sh
 
   - job: pylint
@@ -242,7 +223,7 @@ stages:
           TEST_PY_BD: "sandbox"
         sandbox_clang:
           TEST_PY_BD: "sandbox"
-          OVERRIDE: "-O clang-13"
+          OVERRIDE: "-O clang-14"
         sandbox_nolto:
           TEST_PY_BD: "sandbox"
           BUILD_ENV: "NO_LTO=1"
@@ -488,7 +469,7 @@ stages:
           OVERRIDE: "-a ASAN"
         sandbox_clang_asan:
           BUILDMAN: "sandbox"
-          OVERRIDE: "-O clang-13 -a ASAN"
+          OVERRIDE: "-O clang-14 -a ASAN"
         samsung_socfpga:
           BUILDMAN: "samsung socfpga"
         sun4i:

+ 1 - 1
.checkpatch.conf

@@ -4,7 +4,7 @@
 # Temporary for false positive in checkpatch
 --ignore COMPLEX_MACRO
 
-# For CONFIG_SYS_I2C_NOPROBES
+# For CFG_SYS_I2C_NOPROBES
 --ignore MULTISTATEMENT_MACRO_USE_DO_WHILE
 
 # For simple_strtoul

+ 9 - 26
.gitlab-ci.yml

@@ -2,7 +2,7 @@
 
 # Grab our configured image.  The source for this is found
 # in the u-boot tree at tools/docker/Dockerfile
-image: trini/u-boot-gitlab-ci-runner:jammy-20221003-17Oct2022
+image: trini/u-boot-gitlab-ci-runner:jammy-20221101-22Nov2022
 
 # We run some tests in different order, to catch some failures quicker.
 stages:
@@ -124,31 +124,14 @@ build all other platforms:
         exit $ret;
       fi;
 
-check for migrated symbols in board header:
+check for new CONFIG symbols outside Kconfig:
   stage: testsuites
   script:
-    - KSYMLST=`mktemp`;
-      KUSEDLST=`mktemp`;
-      RET=0;
-      cat `find . -name "Kconfig*"` |
-         sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
-         -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
-         | sort -u > $KSYMLST;
-      for CFG in `find include/configs -name "*.h"`; do
-         (grep '#define[[:blank:]]CONFIG_' $CFG |
-            sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' ;
-            grep '#undef[[:blank:]]CONFIG_' $CFG |
-            sed -n 's/#undef.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p') |
-            sort -u > ${KUSEDLST} || true;
-         NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} |
-            cut -d , -f 3`;
-         if [[ $NUM -ne 0 ]]; then
-            echo "Unmigrated symbols found in $CFG:";
-            comm -12 ${KSYMLST} ${KUSEDLST};
-            RET=1;
-         fi;
-      done;
-      exit $RET
+    - git config --global --add safe.directory "${CI_PROJECT_DIR}"
+    # If grep succeeds and finds a match the test fails as we should
+    # have no matches.
+    - git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_'
+        include/configs `find arch -name config.h` && exit 1 || exit 0
 
 # QA jobs for code analytics
 # static code analysis with cppcheck (we can add --enable=all later)
@@ -225,7 +208,7 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites:
 Run tests for Nokia RX-51 (aka N900):
   stage: testsuites
   script:
-    - export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH;
+    - export PATH=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin:$PATH;
       test/nokia_rx51_test.sh
 
 # Check for any pylint regressions
@@ -256,7 +239,7 @@ sandbox test.py:
 sandbox with clang test.py:
   variables:
     TEST_PY_BD: "sandbox"
-    OVERRIDE: "-O clang-13"
+    OVERRIDE: "-O clang-14"
   <<: *buildman_and_testpy_dfn
 
 sandbox without LTO test.py:

+ 3 - 3
Kconfig

@@ -264,8 +264,8 @@ config HAS_CUSTOM_SYS_INIT_SP_ADDR
 	default y if TFABOOT
 	help
 	  Typically, we use an initial stack pointer address that is calculated
-	  by taking the statically defined CONFIG_SYS_INIT_RAM_ADDR, adding the
-	  statically defined CONFIG_SYS_INIT_RAM_SIZE and then subtracting the
+	  by taking the statically defined CFG_SYS_INIT_RAM_ADDR, adding the
+	  statically defined CFG_SYS_INIT_RAM_SIZE and then subtracting the
 	  build-time constant of GENERATED_GBL_DATA_SIZE.  On MIPS a different
 	  but statica calculation is performed.  However, some platforms will
 	  take a different approach.  Say Y here to define the address statically
@@ -333,7 +333,7 @@ config SPL_SYS_MALLOC_F_LEN
 	  particular needs this to operate, so that it can allocate the
 	  initial serial device and any others that are needed.
 
-	  It is possible to enable CONFIG_SYS_SPL_MALLOC_START to start a new
+	  It is possible to enable CFG_SYS_SPL_MALLOC_START to start a new
 	  malloc() region in SDRAM once it is inited.
 
 config TPL_SYS_MALLOC_F_LEN

+ 2 - 0
MAINTAINERS

@@ -409,6 +409,7 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-atmel.git
 F:	arch/arm/mach-at91/
 F:	board/atmel/
 F:	drivers/cpu/at91_cpu.c
+F:	drivers/memory/atmel-ebi.c
 F:	drivers/misc/microchip_flexcom.c
 F:	drivers/timer/atmel_tcb_timer.c
 F:	include/dt-bindings/mfd/atmel-flexcom.h
@@ -436,6 +437,7 @@ F:	drivers/gpio/nx_gpio.c
 F:	drivers/i2c/nx_i2c.c
 F:	drivers/mmc/nexell_dw_mmc_dm.c
 F:	drivers/pinctrl/nexell/
+F:	drivers/serial/serial_s5p4418_pl011.c
 F:	drivers/video/nexell/
 F:	drivers/video/nexell_display.c
 F:	include/configs/s5p4418_nanopi2.h

+ 18 - 22
Makefile

@@ -761,10 +761,10 @@ KBUILD_CFLAGS += $(call cc-disable-warning, maybe-uninitialized)
 # change __FILE__ to the relative path from the srctree
 KBUILD_CFLAGS	+= $(call cc-option,-fmacro-prefix-map=$(srctree)/=)
 
-KBUILD_CFLAGS	+= -g
+KBUILD_CFLAGS	+= -gdwarf-4
 # $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
 # option to the assembler.
-KBUILD_AFLAGS	+= -g
+KBUILD_AFLAGS	+= -gdwarf-4
 
 # Report stack usage if supported
 # ARC tools based on GCC 7.1 has an issue with stack usage
@@ -806,6 +806,8 @@ KBUILD_CPPFLAGS += $(KCPPFLAGS)
 KBUILD_AFLAGS += $(KAFLAGS)
 KBUILD_CFLAGS += $(KCFLAGS)
 
+KBUILD_LDFLAGS  += $(call ld-option,--no-warn-rwx-segments)
+
 KBUILD_HOSTCFLAGS += $(if $(CONFIG_TOOLS_DEBUG),-g)
 
 # Use UBOOTINCLUDE when you must reference the include/ directory.
@@ -1073,10 +1075,6 @@ cmd_lzma = lzma -c -z -k -9 $< > $@
 
 cfg: u-boot.cfg
 
-quiet_cmd_cfgcheck = CFGCHK  $2
-cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
-		$(srctree)/scripts/config_whitelist.txt $(srctree)
-
 quiet_cmd_ofcheck = OFCHK   $2
 cmd_ofcheck = $(srctree)/scripts/check-of.sh $2 \
 		$(srctree)/scripts/of_allowlist.txt
@@ -1138,16 +1136,12 @@ endif
 	$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
 		$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
 	$(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY))
-	@# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which
+	@# CFG_SYS_TIMER_RATE has brackets in it for some boards which
 	@# confuses this rule. Use if() to send just a single character which
 	@# is enable to tell 'deprecated' that one of these symbols exists
-	$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CONFIG_SYS_TIMER_RATE)$(CONFIG_SYS_TIMER_COUNTER)),x))
+	$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x))
 	$(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL))
 	$(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI))
-	@# Check that this build does not use CONFIG options that we do not
-	@# know about unless they are in Kconfig. All the existing CONFIG
-	@# options are whitelisted, so new ones should not be added.
-	$(call cmd,cfgcheck,u-boot.cfg)
 	@# Check that this build does not override OF_HAS_PRIOR_STAGE by
 	@# disabling OF_BOARD.
 	$(call cmd,ofcheck,$(KCONFIG_CONFIG))
@@ -1361,8 +1355,8 @@ u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
 # U-Boot entry point, needed for booting of full-blown U-Boot
 # from the SPL U-Boot version.
 #
-ifndef CONFIG_SYS_UBOOT_START
-CONFIG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
+ifndef CFG_SYS_UBOOT_START
+CFG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
 endif
 
 # Boards with more complex image requirements can provide an .its source file
@@ -1387,7 +1381,7 @@ endif
 
 ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
 	-p $(CONFIG_FIT_EXTERNAL_OFFSET) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \
@@ -1395,10 +1389,10 @@ MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST)))
 else
 MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
 endif
@@ -1429,7 +1423,7 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
 UBOOT_BIN := u-boot.bin
 
 MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \
-	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
+	-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
 	-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
 
 u-boot.bin.lzma: u-boot.bin FORCE
@@ -2439,11 +2433,13 @@ endif
 	$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
 
 quiet_cmd_genenv = GENENV  $@
-cmd_genenv = $(OBJCOPY) --dump-section .rodata.default_environment=$@ env/common.o; \
-	sed --in-place -e 's/\x00/\x0A/g' $@; sed --in-place -e '/^\s*$$/d' $@; \
-	sort --field-separator== -k1,1 --stable $@ -o $@
+cmd_genenv = \
+	$(objtree)/tools/printinitialenv | \
+	sed -e '/^\s*$$/d' | \
+	sort --field-separator== -k1,1 --stable -o $@
 
-u-boot-initial-env: u-boot.bin
+u-boot-initial-env: $(env_h) FORCE
+	$(Q)$(MAKE) $(build)=tools $(objtree)/tools/printinitialenv
 	$(call if_changed,genenv)
 
 # Consistency checks

+ 57 - 220
README

@@ -341,7 +341,7 @@ The following options need to be configured:
 
 		CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
 		Physical address from the view of DDR controllers. It is the
-		same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
+		same as CFG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
 		it could be different for ARM SoCs.
 
 - MIPS CPU options:
@@ -352,7 +352,7 @@ The following options need to be configured:
 		be swapped if a flash programmer is used.
 
 - ARM options:
-		CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+		CFG_SYS_EXCEPTION_VECTORS_HIGH
 
 		Select high exception vectors of the ARM core, e.g., do not
 		clear the V bit of the c1 register of CP15.
@@ -373,12 +373,6 @@ The following options need to be configured:
 		such as ARM architectural timer initialization.
 
 - Linux Kernel Interface:
-		CONFIG_MEMSIZE_IN_BYTES		[relevant for MIPS only]
-
-		When transferring memsize parameter to Linux, some versions
-		expect it to be in bytes, others in MB.
-		Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
-
 		CONFIG_OF_LIBFDT
 
 		New kernel versions are expecting firmware settings to be
@@ -415,16 +409,16 @@ The following options need to be configured:
 		the defaults discussed just above.
 
 - Cache Configuration for ARM:
-		CONFIG_SYS_PL310_BASE - Physical base address of PL310
+		CFG_SYS_PL310_BASE - Physical base address of PL310
 					controller register space
 
 - Serial Ports:
-		CONFIG_PL011_CLOCK
+		CFG_PL011_CLOCK
 
 		If you have Amba PrimeCell PL011 UARTs, set this variable to
 		the clock speed of the UARTs.
 
-		CONFIG_PL01x_PORTS
+		CFG_PL01x_PORTS
 
 		If you have Amba PrimeCell PL010 or PL011 UARTs on your board,
 		define this to a list of base addresses for each (supported)
@@ -460,33 +454,8 @@ The following options need to be configured:
 		to 0 disables calling WATCHDOG_RESET() from the timer
 		interrupt.
 
-- Real-Time Clock:
-
-		When CONFIG_CMD_DATE is selected, the type of the RTC
-		has to be selected, too. Define exactly one of the
-		following options:
-
-		CONFIG_RTC_PCF8563	- use Philips PCF8563 RTC
-		CONFIG_RTC_MC13XXX	- use MC13783 or MC13892 RTC
-		CONFIG_RTC_MC146818	- use MC146818 RTC
-		CONFIG_RTC_DS1307	- use Maxim, Inc. DS1307 RTC
-		CONFIG_RTC_DS1337	- use Maxim, Inc. DS1337 RTC
-		CONFIG_RTC_DS1338	- use Maxim, Inc. DS1338 RTC
-		CONFIG_RTC_DS1339	- use Maxim, Inc. DS1339 RTC
-		CONFIG_RTC_DS164x	- use Dallas DS164x RTC
-		CONFIG_RTC_ISL1208	- use Intersil ISL1208 RTC
-		CONFIG_RTC_MAX6900	- use Maxim, Inc. MAX6900 RTC
-		CONFIG_RTC_DS1337_NOOSC	- Turn off the OSC output for DS1337
-		CONFIG_SYS_RV3029_TCR	- enable trickle charger on
-					  RV3029 RTC.
-
-		Note that if the RTC uses I2C, then the I2C interface
-		must also be configured. See I2C Support, below.
-
 - GPIO Support:
-		CONFIG_PCA953X		- use NXP's PCA953X series I2C GPIO
-
-		The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
+		The CFG_SYS_I2C_PCA953X_WIDTH option specifies a list of
 		chip-ngpio pairs that tell the PCA953X driver the number of
 		pins supported by a particular chip.
 
@@ -572,13 +541,13 @@ The following options need to be configured:
 		CONFIG_SH_ETHER
 		Support for Renesas on-chip Ethernet controller
 
-			CONFIG_SH_ETHER_USE_PORT
+			CFG_SH_ETHER_USE_PORT
 			Define the number of ports to be used
 
-			CONFIG_SH_ETHER_PHY_ADDR
+			CFG_SH_ETHER_PHY_ADDR
 			Define the ETH PHY's address
 
-			CONFIG_SH_ETHER_CACHE_WRITEBACK
+			CFG_SH_ETHER_CACHE_WRITEBACK
 			If this option is set, the driver enables cache flush.
 
 - TPM Support:
@@ -610,11 +579,6 @@ The following options need to be configured:
 		Support for generic parallel port TPM devices. Only one device
 		per system is supported at this time.
 
-			CONFIG_TPM_TIS_BASE_ADDRESS
-			Base address where the generic TPM device is mapped
-			to. Contemporary x86 systems usually map it at
-			0xfed40000.
-
 		CONFIG_TPM
 		Define this to enable the TPM support library which provides
 		functional interfaces to some TPM commands.
@@ -654,21 +618,6 @@ The following options need to be configured:
 		variable usbtty to be cdc_acm should suffice. The following
 		might be defined in YourBoardName.h
 
-			CONFIG_USB_DEVICE
-			Define this to build a UDC device
-
-			CONFIG_USB_TTY
-			Define this to have a tty type of device available to
-			talk to the UDC device
-
-			CONFIG_USBD_HS
-			Define this to enable the high speed support for usb
-			device and usbtty. If this feature is enabled, a routine
-			int is_usbd_high_speed(void)
-			also needs to be defined by the driver to dynamically poll
-			whether the enumeration has succeded at high speed or full
-			speed.
-
 		If you have a USB-IF assigned VendorID then you may wish to
 		define your own vendor specific values either in BoardName.h
 		or directly in usbd_vendor_info.h. If you don't define
@@ -766,38 +715,6 @@ The following options need to be configured:
 		Some PHY like Intel LXT971A need extra delay after
 		command issued before MII status register can be read
 
-- IP address:
-		CONFIG_IPADDR
-
-		Define a default value for the IP address to use for
-		the default Ethernet interface, in case this is not
-		determined through e.g. bootp.
-		(Environment variable "ipaddr")
-
-- Server IP address:
-		CONFIG_SERVERIP
-
-		Defines a default value for the IP address of a TFTP
-		server to contact when using the "tftboot" command.
-		(Environment variable "serverip")
-
-- Gateway IP address:
-		CONFIG_GATEWAYIP
-
-		Defines a default value for the IP address of the
-		default router where packets to other networks are
-		sent to.
-		(Environment variable "gatewayip")
-
-- Subnet mask:
-		CONFIG_NETMASK
-
-		Defines a default value for the subnet mask (or
-		routing prefix) which is used to determine if an IP
-		address belongs to the local subnet or needs to be
-		forwarded through a router.
-		(Environment variable "netmask")
-
 - BOOTP Recovery Mode:
 		CONFIG_BOOTP_RANDOM_DELAY
 
@@ -923,26 +840,26 @@ The following options need to be configured:
 		with a list of GPIO LEDs that have inverted polarity.
 
 - I2C Support:
-		CONFIG_SYS_NUM_I2C_BUSES
+		CFG_SYS_NUM_I2C_BUSES
 		Hold the number of i2c buses you want to use.
 
-		CONFIG_SYS_I2C_DIRECT_BUS
+		CFG_SYS_I2C_DIRECT_BUS
 		define this, if you don't use i2c muxes on your hardware.
-		if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
+		if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
 		omit this define.
 
-		CONFIG_SYS_I2C_MAX_HOPS
+		CFG_SYS_I2C_MAX_HOPS
 		define how many muxes are maximal consecutively connected
 		on one i2c bus. If you not use i2c muxes, omit this
 		define.
 
-		CONFIG_SYS_I2C_BUSES
+		CFG_SYS_I2C_BUSES
 		hold a list of buses you want to use, only used if
-		CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
-		a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
-		CONFIG_SYS_NUM_I2C_BUSES = 9:
+		CFG_SYS_I2C_DIRECT_BUS is not defined, for example
+		a board with CFG_SYS_I2C_MAX_HOPS = 1 and
+		CFG_SYS_NUM_I2C_BUSES = 9:
 
-		 CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP}}, \
+		 CFG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \
 					{0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \
@@ -1038,32 +955,24 @@ The following options need to be configured:
 		You should define these to the GPIO value as given directly to
 		the generic GPIO functions.
 
-		CONFIG_I2C_MULTI_BUS
+		CFG_I2C_MULTI_BUS
 
 		This option allows the use of multiple I2C buses, each of which
 		must have a controller.	 At any point in time, only one bus is
 		active.	 To switch to a different bus, use the 'i2c dev' command.
 		Note that bus numbering is zero-based.
 
-		CONFIG_SYS_I2C_NOPROBES
+		CFG_SYS_I2C_NOPROBES
 
 		This option specifies a list of I2C devices that will be skipped
-		when the 'i2c probe' command is issued.	 If CONFIG_I2C_MULTI_BUS
-		is set, specify a list of bus-device pairs.  Otherwise, specify
-		a 1D array of device addresses
+		when the 'i2c probe' command is issued.
 
 		e.g.
-			#undef	CONFIG_I2C_MULTI_BUS
-			#define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
+			#define CFG_SYS_I2C_NOPROBES {0x50,0x68}
 
 		will skip addresses 0x50 and 0x68 on a board with one I2C bus
 
-			#define CONFIG_I2C_MULTI_BUS
-			#define CONFIG_SYS_I2C_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
-
-		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
-
-		CONFIG_SYS_RTC_BUS_NUM
+		CFG_SYS_RTC_BUS_NUM
 
 		If defined, then this indicates the I2C bus number for the RTC.
 		If not defined, then U-Boot assumes that RTC is on I2C bus 0.
@@ -1109,7 +1018,7 @@ The following options need to be configured:
 		will require a board or device specific function to
 		be written.
 
-		CONFIG_FPGA_DELAY
+		CFG_FPGA_DELAY
 
 		If defined, a function that provides delays in the FPGA
 		configuration driver.
@@ -1121,19 +1030,19 @@ The following options need to be configured:
 		configuration if the INIT_B line goes low (which
 		indicated a CRC error).
 
-		CONFIG_SYS_FPGA_WAIT_INIT
+		CFG_SYS_FPGA_WAIT_INIT
 
 		Maximum time to wait for the INIT_B line to de-assert
 		after PROB_B has been de-asserted during a Virtex II
 		FPGA configuration sequence. The default time is 500
 		ms.
 
-		CONFIG_SYS_FPGA_WAIT_BUSY
+		CFG_SYS_FPGA_WAIT_BUSY
 
 		Maximum time to wait for BUSY to de-assert during
 		Virtex II FPGA configuration. The default is 5 ms.
 
-		CONFIG_SYS_FPGA_WAIT_CONFIG
+		CFG_SYS_FPGA_WAIT_CONFIG
 
 		Time to wait after FPGA configuration. The default is
 		200 ms.
@@ -1154,24 +1063,17 @@ The following options need to be configured:
 		completely disabled. Anybody can change or delete
 		these parameters.
 
-		Alternatively, if you define _both_ an ethaddr in the
-		default env _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
-		Ethernet address is installed in the environment,
-		which can be changed exactly ONCE by the user. [The
-		serial# is unaffected by this, i. e. it remains
-		read-only.]
-
 		The same can be accomplished in a more flexible way
 		for any variable by configuring the type of access
 		to allow for those variables in the ".flags" variable
-		or define CONFIG_ENV_FLAGS_LIST_STATIC.
+		or define CFG_ENV_FLAGS_LIST_STATIC.
 
 - Protected RAM:
-		CONFIG_PRAM
+		CFG_PRAM
 
 		Define this variable to enable the reservation of
 		"protected RAM", i. e. RAM which is not overwritten
-		by U-Boot. Define CONFIG_PRAM to hold the number of
+		by U-Boot. Define CFG_PRAM to hold the number of
 		kB you want to reserve for pRAM. You can overwrite
 		this default value by defining an environment
 		variable "pram" to the number of kB you want to
@@ -1222,7 +1124,7 @@ The following options need to be configured:
 		symbols.
 
 - Default Environment:
-		CONFIG_EXTRA_ENV_SETTINGS
+		CFG_EXTRA_ENV_SETTINGS
 
 		Define this to contain any number of null terminated
 		strings (variable = value pairs) that will be part of
@@ -1231,7 +1133,7 @@ The following options need to be configured:
 		For example, place something like this in your
 		board's config file:
 
-		#define CONFIG_EXTRA_ENV_SETTINGS \
+		#define CFG_EXTRA_ENV_SETTINGS \
 			"myvar1=value1\0" \
 			"myvar2=value2\0"
 
@@ -1256,13 +1158,6 @@ The following options need to be configured:
 		this is instead controlled by the value of
 		/config/load-environment.
 
-		CONFIG_STANDALONE_LOAD_ADDR
-
-		This option defines a board specific value for the
-		address where standalone program gets loaded, thus
-		overwriting the architecture dependent default
-		settings.
-
 - Automatic software updates via TFTP server
 		CONFIG_UPDATE_TFTP
 		CONFIG_UPDATE_TFTP_CNT_MAX
@@ -1364,24 +1259,20 @@ The following options need to be configured:
 		CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
 		CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
 		CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
-		CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
-		CONFIG_SYS_NAND_ECCBYTES
+		CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE,
+		CFG_SYS_NAND_ECCBYTES
 		Defines the size and behavior of the NAND that SPL uses
 		to read U-Boot
 
-		CONFIG_SYS_NAND_U_BOOT_DST
+		CFG_SYS_NAND_U_BOOT_DST
 		Location in memory to load U-Boot to
 
-		CONFIG_SYS_NAND_U_BOOT_SIZE
+		CFG_SYS_NAND_U_BOOT_SIZE
 		Size of image to load
 
-		CONFIG_SYS_NAND_U_BOOT_START
+		CFG_SYS_NAND_U_BOOT_START
 		Entry point in loaded image to jump to
 
-		CONFIG_SYS_NAND_HW_ECC_OOBFIRST
-		Define this if you need to first read the OOB and then the
-		data. This is used, for example, on davinci platforms.
-
 		CONFIG_SPL_RAM_DEVICE
 		Support for running image already present in ram, in SPL binary
 
@@ -1434,22 +1325,22 @@ Configuration Settings:
 - CONFIG_SYS_PROMPT:	This is what U-Boot prints on the console to
 		prompt for user input.
 
-- CONFIG_SYS_BAUDRATE_TABLE:
+- CFG_SYS_BAUDRATE_TABLE:
 		List of legal baudrate settings for this board.
 
-- CONFIG_SYS_MEM_RESERVE_SECURE
+- CFG_SYS_MEM_RESERVE_SECURE
 		Only implemented for ARMv8 for now.
-		If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
+		If defined, the size of CFG_SYS_MEM_RESERVE_SECURE memory
 		is substracted from total RAM and won't be reported to OS.
 		This memory can be used as secure memory. A variable
 		gd->arch.secure_ram is used to track the location. In systems
 		the RAM base is not zero, or RAM is divided into banks,
 		this variable needs to be recalcuated to get the address.
 
-- CONFIG_SYS_SDRAM_BASE:
+- CFG_SYS_SDRAM_BASE:
 		Physical start address of SDRAM. _Must_ be 0 here.
 
-- CONFIG_SYS_FLASH_BASE:
+- CFG_SYS_FLASH_BASE:
 		Physical start address of Flash memory.
 
 - CONFIG_SYS_MALLOC_LEN:
@@ -1473,16 +1364,16 @@ Configuration Settings:
 		boards which do not use the full malloc in SPL (which is
 		enabled with CONFIG_SYS_SPL_MALLOC).
 
-- CONFIG_SYS_BOOTMAPSZ:
+- CFG_SYS_BOOTMAPSZ:
 		Maximum size of memory mapped by the startup code of
 		the Linux kernel; all data that must be processed by
 		the Linux kernel (bd_info, boot arguments, FDT blob if
 		used) must be put below this limit, unless "bootm_low"
 		environment variable is defined and non-zero. In such case
 		all data for the Linux kernel must be between "bootm_low"
-		and "bootm_low" + CONFIG_SYS_BOOTMAPSZ.	 The environment
+		and "bootm_low" + CFG_SYS_BOOTMAPSZ.	 The environment
 		variable "bootm_mapsize" will override the value of
-		CONFIG_SYS_BOOTMAPSZ.  If CONFIG_SYS_BOOTMAPSZ is undefined,
+		CFG_SYS_BOOTMAPSZ.  If CFG_SYS_BOOTMAPSZ is undefined,
 		then the value in "bootm_size" will be used instead.
 
 - CONFIG_SYS_BOOT_GET_CMDLINE:
@@ -1513,26 +1404,8 @@ Configuration Settings:
 - CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 		Use buffered writes to flash.
 
-- CONFIG_FLASH_SPANSION_S29WS_N
-		s29ws-n MirrorBit flash has non-standard addresses for buffered
-		write commands.
-
-- CONFIG_FLASH_SHOW_PROGRESS
-		If defined (must be an integer), print out countdown
-		digits and dots.  Recommended value: 45 (9..1) for 80
-		column displays, 15 (3..1) for 40 column displays.
-
-- CONFIG_FLASH_VERIFY
-		If defined, the content of the flash (destination) is compared
-		against the source after the write operation. An error message
-		will be printed when the contents are not identical.
-		Please note that this option is useless in nearly all cases,
-		since such flash programming errors usually are detected earlier
-		while unprotecting/erasing/programming. Please only enable
-		this option if you really know what you are doing.
-
 - CONFIG_ENV_FLAGS_LIST_DEFAULT
-- CONFIG_ENV_FLAGS_LIST_STATIC
+- CFG_ENV_FLAGS_LIST_STATIC
 	Enable validation of the values given to environment variables when
 	calling env set.  Variables can be restricted to only decimal,
 	hexadecimal, or boolean.  If CONFIG_CMD_NET is also defined,
@@ -1563,7 +1436,7 @@ Configuration Settings:
 		Define this to a list (string) to define the ".flags"
 		environment variable in the default or embedded environment.
 
-	- CONFIG_ENV_FLAGS_LIST_STATIC
+	- CFG_ENV_FLAGS_LIST_STATIC
 		Define this to a list (string) to define validation that
 		should be done if an entry is not found in the ".flags"
 		environment variable.  To override a setting in the static
@@ -1578,11 +1451,6 @@ The following definitions that deal with the placement and management
 of environment data (variable area); in general, we support the
 following configurations:
 
-- CONFIG_BUILD_ENVCRC:
-
-	Builds up envcrc with the target environment so that external utils
-	may easily extract it and embed it in final U-Boot images.
-
 BE CAREFUL! The first access to the environment happens quite early
 in U-Boot initialization (when we try to get the setting of for the
 console baudrate). You *MUST* have mapped your NVRAM area then, or
@@ -1623,13 +1491,6 @@ use the "saveenv" command to store a valid environment.
 - CONFIG_SYS_FAULT_MII_ADDR:
 		MII address of the PHY to check for the Ethernet link state.
 
-- CONFIG_NS16550_MIN_FUNCTIONS:
-		Define this if you desire to only have use of the NS16550_init
-		and NS16550_putc functions for the serial driver located at
-		drivers/serial/ns16550.c.  This option is useful for saving
-		space for already greatly restricted images, including but not
-		limited to NAND_SPL configurations.
-
 - CONFIG_DISPLAY_BOARDINFO
 		Display information about the board that U-Boot is running on
 		when U-Boot starts up. The board function checkboard() is called
@@ -1650,11 +1511,11 @@ Low Level (hardware related) configuration options:
 		Default (power-on reset) physical address of CCSR on Freescale
 		PowerPC SOCs.
 
-- CONFIG_SYS_CCSRBAR:
+- CFG_SYS_CCSRBAR:
 		Virtual address of CCSR.  On a 32-bit build, this is typically
 		the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
 
-- CONFIG_SYS_CCSRBAR_PHYS:
+- CFG_SYS_CCSRBAR_PHYS:
 		Physical address of CCSR.  CCSR can be relocated to a new
 		physical address, if desired.  In this case, this macro should
 		be set to that address.	 Otherwise, it should be set to the
@@ -1662,17 +1523,17 @@ Low Level (hardware related) configuration options:
 		is typically relocated on 36-bit builds.  It is recommended
 		that this macro be defined via the _HIGH and _LOW macros:
 
-		#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH
-			* 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW)
+		#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH
+			* 1ull) << 32 | CFG_SYS_CCSRBAR_PHYS_LOW)
 
-- CONFIG_SYS_CCSRBAR_PHYS_HIGH:
-		Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS.	This value is typically
+- CFG_SYS_CCSRBAR_PHYS_HIGH:
+		Bits 33-36 of CFG_SYS_CCSRBAR_PHYS.	This value is typically
 		either 0 (32-bit build) or 0xF (36-bit build).	This macro is
 		used in assembly code, so it must not contain typecasts or
 		integer size suffixes (e.g. "ULL").
 
-- CONFIG_SYS_CCSRBAR_PHYS_LOW:
-		Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS.  This macro is
+- CFG_SYS_CCSRBAR_PHYS_LOW:
+		Lower 32-bits of CFG_SYS_CCSRBAR_PHYS.  This macro is
 		used in assembly code, so it must not contain typecasts or
 		integer size suffixes (e.g. "ULL").
 
@@ -1680,7 +1541,7 @@ Low Level (hardware related) configuration options:
 		DO NOT CHANGE unless you know exactly what you're
 		doing! (11-4) [MPC8xx systems only]
 
-- CONFIG_SYS_INIT_RAM_ADDR:
+- CFG_SYS_INIT_RAM_ADDR:
 
 		Start address of memory area that can be used for
 		initial data and stack; please note that this must be
@@ -1698,18 +1559,6 @@ Low Level (hardware related) configuration options:
 - CONFIG_SYS_OR_TIMING_SDRAM:
 		SDRAM timing
 
-- CONFIG_SYS_SRIO:
-		Chip has SRIO or not
-
-- CONFIG_SRIO1:
-		Board has SRIO 1 port available
-
-- CONFIG_SRIO2:
-		Board has SRIO 2 port available
-
-- CONFIG_SRIO_PCIE_BOOT_MASTER
-		Board can support master function for Boot from SRIO and PCIE
-
 - CONFIG_SYS_SRIOn_MEM_VIRT:
 		Virtual Address of SRIO port 'n' memory region
 
@@ -1731,13 +1580,6 @@ Low Level (hardware related) configuration options:
 		Sets the EBC0_CFG register for the NDFC. If not defined
 		a default value will be used.
 
-- CONFIG_SPD_EEPROM
-		Get DDR timing information from an I2C EEPROM. Common
-		with pluggable memory modules such as SODIMMs
-
-  SPD_EEPROM_ADDRESS
-		I2C address of the SPD EEPROM
-
 - CONFIG_SYS_SPD_BUS_NUM
 		If SPD EEPROM is on an I2C bus other than the first
 		one, specify here. Note that the value must resolve
@@ -1810,11 +1652,6 @@ Low Level (hardware related) configuration options:
 		If defined, the x86 reset vector code is included. This is not
 		needed when U-Boot is running from Coreboot.
 
-- CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
-		Option to disable subpage write in NAND driver
-		driver that uses this:
-		drivers/mtd/nand/raw/davinci_nand.c
-
 Freescale QE/FMAN Firmware Support:
 -----------------------------------
 
@@ -2766,7 +2603,7 @@ locked as (mis-) used as memory, etc.
 	cause you grief during the initial boot! It is frequently not
 	used.
 
-	CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
+	CFG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
 	with your processor/board/system design. The default value
 	you will find in any recent u-boot distribution in
 	walnut.h should work for you. I'd set it to a value larger

+ 19 - 0
api/Kconfig

@@ -11,3 +11,22 @@ config SYS_MMC_MAX_DEVICE
 	default 1
 
 endmenu
+
+config STANDALONE_LOAD_ADDR
+	hex "Address in memory to link standalone applications to"
+	default 0xffffffff80200000 if MIPS && 64BIT
+	default 0x8c000000 if SH
+	default 0x82000000 if ARC
+	default 0x80f00000 if MICROBLAZE
+	default 0x80300000 if ARCH_OMAP2PLUS || FSL_LSCH2 || FSL_LSCH3
+	default 0x80200000 if MIPS && 32BIT
+	default 0x0c100000 if ARM
+	default 0x02000000 if NIOS2
+	default 0x00040000 if PPC || X86
+	default 0x00020000 if M68K
+	default 0x0 if RISCV
+	default SYS_LOAD_ADDR
+	help
+	  This option defines a board specific value for the address where
+	  standalone program gets loaded, thus overwriting the architecture
+	  dependent default settings.

+ 5 - 2
arch/Kconfig

@@ -113,7 +113,6 @@ config RISCV
 	select DM
 	imply SPL_SEPARATE_BSS if SPL
 	imply DM_SERIAL
-	imply DM_ETH
 	imply DM_EVENT
 	imply DM_MMC
 	imply DM_SPI
@@ -146,6 +145,7 @@ config SANDBOX
 	select DM_SPI
 	select DM_SPI_FLASH
 	select GZIP_COMPRESSED
+	select IO_TRACE
 	select LZO
 	select OF_BOARD_SETUP
 	select PCI_ENDPOINT
@@ -240,7 +240,6 @@ config X86
 	imply CMD_SF
 	imply CMD_SF_TEST
 	imply CMD_ZBOOT
-	imply DM_ETH
 	imply DM_EVENT
 	imply DM_GPIO
 	imply DM_KEYBOARD
@@ -381,6 +380,10 @@ config SYS_IMMR
 	  Address for the Internal Memory-Mapped Registers (IMMR) window used
 	  to configure the features of many Freescale / NXP SoCs.
 
+config MONITOR_IS_IN_RAM
+	bool "U-Boot is loaded in to RAM by a pre-loader"
+	depends on M68K || NIOS2
+
 config SKIP_LOWLEVEL_INIT
 	bool "Skip the calls to certain low level initialization functions"
 	depends on ARM || MIPS || RISCV

+ 20 - 0
arch/Kconfig.nxp

@@ -1,5 +1,10 @@
+config FSL_TRUST_ARCH_v1
+	bool
+
 config NXP_ESBC
 	bool "NXP ESBC (secure boot) functionality"
+	select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \
+		ARCH_P5040 || ARCH_P2041
 	help
 	  Enable Freescale Secure Boot feature. Normally selected by defconfig.
 	  If unsure, do not change.
@@ -10,6 +15,7 @@ menu "Chain of trust / secure boot options"
 config CHAIN_OF_TRUST
 	select FSL_CAAM
 	select ARCH_MISC_INIT
+	select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT
 	select FSL_SEC_MON
 	select SPL_BOARD_INIT if (ARM && SPL)
 	select SPL_HASH if (ARM && SPL)
@@ -41,6 +47,17 @@ config ESBC_ADDR_64BIT
 	help
 	  For Layerscape based platforms, ESBC image Address in Header is 64bit.
 
+config FSL_ISBC_KEY_EXT
+	bool
+	help
+	  The key used for verification of next level images is picked up from
+	  an Extension Table which has been verified by the ISBC (Internal
+	  Secure boot Code) in boot ROM of the SoC.  The feature is only
+	  applicable in case of NOR boot and is not applicable in case of
+	  RAMBOOT (NAND, SD, SPI).  For Layerscape, this feature is available
+	  for all device if IE Table is copied to XIP memory Also, for
+	  Layerscape, ISBC doesn't verify this table.
+
 config SYS_FSL_SFP_BE
 	def_bool y
 	depends on PPC || FSL_LSCH2 || ARCH_LS1021A
@@ -251,3 +268,6 @@ config QIXIS_I2C_ACCESS
 config HAS_FSL_DR_USB
 	def_bool y
 	depends on USB_EHCI_HCD && PPC
+
+config SYS_DPAA_FMAN
+	bool

+ 0 - 3
arch/arc/config.mk

@@ -21,6 +21,3 @@ PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -fno-common
 
 # Needed for relocation
 LDFLAGS_FINAL += -pie --gc-sections
-
-# Load address for standalone apps
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000

+ 2 - 2
arch/arc/lib/cache.c

@@ -476,9 +476,9 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
 static void arc_ioc_setup(void)
 {
 	/* IOC Aperture start is equal to DDR start */
-	unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
+	unsigned int ap_base = CFG_SYS_SDRAM_BASE;
 	/* IOC Aperture size is equal to DDR size */
-	long ap_size = CONFIG_SYS_SDRAM_SIZE;
+	long ap_size = CFG_SYS_SDRAM_SIZE;
 
 	/* Unsupported configuration. See [ NOTE 2 ] for more details. */
 	if (!slc_exists())

+ 1 - 1
arch/arc/lib/cpu.c

@@ -20,7 +20,7 @@ int arch_cpu_init(void)
 	timer_init();
 
 	gd->cpu_clk = get_board_sys_clk();
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	gd->ram_size = CFG_SYS_SDRAM_SIZE;
 
 	cache_init();
 

+ 11 - 13
arch/arm/Kconfig

@@ -553,6 +553,9 @@ config ARM64_SUPPORT_AARCH32
 	help
 	  This ARM64 system supports AArch32 execution state.
 
+config IPROC
+	bool
+
 config S5P
 	def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
 
@@ -586,7 +589,6 @@ config ARCH_KIRKWOOD
 config ARCH_MVEBU
 	bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
 	select DM
-	select DM_ETH
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
@@ -659,6 +661,7 @@ config TARGET_BCMCYGNUS
 	bool "Support bcmcygnus"
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
+	select IPROC
 	imply BCM_SF2_ETH
 	imply BCM_SF2_ETH_GMAC
 	imply CMD_HASH
@@ -690,7 +693,6 @@ config ARCH_EXYNOS
 	select DM
 	select DM_GPIO
 	select DM_I2C
-	select DM_ETH
 	select DM_KEYBOARD
 	select DM_SERIAL
 	select DM_SPI
@@ -721,7 +723,6 @@ config ARCH_HIGHBANK
 	select CLK
 	select CLK_CCF
 	select AHCI
-	select DM_ETH
 	select PHYS_64BIT
 	select TIMER
 	select SP804_TIMER
@@ -918,6 +919,7 @@ config ARCH_MX7
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
 	select MACH_IMX
+	select MXC_GPT_HCLK
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
@@ -931,6 +933,7 @@ config ARCH_MX6
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
 	select MACH_IMX
+	select MXC_GPT_HCLK
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
@@ -995,7 +998,6 @@ config ARCH_APPLE
 config ARCH_OWL
 	bool "Actions Semi OWL SoCs"
 	select DM
-	select DM_ETH
 	select DM_SERIAL
 	select GPIO_EXTRA_HEADER
 	select OWL_SERIAL
@@ -1095,7 +1097,6 @@ config ARCH_SUNXI
 	select CMD_USB if DISTRO_DEFAULTS && USB_HOST
 	select CLK
 	select DM
-	select DM_ETH
 	select DM_GPIO
 	select DM_I2C if I2C
 	select DM_SPI if SPI
@@ -1174,7 +1175,6 @@ config ARCH_VERSAL
 	select ARM64
 	select CLK
 	select DM
-	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
 	select GICV3
@@ -1188,7 +1188,6 @@ config ARCH_VERSAL_NET
 	select ARM64
 	select CLK
 	select DM
-	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
 	select OF_CONTROL
@@ -1199,6 +1198,7 @@ config ARCH_VF610
 	bool "Freescale Vybrid"
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
+	select IOMUX_SHARE_CONF_REG
 	select MACH_IMX
 	select SYS_FSL_ERRATUM_ESDHC111
 	imply CMD_MTDPARTS
@@ -1212,7 +1212,6 @@ config ARCH_ZYNQ
 	select CPU_V7A
 	select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
 	select DM
-	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
 	select DM_SPI
@@ -1242,7 +1241,6 @@ config ARCH_ZYNQMP_R5
 	select CLK
 	select CPU_V7R
 	select DM
-	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
 	select OF_CONTROL
@@ -1255,7 +1253,6 @@ config ARCH_ZYNQMP
 	select CLK
 	select DM
 	select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
-	select DM_ETH if NET
 	imply DM_MAILBOX
 	select DM_MMC if MMC
 	select DM_SERIAL
@@ -1606,6 +1603,7 @@ config TARGET_LS1021AQDS
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select LS1_DEEP_SLEEP
+	select PEN_ADDR_BIG_ENDIAN
 	select SUPPORT_SPL
 	select SYS_FSL_DDR
 	select FSL_DDR_INTERACTIVE
@@ -1624,6 +1622,7 @@ config TARGET_LS1021ATWR
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select LS1_DEEP_SLEEP
+	select PEN_ADDR_BIG_ENDIAN
 	select SUPPORT_SPL
 	select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
 	select GPIO_EXTRA_HEADER
@@ -1688,6 +1687,7 @@ config TARGET_LS1021AIOT
 	select CPU_V7A
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
+	select PEN_ADDR_BIG_ENDIAN
 	select SUPPORT_SPL
 	select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
 	select GPIO_EXTRA_HEADER
@@ -1802,7 +1802,6 @@ config TARGET_SL28
 	select DM_I2C
 	select DM_MMC
 	select DM_SPI_FLASH
-	select DM_ETH
 	select DM_MDIO
 	select PCI
 	select DM_RNG
@@ -1839,7 +1838,6 @@ config ARCH_UNIPHIER
 	bool "Socionext UniPhier SoCs"
 	select BOARD_LATE_INIT
 	select DM
-	select DM_ETH
 	select DM_GPIO
 	select DM_I2C
 	select DM_MMC
@@ -2025,7 +2023,6 @@ config TARGET_POMELO
 	select SCSI
 	select DM_SCSI
 	select DM_SERIAL
-	select DM_ETH if NET
 	imply CMD_PCI
 	help
 	   Support for pomelo platform.
@@ -2295,6 +2292,7 @@ source "board/hisilicon/poplar/Kconfig"
 source "board/isee/igep003x/Kconfig"
 source "board/kontron/sl28/Kconfig"
 source "board/myir/mys_6ulx/Kconfig"
+source "board/samsung/common/Kconfig"
 source "board/siemens/common/Kconfig"
 source "board/seeed/npi_imx6ull/Kconfig"
 source "board/socionext/developerbox/Kconfig"

+ 0 - 8
arch/arm/config.mk

@@ -3,14 +3,6 @@
 # (C) Copyright 2000-2002
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
-ifndef CONFIG_STANDALONE_LOAD_ADDR
-ifneq ($(CONFIG_ARCH_OMAP2PLUS),)
-CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
-else
-CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
-endif
-endif
-
 CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \
 		  -fstack-protector-strong
 CFLAGS_EFI := -fpic -fshort-wchar

+ 1 - 1
arch/arm/cpu/arm1176/start.S

@@ -18,7 +18,7 @@
 #include <linux/linkage.h>
 
 #ifndef CONFIG_SYS_PHY_UBOOT_BASE
-#define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
+#define CONFIG_SYS_PHY_UBOOT_BASE	CFG_SYS_UBOOT_BASE
 #endif
 
 /*

+ 0 - 8
arch/arm/cpu/arm920t/imx/Makefile

@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	+= generic.o
-obj-y	+= speed.o
-obj-y	+= timer.o

+ 0 - 76
arch/arm/cpu/arm920t/imx/generic.c

@@ -1,76 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *  arch/arm/mach-imx/generic.c
- *
- *  author: Sascha Hauer
- *  Created: april 20th, 2004
- *  Copyright: Synertronixx GmbH
- *
- *  Common code for i.MX machines
- */
-
-#include <common.h>
-
-#ifdef CONFIG_IMX
-
-#include <asm/arch/imx-regs.h>
-
-void imx_gpio_mode(int gpio_mode)
-{
-	unsigned int pin = gpio_mode & GPIO_PIN_MASK;
-	unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5;
-	unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10;
-	unsigned int tmp;
-
-	/* Pullup enable */
-	if(gpio_mode & GPIO_PUEN)
-		PUEN(port) |= (1<<pin);
-	else
-		PUEN(port) &= ~(1<<pin);
-
-	/* Data direction */
-	if(gpio_mode & GPIO_OUT)
-		DDIR(port) |= 1<<pin;
-	else
-		DDIR(port) &= ~(1<<pin);
-
-	/* Primary / alternate function */
-	if(gpio_mode & GPIO_AF)
-		GPR(port) |= (1<<pin);
-	else
-		GPR(port) &= ~(1<<pin);
-
-	/* use as gpio? */
-	if( ocr == 3 )
-		GIUS(port) |= (1<<pin);
-	else
-		GIUS(port) &= ~(1<<pin);
-
-	/* Output / input configuration */
-	/* FIXME: I'm not very sure about OCR and ICONF, someone
-	 * should have a look over it
-	 */
-	if(pin<16) {
-		tmp = OCR1(port);
-		tmp &= ~( 3<<(pin*2));
-		tmp |= (ocr << (pin*2));
-		OCR1(port) = tmp;
-
-		if( gpio_mode &	GPIO_AOUT )
-			ICONFA1(port) &= ~( 3<<(pin*2));
-		if( gpio_mode &	GPIO_BOUT )
-			ICONFB1(port) &= ~( 3<<(pin*2));
-	} else {
-		tmp = OCR2(port);
-		tmp &= ~( 3<<((pin-16)*2));
-		tmp |= (ocr << ((pin-16)*2));
-		OCR2(port) = tmp;
-
-		if( gpio_mode &	GPIO_AOUT )
-			ICONFA2(port) &= ~( 3<<((pin-16)*2));
-		if( gpio_mode &	GPIO_BOUT )
-			ICONFB2(port) &= ~( 3<<((pin-16)*2));
-	}
-}
-
-#endif /* CONFIG_IMX */

+ 0 - 86
arch/arm/cpu/arm920t/imx/speed.c

@@ -1,86 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *
- * (c) 2004 Sascha Hauer <sascha@saschahauer.de>
- */
-
-
-#include <common.h>
-#if defined (CONFIG_IMX)
-#include <clock_legacy.h>
-
-#include <asm/arch/imx-regs.h>
-
-/* ------------------------------------------------------------------------- */
-/* NOTE: This describes the proper use of this file.
- *
- * get_board_sys_clk() should be defined as the input frequency of the PLL.
- * SH FIXME: 16780000 in our case
- * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
- * the specified bus in HZ.
- */
-/* ------------------------------------------------------------------------- */
-
-ulong get_systemPLLCLK(void)
-{
-	/* FIXME: We assume System_SEL = 0 here */
-	u32 spctl0 = SPCTL0;
-	u32 mfi = (spctl0 >> 10) & 0xf;
-	u32 mfn = spctl0 & 0x3f;
-	u32 mfd = (spctl0 >> 16) & 0x3f;
-	u32 pd =  (spctl0 >> 26) & 0xf;
-
-	mfi = mfi<=5 ? 5 : mfi;
-
-	return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
-}
-
-ulong get_mcuPLLCLK(void)
-{
-	/* FIXME: We assume System_SEL = 0 here */
-	u32 mpctl0 = MPCTL0;
-	u32 mfi = (mpctl0 >> 10) & 0xf;
-	u32 mfn = mpctl0 & 0x3f;
-	u32 mfd = (mpctl0 >> 16) & 0x3f;
-	u32 pd =  (mpctl0 >> 26) & 0xf;
-
-	mfi = mfi<=5 ? 5 : mfi;
-
-	return (2*(get_board_sys_clk()>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
-}
-
-ulong get_FCLK(void)
-{
-	return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK();
-}
-
-/* return HCLK frequency */
-ulong get_HCLK(void)
-{
-	u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
-	printf("bclkdiv: %d\n", bclkdiv);
-	return get_systemPLLCLK() / bclkdiv;
-}
-
-/* return BCLK frequency */
-ulong get_BCLK(void)
-{
-	return get_HCLK();
-}
-
-ulong get_PERCLK1(void)
-{
-	return get_systemPLLCLK() / (((PCDR) & 0xf)+1);
-}
-
-ulong get_PERCLK2(void)
-{
-	return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1);
-}
-
-ulong get_PERCLK3(void)
-{
-	return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1);
-}
-
-#endif /* defined (CONFIG_IMX) */

+ 0 - 100
arch/arm/cpu/arm920t/imx/timer.c

@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <time.h>
-#if defined (CONFIG_IMX)
-
-#include <asm/arch/imx-regs.h>
-#include <linux/delay.h>
-
-int timer_init (void)
-{
-	int i;
-	/* setup GP Timer 1 */
-	TCTL1 = TCTL_SWR;
-	for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
-	TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
-	TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
-
-	/* Reset the timer */
-	TCTL1 &= ~TCTL_TEN;
-	TCTL1 |= TCTL_TEN; /* Enable timer */
-
-	return (0);
-}
-
-/*
- * timer without interrupts
- */
-static ulong get_timer_masked (void)
-{
-	return TCN1;
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong endtime = get_timer_masked() + usec;
-	signed long diff;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
-
-/*
- * Reset the cpu by setting up the watchdog timer and let him time out
- */
-void reset_cpu(void)
-{
-	/* Disable watchdog and set Time-Out field to 0 */
-	WCR = 0x00000000;
-
-	/* Write Service Sequence */
-	WSR = 0x00005555;
-	WSR = 0x0000AAAA;
-
-	/* Enable watchdog */
-	WCR = 0x00000001;
-
-	while (1);
-	/*NOTREACHED*/
-}
-
-#endif /* defined (CONFIG_IMX) */

+ 0 - 1
arch/arm/cpu/arm926ejs/Makefile

@@ -12,7 +12,6 @@ extra-y	:=
 endif
 endif
 
-obj-$(CONFIG_MX27) += mx27/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
 obj-$(if $(filter spear,$(SOC)),y) += spear/
 obj-$(CONFIG_ARCH_SUNXI) += sunxi/

+ 0 - 7
arch/arm/cpu/arm926ejs/mx27/Makefile

@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-
-obj-y	+= generic.o timer.o reset.o relocate.o

+ 0 - 378
arch/arm/cpu/arm926ejs/mx27/generic.c

@@ -1,378 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *  Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
- *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
- */
-
-#include <common.h>
-#include <div64.h>
-#include <net.h>
-#include <netdev.h>
-#include <vsprintf.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/mach-imx/sys_proto.h>
-#ifdef CONFIG_MMC_MXC
-#include <asm/arch/mxcmmc.h>
-#endif
-
-/*
- *  get the system pll clock in Hz
- *
- *                  mfi + mfn / (mfd +1)
- *  f = 2 * f_ref * --------------------
- *                        pd + 1
- */
-static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
-{
-	unsigned int mfi = (pll >> 10) & 0xf;
-	unsigned int mfn = pll & 0x3ff;
-	unsigned int mfd = (pll >> 16) & 0x3ff;
-	unsigned int pd =  (pll >> 26) & 0xf;
-
-	mfi = mfi <= 5 ? 5 : mfi;
-
-	return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
-			(mfd + 1) * (pd + 1));
-}
-
-static ulong clk_in_32k(void)
-{
-	return 1024 * CONFIG_MX27_CLK32;
-}
-
-static ulong clk_in_26m(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
-		/* divide by 1.5 */
-		return 26000000 * 2 / 3;
-	} else {
-		return 26000000;
-	}
-}
-
-static ulong imx_get_mpllclk(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	ulong cscr = readl(&pll->cscr);
-	ulong fref;
-
-	if (cscr & CSCR_MCU_SEL)
-		fref = clk_in_26m();
-	else
-		fref = clk_in_32k();
-
-	return imx_decode_pll(readl(&pll->mpctl0), fref);
-}
-
-static ulong imx_get_armclk(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	ulong cscr = readl(&pll->cscr);
-	ulong fref = imx_get_mpllclk();
-	ulong div;
-
-	if (!(cscr & CSCR_ARM_SRC_MPLL))
-		fref = lldiv((fref * 2), 3);
-
-	div = ((cscr >> 12) & 0x3) + 1;
-
-	return lldiv(fref, div);
-}
-
-static ulong imx_get_ahbclk(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	ulong cscr = readl(&pll->cscr);
-	ulong fref = imx_get_mpllclk();
-	ulong div;
-
-	div = ((cscr >> 8) & 0x3) + 1;
-
-	return lldiv(fref * 2, 3 * div);
-}
-
-static __attribute__((unused)) ulong imx_get_spllclk(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-	ulong cscr = readl(&pll->cscr);
-	ulong fref;
-
-	if (cscr & CSCR_SP_SEL)
-		fref = clk_in_26m();
-	else
-		fref = clk_in_32k();
-
-	return imx_decode_pll(readl(&pll->spctl0), fref);
-}
-
-static ulong imx_decode_perclk(ulong div)
-{
-	return lldiv((imx_get_mpllclk() * 2), (div * 3));
-}
-
-static ulong imx_get_perclk1(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
-}
-
-static ulong imx_get_perclk2(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
-}
-
-static __attribute__((unused)) ulong imx_get_perclk3(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
-}
-
-static __attribute__((unused)) ulong imx_get_perclk4(void)
-{
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
-}
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
-	switch (clk) {
-	case MXC_ARM_CLK:
-		return imx_get_armclk();
-	case MXC_I2C_CLK:
-		return imx_get_ahbclk()/2;
-	case MXC_UART_CLK:
-		return imx_get_perclk1();
-	case MXC_FEC_CLK:
-		return imx_get_ahbclk();
-	case MXC_ESDHC_CLK:
-		return imx_get_perclk2();
-	}
-	return -1;
-}
-
-
-u32 get_cpu_rev(void)
-{
-	return MXC_CPU_MX27 << 12;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
-{
-	char buf[32];
-
-	printf("CPU:   Freescale i.MX27 at %s MHz\n\n",
-			strmhz(buf, imx_get_mpllclk()));
-	return 0;
-}
-#endif
-
-int cpu_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_FEC_MXC)
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	/* enable FEC clock */
-	writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
-	writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
-	return fecmxc_initialize(bis);
-#else
-	return 0;
-#endif
-}
-
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(struct bd_info *bis)
-{
-#ifdef CONFIG_MMC_MXC
-	return mxc_mmc_init(bis);
-#else
-	return 0;
-#endif
-}
-
-void imx_gpio_mode(int gpio_mode)
-{
-	struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
-	unsigned int pin = gpio_mode & GPIO_PIN_MASK;
-	unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
-	unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
-	unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
-	unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
-	unsigned int tmp;
-
-	/* Pullup enable */
-	if (gpio_mode & GPIO_PUEN) {
-		writel(readl(&regs->port[port].puen) | (1 << pin),
-				&regs->port[port].puen);
-	} else {
-		writel(readl(&regs->port[port].puen) & ~(1 << pin),
-				&regs->port[port].puen);
-	}
-
-	/* Data direction */
-	if (gpio_mode & GPIO_OUT) {
-		writel(readl(&regs->port[port].gpio_dir) | 1 << pin,
-				&regs->port[port].gpio_dir);
-	} else {
-		writel(readl(&regs->port[port].gpio_dir) & ~(1 << pin),
-				&regs->port[port].gpio_dir);
-	}
-
-	/* Primary / alternate function */
-	if (gpio_mode & GPIO_AF) {
-		writel(readl(&regs->port[port].gpr) | (1 << pin),
-				&regs->port[port].gpr);
-	} else {
-		writel(readl(&regs->port[port].gpr) & ~(1 << pin),
-				&regs->port[port].gpr);
-	}
-
-	/* use as gpio? */
-	if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
-		writel(readl(&regs->port[port].gius) | (1 << pin),
-				&regs->port[port].gius);
-	} else {
-		writel(readl(&regs->port[port].gius) & ~(1 << pin),
-				&regs->port[port].gius);
-	}
-
-	/* Output / input configuration */
-	if (pin < 16) {
-		tmp = readl(&regs->port[port].ocr1);
-		tmp &= ~(3 << (pin * 2));
-		tmp |= (ocr << (pin * 2));
-		writel(tmp, &regs->port[port].ocr1);
-
-		writel(readl(&regs->port[port].iconfa1) & ~(3 << (pin * 2)),
-				&regs->port[port].iconfa1);
-		writel(readl(&regs->port[port].iconfa1) | aout << (pin * 2),
-				&regs->port[port].iconfa1);
-		writel(readl(&regs->port[port].iconfb1) & ~(3 << (pin * 2)),
-				&regs->port[port].iconfb1);
-		writel(readl(&regs->port[port].iconfb1) | bout << (pin * 2),
-				&regs->port[port].iconfb1);
-	} else {
-		pin -= 16;
-
-		tmp = readl(&regs->port[port].ocr2);
-		tmp &= ~(3 << (pin * 2));
-		tmp |= (ocr << (pin * 2));
-		writel(tmp, &regs->port[port].ocr2);
-
-		writel(readl(&regs->port[port].iconfa2) & ~(3 << (pin * 2)),
-				&regs->port[port].iconfa2);
-		writel(readl(&regs->port[port].iconfa2) | aout << (pin * 2),
-				&regs->port[port].iconfa2);
-		writel(readl(&regs->port[port].iconfb2) & ~(3 << (pin * 2)),
-				&regs->port[port].iconfb2);
-		writel(readl(&regs->port[port].iconfb2) | bout << (pin * 2),
-				&regs->port[port].iconfb2);
-	}
-}
-
-#ifdef CONFIG_MXC_UART
-void mx27_uart1_init_pins(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PE12_PF_UART1_TXD,
-		PE13_PF_UART1_RXD,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx_gpio_mode(mode[i]);
-
-}
-#endif /* CONFIG_MXC_UART */
-
-#ifdef CONFIG_FEC_MXC
-void mx27_fec_init_pins(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PD0_AIN_FEC_TXD0,
-		PD1_AIN_FEC_TXD1,
-		PD2_AIN_FEC_TXD2,
-		PD3_AIN_FEC_TXD3,
-		PD4_AOUT_FEC_RX_ER,
-		PD5_AOUT_FEC_RXD1,
-		PD6_AOUT_FEC_RXD2,
-		PD7_AOUT_FEC_RXD3,
-		PD8_AF_FEC_MDIO,
-		PD9_AIN_FEC_MDC | GPIO_PUEN,
-		PD10_AOUT_FEC_CRS,
-		PD11_AOUT_FEC_TX_CLK,
-		PD12_AOUT_FEC_RXD0,
-		PD13_AOUT_FEC_RX_DV,
-		PD14_AOUT_FEC_CLR,
-		PD15_AOUT_FEC_COL,
-		PD16_AIN_FEC_TX_ER,
-		PF23_AIN_FEC_TX_EN,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx_gpio_mode(mode[i]);
-}
-
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
-	int i;
-	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-	struct fuse_bank *bank = &iim->bank[0];
-	struct fuse_bank0_regs *fuse =
-			(struct fuse_bank0_regs *)bank->fuse_regs;
-
-	for (i = 0; i < 6; i++)
-		mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff;
-}
-#endif /* CONFIG_FEC_MXC */
-
-#ifdef CONFIG_MMC_MXC
-void mx27_sd1_init_pins(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PE18_PF_SD1_D0,
-		PE19_PF_SD1_D1,
-		PE20_PF_SD1_D2,
-		PE21_PF_SD1_D3,
-		PE22_PF_SD1_CMD,
-		PE23_PF_SD1_CLK,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx_gpio_mode(mode[i]);
-
-}
-
-void mx27_sd2_init_pins(void)
-{
-	int i;
-	unsigned int mode[] = {
-		PB4_PF_SD2_D0,
-		PB5_PF_SD2_D1,
-		PB6_PF_SD2_D2,
-		PB7_PF_SD2_D3,
-		PB8_PF_SD2_CMD,
-		PB9_PF_SD2_CLK,
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mode); i++)
-		imx_gpio_mode(mode[i]);
-
-}
-#endif /* CONFIG_MMC_MXC */

+ 0 - 50
arch/arm/cpu/arm926ejs/mx27/relocate.S

@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  relocate - i.MX27-specific vector relocation
- *
- *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <linux/linkage.h>
-
-/*
- * The i.MX27 SoC is very specific with respect to exceptions: it
- * does not provide RAM at the high vectors address (0xFFFF0000),
- * thus only the low address (0x00000000) is useable; but that is
- * in ROM. Therefore, vectors cannot be changed at all.
- *
- * However, these ROM-based vectors actually just perform indirect
- * calls through pointers located in RAM at SoC-specific addresses,
- * as follows:
- *
- * Offset      Exception              Use by ROM code
- * 0x00000000  reset                  indirect branch to [0x00000014]
- * 0x00000004  undefined instruction  indirect branch to [0xfffffef0]
- * 0x00000008  software interrupt     indirect branch to [0xfffffef4]
- * 0x0000000c  prefetch abort         indirect branch to [0xfffffef8]
- * 0x00000010  data abort             indirect branch to [0xfffffefc]
- * 0x00000014  (reserved in ARMv5)    vector to ROM reset: 0xc0000000
- * 0x00000018  IRQ                    indirect branch to [0xffffff00]
- * 0x0000001c  FIQ                    indirect branch to [0xffffff04]
- *
- * In order to initialize exceptions on i.MX27, we must copy U-Boot's
- * indirect (not exception!) vector table into 0xfffffef0..0xffffff04
- * taking care not to copy vectors number 5 (reserved exception).
- */
-
-	.section	.text.relocate_vectors,"ax",%progbits
-
-ENTRY(relocate_vectors)
-
-	ldr	r0, [r9, #GD_RELOCADDR]	/* r0 = gd->relocaddr */
-	ldr	r1, =32			/* size of vector table */
-	add	r0, r0, r1		/* skip to indirect table */
-	ldr	r1, =0xFFFFFEF0		/* i.MX27 indirect table */
-	ldmia	r0!, {r2-r8}		/* load indirect vectors 1..7 */
-	stmia	r1!, {r2-r5, r7,r8}	/* write all but vector 5 */
-
-	bx	lr
-
-ENDPROC(relocate_vectors)

+ 0 - 41
arch/arm/cpu/arm926ejs/mx27/reset.c

@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-/*
- * Reset the cpu by setting up the watchdog timer and let it time out
- */
-void reset_cpu(void)
-{
-	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
-	/* Disable watchdog and set Time-Out field to 0 */
-	writew(0x0000, &regs->wcr);
-
-	/* Write Service Sequence */
-	writew(0x5555, &regs->wsr);
-	writew(0xAAAA, &regs->wsr);
-
-	/* Enable watchdog */
-	writew(WCR_WDE, &regs->wcr);
-
-	while (1);
-	/*NOTREACHED*/
-}

+ 0 - 166
arch/arm/cpu/arm926ejs/mx27/timer.c

@@ -1,166 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- */
-
-#include <common.h>
-#include <div64.h>
-#include <init.h>
-#include <time.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/ptrace.h>
-#include <linux/delay.h>
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR		(1 << 15)	/* Software reset	*/
-#define GPTCR_FRR		(1 << 8)	/* Freerun / restart	*/
-#define GPTCR_CLKSOURCE_32	(4 << 1)	/* Clock source		*/
-#define GPTCR_TEN		1		/* Timer enable		*/
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp	(gd->arch.tbl)
-#define lastinc		(gd->arch.lastinc)
-
-/*
- * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
- * "tick" is internal timer period
- */
-#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION
-/* ~0.4% error - measured with stop-watch on 100s boot-delay */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CONFIG_MX27_CLK32);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	time *= CONFIG_MX27_CLK32;
-	do_div(time, CONFIG_SYS_HZ);
-	return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * CONFIG_MX27_CLK32 + 999999;
-	do_div(us, 1000000);
-	return us;
-}
-#else
-/* ~2% error */
-#define TICK_PER_TIME	((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \
-		CONFIG_SYS_HZ)
-#define US_PER_TICK	(1000000 / CONFIG_MX27_CLK32)
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	do_div(tick, TICK_PER_TIME);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	return time * TICK_PER_TIME;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us += US_PER_TICK - 1;
-	do_div(us, US_PER_TICK);
-	return us;
-}
-#endif
-
-/* nothing really to do with interrupts, just starts up a counter. */
-/* The 32768Hz 32-bit timer overruns in 131072 seconds */
-int timer_init(void)
-{
-	int i;
-	struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-
-	/* setup GP Timer 1 */
-	writel(GPTCR_SWR, &regs->gpt_tctl);
-
-	writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0);
-	writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1);
-
-	for (i = 0; i < 100; i++)
-		writel(0, &regs->gpt_tctl); /* We have no udelay by now */
-	writel(0, &regs->gpt_tprer); /* 32Khz */
-	/* Freerun Mode, PERCLK1 input */
-	writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
-			&regs->gpt_tctl);
-	writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl);
-
-	return 0;
-}
-
-unsigned long long get_ticks(void)
-{
-	struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
-	ulong now = readl(&regs->gpt_tcn); /* current tick value */
-
-	if (now >= lastinc) {
-		/*
-		 * normal mode (non roll)
-		 * move stamp forward with absolut diff ticks
-		 */
-		timestamp += (now - lastinc);
-	} else {
-		/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
-	}
-	lastinc = now;
-	return timestamp;
-}
-
-static ulong get_timer_masked(void)
-{
-	/*
-	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-	 * 5 * 10^6 days - long enough.
-	 */
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timstamp value */
-void __udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
-
-ulong get_tbclk(void)
-{
-	return CONFIG_MX27_CLK32;
-}

+ 1 - 1
arch/arm/cpu/arm926ejs/start.S

@@ -95,7 +95,7 @@ flush_dcache:
 	mrc	p15, 0, r0, c1, c0, 0
 	bic	r0, r0, #0x00000300	/* clear bits 9:8 (---- --RS) */
 	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
-#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#ifdef CFG_SYS_EXCEPTION_VECTORS_HIGH
 	orr	r0, r0, #0x00002000	/* set bit 13 (--V- ----) */
 #else
 	bic	r0, r0, #0x00002000	/* clear bit 13 (--V- ----) */

+ 3 - 3
arch/arm/cpu/armv7/arch_timer.c

@@ -14,7 +14,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_SYS_HZ_CLOCK
+#ifndef CFG_SYS_HZ_CLOCK
 static inline u32 read_cntfrq(void)
 {
 	u32 frq;
@@ -29,8 +29,8 @@ int timer_init(void)
 	gd->arch.tbl = 0;
 	gd->arch.tbu = 0;
 
-#ifdef CONFIG_SYS_HZ_CLOCK
-	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+#ifdef CFG_SYS_HZ_CLOCK
+	gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
 #else
 	gd->arch.timer_rate_hz = read_cntfrq();
 #endif

+ 11 - 0
arch/arm/cpu/armv7/ls102xa/Kconfig

@@ -1,6 +1,8 @@
 config ARCH_LS1021A
 	bool
+	select FSL_DEVICE_DISABLE
 	select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
+	select LS102XA_STREAM_ID
 	select SYS_FSL_DDR_BE if SYS_FSL_DDR
 	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
 	select SYS_FSL_IFC_BE
@@ -30,9 +32,15 @@ config ARCH_LS1021A
 menu "LS102xA architecture"
 	depends on ARCH_LS1021A
 
+config FSL_DEVICE_DISABLE
+	bool
+
 config LS1_DEEP_SLEEP
 	bool "Deep sleep"
 
+config LS102XA_STREAM_ID
+	bool
+
 config MAX_CPUS
 	int "Maximum number of CPUs permitted for LS102xA"
 	default 2
@@ -43,6 +51,9 @@ config MAX_CPUS
 	  cores, count the reserved ports. This will allocate enough memory
 	  in spin table to properly handle all cores.
 
+config PEN_ADDR_BIG_ENDIAN
+	bool
+
 config SYS_CCI400_OFFSET
 	hex "Offset for CCI400 base"
 	depends on SYS_FSL_HAS_CCI400

+ 10 - 19
arch/arm/cpu/armv7/ls102xa/cpu.c

@@ -168,18 +168,18 @@ static void mmu_setup(void)
 	/* Level 1 has 512 entries */
 	for (i = 0; i < 512; i++) {
 		/* Mapping for PCIe 1 */
-		if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
-		    va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
-				 CONFIG_SYS_PCIE_MMAP_SIZE))
+		if (va_start >= CFG_SYS_PCIE1_VIRT_ADDR &&
+		    va_start < (CFG_SYS_PCIE1_VIRT_ADDR +
+				 CFG_SYS_PCIE_MMAP_SIZE))
 			set_pgsection(level1_table, i,
-				      CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
+				      CFG_SYS_PCIE1_PHYS_BASE + va_start,
 				      MT_DEVICE_MEM);
 		/* Mapping for PCIe 2 */
-		else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
-			 va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
-				     CONFIG_SYS_PCIE_MMAP_SIZE))
+		else if (va_start >= CFG_SYS_PCIE2_VIRT_ADDR &&
+			 va_start < (CFG_SYS_PCIE2_VIRT_ADDR +
+				     CFG_SYS_PCIE_MMAP_SIZE))
 			set_pgsection(level1_table, i,
-				      CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
+				      CFG_SYS_PCIE2_PHYS_BASE + va_start,
 				      MT_DEVICE_MEM);
 		else
 			set_pgsection(level1_table, i,
@@ -302,20 +302,11 @@ int cpu_mmc_init(struct bd_info *bis)
 }
 #endif
 
-int cpu_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
-	tsec_standard_init(bis);
-#endif
-
-	return 0;
-}
-
 int arch_cpu_init(void)
 {
-	void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *rcpm2_base =
-		(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+		(void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
 	struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
 	u32 state;
 

+ 2 - 2
arch/arm/cpu/armv7/ls102xa/fdt.c

@@ -125,7 +125,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 
 #ifdef CONFIG_SYS_NS16550
 	do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
-			       "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+			       "clock-frequency", CFG_SYS_NS16550_CLK, 1);
 #endif
 
 	sysclk_path = fdt_get_alias(blob, "sysclk");
@@ -183,7 +183,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 	off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
-					    CONFIG_SYS_IFC_ADDR);
+					    CFG_SYS_IFC_ADDR);
 	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
 #else
 	off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,

+ 3 - 3
arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c

@@ -29,7 +29,7 @@
  */
 static void __secure ls1_save_ddr_head(void)
 {
-	const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
+	const char *src = (const char *)CFG_SYS_SDRAM_BASE;
 	char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
 	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
 	int i;
@@ -42,7 +42,7 @@ static void __secure ls1_save_ddr_head(void)
 
 static void __secure ls1_fsm_setup(void)
 {
-	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
 
 	out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
@@ -118,7 +118,7 @@ static void __secure ls1_delay(unsigned int loop)
 
 static void __secure ls1_start_fsm(void)
 {
-	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
 	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
 	struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;

+ 5 - 6
arch/arm/cpu/armv7/nonsec_virt.S

@@ -112,8 +112,8 @@ ENTRY(_do_nonsec_entry)
 ENDPROC(_do_nonsec_entry)
 
 .macro get_cbar_addr	addr
-#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
-	ldr	\addr, =CONFIG_ARM_GIC_BASE_ADDRESS
+#ifdef CFG_ARM_GIC_BASE_ADDRESS
+	ldr	\addr, =CFG_ARM_GIC_BASE_ADDRESS
 #else
 	mrc	p15, 4, \addr, c15, c0, 0	@ read CBAR
 	bfc	\addr, #0, #15			@ clear reserved bits
@@ -205,11 +205,11 @@ ENTRY(_nonsec_init)
 	bx	lr
 ENDPROC(_nonsec_init)
 
-#ifdef CONFIG_SMP_PEN_ADDR
+#ifdef CFG_SMP_PEN_ADDR
 /* void __weak smp_waitloop(unsigned previous_address); */
-ENTRY(smp_waitloop)
+WEAK(smp_waitloop)
 	wfi
-	ldr	r1, =CONFIG_SMP_PEN_ADDR	@ load start address
+	ldr	r1, =CFG_SMP_PEN_ADDR	@ load start address
 	ldr	r1, [r1]
 #ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
 	rev	r1, r1
@@ -219,7 +219,6 @@ ENTRY(smp_waitloop)
 	mov	r0, r1
 	b	_do_nonsec_entry
 ENDPROC(smp_waitloop)
-.weak smp_waitloop
 #endif
 
 	.popsection

+ 26 - 51
arch/arm/cpu/armv7/psci.S

@@ -36,34 +36,32 @@ _psci_vectors:
 	b	default_psci_vector	@ irq
 	b	psci_fiq_enter		@ fiq
 
-ENTRY(psci_fiq_enter)
+WEAK(psci_fiq_enter)
 	movs	pc, lr
 ENDPROC(psci_fiq_enter)
-.weak psci_fiq_enter
 
-ENTRY(default_psci_vector)
+WEAK(default_psci_vector)
 	movs	pc, lr
 ENDPROC(default_psci_vector)
-.weak default_psci_vector
-
-ENTRY(psci_version)
-ENTRY(psci_cpu_suspend)
-ENTRY(psci_cpu_off)
-ENTRY(psci_cpu_on)
-ENTRY(psci_affinity_info)
-ENTRY(psci_migrate)
-ENTRY(psci_migrate_info_type)
-ENTRY(psci_migrate_info_up_cpu)
-ENTRY(psci_system_off)
-ENTRY(psci_system_reset)
-ENTRY(psci_features)
-ENTRY(psci_cpu_freeze)
-ENTRY(psci_cpu_default_suspend)
-ENTRY(psci_node_hw_state)
-ENTRY(psci_system_suspend)
-ENTRY(psci_set_suspend_mode)
-ENTRY(psi_stat_residency)
-ENTRY(psci_stat_count)
+
+WEAK(psci_version)
+WEAK(psci_cpu_suspend)
+WEAK(psci_cpu_off)
+WEAK(psci_cpu_on)
+WEAK(psci_affinity_info)
+WEAK(psci_migrate)
+WEAK(psci_migrate_info_type)
+WEAK(psci_migrate_info_up_cpu)
+WEAK(psci_system_off)
+WEAK(psci_system_reset)
+WEAK(psci_features)
+WEAK(psci_cpu_freeze)
+WEAK(psci_cpu_default_suspend)
+WEAK(psci_node_hw_state)
+WEAK(psci_system_suspend)
+WEAK(psci_set_suspend_mode)
+WEAK(psi_stat_residency)
+WEAK(psci_stat_count)
 	mov	r0, #ARM_PSCI_RET_NI	@ Return -1 (Not Implemented)
 	mov	pc, lr
 ENDPROC(psci_stat_count)
@@ -84,24 +82,6 @@ ENDPROC(psci_cpu_on)
 ENDPROC(psci_cpu_off)
 ENDPROC(psci_cpu_suspend)
 ENDPROC(psci_version)
-.weak psci_version
-.weak psci_cpu_suspend
-.weak psci_cpu_off
-.weak psci_cpu_on
-.weak psci_affinity_info
-.weak psci_migrate
-.weak psci_migrate_info_type
-.weak psci_migrate_info_up_cpu
-.weak psci_system_off
-.weak psci_system_reset
-.weak psci_features
-.weak psci_cpu_freeze
-.weak psci_cpu_default_suspend
-.weak psci_node_hw_state
-.weak psci_system_suspend
-.weak psci_set_suspend_mode
-.weak psi_stat_residency
-.weak psci_stat_count
 
 _psci_table:
 	.word	ARM_PSCI_FN_CPU_SUSPEND
@@ -179,12 +159,11 @@ _smc_psci:
 	movs	pc, lr			@ Return to the kernel
 
 @ Requires dense and single-cluster CPU ID space
-ENTRY(psci_get_cpu_id)
+WEAK(psci_get_cpu_id)
 	mrc	p15, 0, r0, c0, c0, 5	/* read MPIDR */
 	and	r0, r0, #0xff		/* return CPU ID in cluster */
 	bx	lr
 ENDPROC(psci_get_cpu_id)
-.weak psci_get_cpu_id
 
 /* Imported from Linux kernel */
 ENTRY(psci_v7_flush_dcache_all)
@@ -236,7 +215,7 @@ finished:
 	bx	lr
 ENDPROC(psci_v7_flush_dcache_all)
 
-ENTRY(psci_disable_smp)
+WEAK(psci_disable_smp)
 	mrc	p15, 0, r0, c1, c0, 1		@ ACTLR
 	bic	r0, r0, #(1 << 6)		@ Clear SMP bit
 	mcr	p15, 0, r0, c1, c0, 1		@ ACTLR
@@ -244,16 +223,14 @@ ENTRY(psci_disable_smp)
 	dsb
 	bx	lr
 ENDPROC(psci_disable_smp)
-.weak psci_disable_smp
 
-ENTRY(psci_enable_smp)
+WEAK(psci_enable_smp)
 	mrc	p15, 0, r0, c1, c0, 1		@ ACTLR
 	orr	r0, r0, #(1 << 6)		@ Set SMP bit
 	mcr	p15, 0, r0, c1, c0, 1		@ ACTLR
 	isb
 	bx	lr
 ENDPROC(psci_enable_smp)
-.weak psci_enable_smp
 
 ENTRY(psci_cpu_off_common)
 	push	{lr}
@@ -316,15 +293,13 @@ ENTRY(psci_stack_setup)
 	bx	r6
 ENDPROC(psci_stack_setup)
 
-ENTRY(psci_arch_init)
+WEAK(psci_arch_init)
 	mov	pc, lr
 ENDPROC(psci_arch_init)
-.weak psci_arch_init
 
-ENTRY(psci_arch_cpu_entry)
+WEAK(psci_arch_cpu_entry)
 	mov	pc, lr
 ENDPROC(psci_arch_cpu_entry)
-.weak psci_arch_cpu_entry
 
 ENTRY(psci_cpu_entry)
 	bl	psci_enable_smp

+ 5 - 6
arch/arm/cpu/armv7/s5p-common/pwm.c

@@ -7,12 +7,11 @@
 
 #include <common.h>
 #include <errno.h>
-#include <pwm.h>
 #include <asm/io.h>
 #include <asm/arch/pwm.h>
 #include <asm/arch/clk.h>
 
-int pwm_enable(int pwm_id)
+int s5p_pwm_enable(int pwm_id)
 {
 	const struct s5p_timer *pwm =
 #if defined(CONFIG_ARCH_NEXELL)
@@ -30,7 +29,7 @@ int pwm_enable(int pwm_id)
 	return 0;
 }
 
-void pwm_disable(int pwm_id)
+void s5p_pwm_disable(int pwm_id)
 {
 	const struct s5p_timer *pwm =
 #if defined(CONFIG_ARCH_NEXELL)
@@ -92,7 +91,7 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
 
 #define NS_IN_SEC 1000000000UL
 
-int pwm_config(int pwm_id, int duty_ns, int period_ns)
+int s5p_pwm_config(int pwm_id, int duty_ns, int period_ns)
 {
 	const struct s5p_timer *pwm =
 #if defined(CONFIG_ARCH_NEXELL)
@@ -157,7 +156,7 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns)
 	return 0;
 }
 
-int pwm_init(int pwm_id, int div, int invert)
+int s5p_pwm_init(int pwm_id, int div, int invert)
 {
 	u32 val;
 	const struct s5p_timer *pwm =
@@ -219,7 +218,7 @@ int pwm_init(int pwm_id, int div, int invert)
 		val |= TCON_INVERTER(pwm_id);
 	writel(val, &pwm->tcon);
 
-	pwm_enable(pwm_id);
+	s5p_pwm_enable(pwm_id);
 
 	return 0;
 }

+ 3 - 7
arch/arm/cpu/armv7/s5p-common/timer.c

@@ -16,10 +16,6 @@
 #include <asm/arch/clk.h>
 #include <linux/delay.h>
 
-/* Use the old PWM interface for now */
-#undef CONFIG_DM_PWM
-#include <pwm.h>
-
 DECLARE_GLOBAL_DATA_PTR;
 
 unsigned long get_current_tick(void);
@@ -49,9 +45,9 @@ static unsigned long timer_get_us_down(void)
 int timer_init(void)
 {
 	/* PWM Timer 4 */
-	pwm_init(4, MUX_DIV_4, 0);
-	pwm_config(4, 100000, 100000);
-	pwm_enable(4);
+	s5p_pwm_init(4, MUX_DIV_4, 0);
+	s5p_pwm_config(4, 100000, 100000);
+	s5p_pwm_enable(4);
 
 	/* Use this as the current monotonic time in us */
 	gd->arch.timer_reset_value = 0;

+ 0 - 29
arch/arm/cpu/armv7/s5p4418/cpu.c

@@ -13,10 +13,8 @@
 #include <asm/io.h>
 #include <asm/arch/nexell.h>
 #include <asm/arch/clk.h>
-#include <asm/arch/reset.h>
 #include <asm/arch/tieoff.h>
 #include <cpu_func.h>
-#include <linux/delay.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -45,39 +43,12 @@ static void cpu_soc_init(void)
 	nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1);
 }
 
-#ifdef CONFIG_PL011_SERIAL
-static void serial_device_init(void)
-{
-	char dev[10];
-	int id;
-
-	sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX);
-	id = RESET_ID_UART0 + CONFIG_CONS_INDEX;
-
-	struct clk *clk = clk_get((const char *)dev);
-
-	/* reset control: Low active ___|---   */
-	nx_rstcon_setrst(id, RSTCON_ASSERT);
-	udelay(10);
-	nx_rstcon_setrst(id, RSTCON_NEGATE);
-	udelay(10);
-
-	/* set clock   */
-	clk_disable(clk);
-	clk_set_rate(clk, CONFIG_PL011_CLOCK);
-	clk_enable(clk);
-}
-#endif
-
 int arch_cpu_init(void)
 {
 	flush_dcache_all();
 	cpu_soc_init();
 	clk_init();
 
-	if (IS_ENABLED(CONFIG_PL011_SERIAL))
-		serial_device_init();
-
 	return 0;
 }
 

+ 2 - 4
arch/arm/cpu/armv7/start.S

@@ -151,16 +151,14 @@ ENDPROC(c_runtime_cpu_setup)
  * Don't save anything to stack even if compiled with -O0
  *
  *************************************************************************/
-ENTRY(save_boot_params)
+WEAK(save_boot_params)
 	b	save_boot_params_ret		@ back to my caller
 ENDPROC(save_boot_params)
-	.weak	save_boot_params
 
 #ifdef CONFIG_ARMV7_LPAE
-ENTRY(switch_to_hypervisor)
+WEAK(switch_to_hypervisor)
 	b	switch_to_hypervisor_ret
 ENDPROC(switch_to_hypervisor)
-	.weak	switch_to_hypervisor
 #endif
 
 /*************************************************************************

+ 2 - 2
arch/arm/cpu/armv7/stv0991/timer.c

@@ -18,7 +18,7 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
 				(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
 
 #define READ_TIMER()	(readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
-#define GPT_RESOLUTION	(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
+#define GPT_RESOLUTION	(CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -67,7 +67,7 @@ void __udelay(unsigned long usec)
 {
 	ulong tmo;
 	ulong start = get_timer_masked();
-	ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
+	ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100);
 	ulong rndoff;
 
 	rndoff = (usec % 10) ? 1 : 0;

+ 2 - 2
arch/arm/cpu/armv7/virt-v7.c

@@ -26,8 +26,8 @@ static unsigned int read_id_pfr1(void)
 
 static unsigned long get_gicd_base_address(void)
 {
-#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
-	return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
+#ifdef CFG_ARM_GIC_BASE_ADDRESS
+	return CFG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
 #else
 	unsigned periphbase;
 

+ 4 - 4
arch/arm/cpu/armv7m/systick-timer.c

@@ -18,7 +18,7 @@
  * The number of reference clock ticks that correspond to 10ms is normally
  * defined in the SysTick Calibration register's TENMS field. However, on some
  * devices this is wrong, so this driver allows the clock rate to be defined
- * using CONFIG_SYS_HZ_CLOCK.
+ * using CFG_SYS_HZ_CLOCK.
  */
 
 #include <common.h>
@@ -76,10 +76,10 @@ int timer_init(void)
 
 	/*
 	 * If the TENMS field is inexact or wrong, specify the clock rate using
-	 * CONFIG_SYS_HZ_CLOCK.
+	 * CFG_SYS_HZ_CLOCK.
 	 */
-#if defined(CONFIG_SYS_HZ_CLOCK)
-	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+#if defined(CFG_SYS_HZ_CLOCK)
+	gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
 #else
 	gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100;
 #endif

+ 3 - 0
arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -29,6 +29,7 @@ config ARCH_LS1028A
 	select ESBC_HDR_LS if CHAIN_OF_TRUST
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
+	select FSL_TZASC_400
 	select GICV3
 	select NXP_LSCH3_2
 	select SYS_FSL_HAS_CCI400
@@ -69,6 +70,7 @@ config ARCH_LS1043A
 	select GICV2
 	select HAS_FSL_XHCI_USB if USB_HOST
 	select SKIP_LOWLEVEL_INIT
+	select SYS_DPAA_FMAN
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
@@ -106,6 +108,7 @@ config ARCH_LS1046A
 	select GICV2
 	select HAS_FSL_XHCI_USB if USB_HOST
 	select SKIP_LOWLEVEL_INIT
+	select SYS_DPAA_FMAN
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR

+ 56 - 59
arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -114,7 +114,7 @@ static struct mm_region early_map[] = {
 	  CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
-	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+	{ CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
 	  CONFIG_SYS_FSL_IFC_SIZE1,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
@@ -130,9 +130,9 @@ static struct mm_region early_map[] = {
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
 #ifdef CONFIG_FSL_IFC
-	/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
+	/* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */
 	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
-	  CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+	  CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
 #endif
@@ -257,26 +257,26 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-	  CONFIG_SYS_PCIE1_PHYS_SIZE,
+	{ CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
+	  CFG_SYS_PCIE1_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-	  CONFIG_SYS_PCIE2_PHYS_SIZE,
+	{ CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
+	  CFG_SYS_PCIE2_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
-	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-	  CONFIG_SYS_PCIE3_PHYS_SIZE,
+#ifdef CFG_SYS_PCIE3_PHYS_ADDR
+	{ CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
+	  CFG_SYS_PCIE3_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 #endif
-#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
-	{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
-	  CONFIG_SYS_PCIE4_PHYS_SIZE,
+#ifdef CFG_SYS_PCIE4_PHYS_ADDR
+	{ CFG_SYS_PCIE4_PHYS_ADDR, CFG_SYS_PCIE4_PHYS_ADDR,
+	  CFG_SYS_PCIE4_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
@@ -368,19 +368,19 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
-	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-	  CONFIG_SYS_PCIE1_PHYS_SIZE,
+	{ CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
+	  CFG_SYS_PCIE1_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-	  CONFIG_SYS_PCIE2_PHYS_SIZE,
+	{ CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
+	  CFG_SYS_PCIE2_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
-	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-	  CONFIG_SYS_PCIE3_PHYS_SIZE,
+#ifdef CFG_SYS_PCIE3_PHYS_ADDR
+	{ CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
+	  CFG_SYS_PCIE3_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
@@ -391,7 +391,7 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
 #endif
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	{},	/* space holder for secure mem */
 #endif
 	{},
@@ -445,7 +445,7 @@ static inline void early_mmu_setup(void)
 	if (el == 3)
 		gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
 	else
-		gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
+		gd->arch.tlb_addr = CFG_SYS_DDR_SDRAM_BASE;
 	gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 	gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 
@@ -477,25 +477,25 @@ static void fix_pcie_mmu_map(void)
 	    (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 		for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 			switch (final_map[i].phys) {
-			case CONFIG_SYS_PCIE1_PHYS_ADDR:
+			case CFG_SYS_PCIE1_PHYS_ADDR:
 				final_map[i].phys = 0x2000000000ULL;
 				final_map[i].virt = 0x2000000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
-			case CONFIG_SYS_PCIE2_PHYS_ADDR:
+			case CFG_SYS_PCIE2_PHYS_ADDR:
 				final_map[i].phys = 0x2800000000ULL;
 				final_map[i].virt = 0x2800000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
-#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
-			case CONFIG_SYS_PCIE3_PHYS_ADDR:
+#ifdef CFG_SYS_PCIE3_PHYS_ADDR
+			case CFG_SYS_PCIE3_PHYS_ADDR:
 				final_map[i].phys = 0x3000000000ULL;
 				final_map[i].virt = 0x3000000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
 #endif
-#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
-			case CONFIG_SYS_PCIE4_PHYS_ADDR:
+#ifdef CFG_SYS_PCIE4_PHYS_ADDR
+			case CFG_SYS_PCIE4_PHYS_ADDR:
 				final_map[i].phys = 0x3800000000ULL;
 				final_map[i].virt = 0x3800000000ULL;
 				final_map[i].size = 0x800000000ULL;
@@ -568,7 +568,7 @@ static inline void final_mmu_setup(void)
 		}
 	}
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 		if (el == 3) {
 			/*
@@ -580,7 +580,7 @@ static inline void final_mmu_setup(void)
 			gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 			final_map[index].virt = gd->arch.secure_ram & ~0x3;
 			final_map[index].phys = final_map[index].virt;
-			final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
+			final_map[index].size = CFG_SYS_MEM_RESERVE_SECURE;
 			final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 			gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 			tlb_addr_save = gd->arch.tlb_addr;
@@ -1057,9 +1057,6 @@ int cpu_eth_init(struct bd_info *bis)
 
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 	error = fsl_mc_ldpaa_init(bis);
-#endif
-#ifdef CONFIG_FMAN_ENET
-	fm_standard_init(bis);
 #endif
 	return error;
 }
@@ -1311,22 +1308,22 @@ phys_size_t get_effective_memsize(void)
 	 * allocated from first region. If the memory extends to  the second
 	 * region (or the third region if applicable), Management Complex (MC)
 	 * memory should be put into the highest region, i.e. the end of DDR
-	 * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
+	 * memory. CFG_MAX_MEM_MAPPED is set to the size of first region so
 	 * U-Boot doesn't relocate itself into higher address. Should DDR be
 	 * configured to skip the first region, this function needs to be
 	 * adjusted.
 	 */
-	if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
-		ea_size = CONFIG_MAX_MEM_MAPPED;
+	if (gd->ram_size > CFG_MAX_MEM_MAPPED) {
+		ea_size = CFG_MAX_MEM_MAPPED;
 		rem = gd->ram_size - ea_size;
 	} else {
 		ea_size = gd->ram_size;
 	}
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	/* Check if we have enough space for secure memory */
-	if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
-		ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+	if (ea_size > CFG_SYS_MEM_RESERVE_SECURE)
+		ea_size -= CFG_SYS_MEM_RESERVE_SECURE;
 	else
 		printf("Error: No enough space for secure memory.\n");
 #endif
@@ -1433,7 +1430,7 @@ int dram_init_banksize(void)
 	 * gd->arch.secure_ram should be done to avoid running it repeatedly.
 	 */
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 		debug("No need to run again, skip %s\n", __func__);
 
@@ -1441,12 +1438,12 @@ int dram_init_banksize(void)
 	}
 #endif
 
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
-		gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
-		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+	if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) {
+		gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
+		gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
 		gd->bd->bi_dram[1].size = gd->ram_size -
-					  CONFIG_SYS_DDR_BLOCK1_SIZE;
+					  CFG_SYS_DDR_BLOCK1_SIZE;
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 		if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
 			gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
@@ -1458,17 +1455,17 @@ int dram_init_banksize(void)
 	} else {
 		gd->bd->bi_dram[0].size = gd->ram_size;
 	}
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	if (gd->bd->bi_dram[0].size >
-				CONFIG_SYS_MEM_RESERVE_SECURE) {
+				CFG_SYS_MEM_RESERVE_SECURE) {
 		gd->bd->bi_dram[0].size -=
-				CONFIG_SYS_MEM_RESERVE_SECURE;
+				CFG_SYS_MEM_RESERVE_SECURE;
 		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
 				      gd->bd->bi_dram[0].size;
 		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-		gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+		gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE;
 	}
-#endif	/* CONFIG_SYS_MEM_RESERVE_SECURE */
+#endif	/* CFG_SYS_MEM_RESERVE_SECURE */
 
 #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
 	/* Assign memory for MC */
@@ -1520,7 +1517,7 @@ int dram_init_banksize(void)
 	}
 #endif
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	debug("%s is called. gd->ram_size is reduced to %lu\n",
 	      __func__, (ulong)gd->ram_size);
 #endif
@@ -1571,7 +1568,7 @@ void update_early_mmu_table(void)
 
 	if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
 		mmu_change_region_attr(
-					CONFIG_SYS_SDRAM_BASE,
+					CFG_SYS_SDRAM_BASE,
 					gd->ram_size,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
@@ -1579,8 +1576,8 @@ void update_early_mmu_table(void)
 					PTE_TYPE_VALID);
 	} else {
 		mmu_change_region_attr(
-					CONFIG_SYS_SDRAM_BASE,
-					CONFIG_SYS_DDR_BLOCK1_SIZE,
+					CFG_SYS_SDRAM_BASE,
+					CFG_SYS_DDR_BLOCK1_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
 					PTE_BLOCK_NS			|
@@ -1589,10 +1586,10 @@ void update_early_mmu_table(void)
 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
 #endif
-		if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
+		if (gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE >
 		    CONFIG_SYS_DDR_BLOCK2_SIZE) {
 			mmu_change_region_attr(
-					CONFIG_SYS_DDR_BLOCK2_BASE,
+					CFG_SYS_DDR_BLOCK2_BASE,
 					CONFIG_SYS_DDR_BLOCK2_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
@@ -1601,7 +1598,7 @@ void update_early_mmu_table(void)
 			mmu_change_region_attr(
 					CONFIG_SYS_DDR_BLOCK3_BASE,
 					gd->ram_size -
-					CONFIG_SYS_DDR_BLOCK1_SIZE -
+					CFG_SYS_DDR_BLOCK1_SIZE -
 					CONFIG_SYS_DDR_BLOCK2_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
@@ -1611,9 +1608,9 @@ void update_early_mmu_table(void)
 #endif
 		{
 			mmu_change_region_attr(
-					CONFIG_SYS_DDR_BLOCK2_BASE,
+					CFG_SYS_DDR_BLOCK2_BASE,
 					gd->ram_size -
-					CONFIG_SYS_DDR_BLOCK1_SIZE,
+					CFG_SYS_DDR_BLOCK1_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
 					PTE_BLOCK_NS			|

+ 2 - 2
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3

@@ -116,10 +116,10 @@ Flash Layout
 Environment Variables
 =====================
 mcboottimeout:	MC boot timeout in milliseconds. If this variable is not defined
-		the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+		the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
 
 mcmemsize:	MC DRAM block size in hex. If this variable is not defined, the value
-		CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+		CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
 
 mcinitcmd:	This environment variable is defined to initiate MC and DPL deployment
 		from the location where it is stored(NOR, NAND, SD, SATA, USB)during

+ 1 - 1
arch/arm/cpu/armv8/fsl-layerscape/fdt.c

@@ -646,7 +646,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 
 #ifdef CONFIG_SYS_NS16550
 	do_fixup_by_compat_u32(blob, "fsl,ns16550",
-			       "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+			       "clock-frequency", CFG_SYS_NS16550_CLK, 1);
 #endif
 
 	do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",

+ 2 - 6
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c

@@ -24,11 +24,7 @@ void get_sys_info(struct sys_info *sys_info)
 /* rcw_tmp is needed to get FMAN clock, or to get cluster group A
  * mux 2 clock for LS1043A/LS1046A.
  */
-#if defined(CONFIG_SYS_DPAA_FMAN) || \
-	    defined(CONFIG_ARCH_LS1046A) || \
-	    defined(CONFIG_ARCH_LS1043A)
-	u32 rcw_tmp;
-#endif
+	__maybe_unused u32 rcw_tmp;
 	struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR);
 	unsigned int cpu;
 	const u8 core_cplx_pll[8] = {
@@ -96,7 +92,7 @@ void get_sys_info(struct sys_info *sys_info)
 
 #define HWA_CGA_M1_CLK_SEL	0xe0000000
 #define HWA_CGA_M1_CLK_SHIFT	29
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
 	rcw_tmp = in_be32(&gur->rcwsr[7]);
 	switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
 	case 2:

+ 1 - 1
arch/arm/cpu/armv8/fsl-layerscape/icid.c

@@ -41,7 +41,7 @@ void set_icids(void)
 	/* setup general icid offsets */
 	set_icid(icid_tbl, icid_tbl_sz);
 
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
 	set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz);
 #endif
 }

+ 2 - 2
arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c

@@ -10,7 +10,7 @@
 #include <fsl_sec.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
@@ -59,7 +59,7 @@ struct icid_id_table icid_tbl[] = {
 
 int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
 
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
 struct fman_icid_id_table fman_icid_tbl[] = {
 	/* port id, icid */
 	SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),

+ 2 - 2
arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c

@@ -9,7 +9,7 @@
 #include <asm/arch-fsl-layerscape/fsl_portals.h>
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
 	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
@@ -58,7 +58,7 @@ struct icid_id_table icid_tbl[] = {
 
 int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
 
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
 struct fman_icid_id_table fman_icid_tbl[] = {
 	/* port id, icid */
 	SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),

+ 3 - 3
arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -531,7 +531,7 @@ static void erratum_a010539(void)
 
 	porsr1 = in_be32(&gur->porsr1);
 	porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
-	out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+	out_be32((void *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
 		 porsr1);
 	out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
 #endif
@@ -643,8 +643,8 @@ void init_pfe_scfg_dcfg_regs(void)
 	out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
 		 | SCFG_RD_QOS1_PFE2_QOS));
 
-	ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
-	out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
+	ecccr2 = in_be32(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
+	out_be32((void *)CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
 		 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
 }
 #endif

+ 1 - 1
arch/arm/cpu/armv8/fsl-layerscape/spl.c

@@ -116,7 +116,7 @@ void board_init_f(ulong dummy)
 #endif
 	dram_init();
 #ifdef CONFIG_SPL_FSL_LS_PPA
-#ifndef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifndef CFG_SYS_MEM_RESERVE_SECURE
 #error Need secure RAM for PPA
 #endif
 	/*

+ 4 - 8
arch/arm/cpu/armv8/psci.S

@@ -12,11 +12,10 @@
 
 /* Default PSCI function, return -1, Not Implemented */
 #define PSCI_DEFAULT(__fn) \
-	ENTRY(__fn); \
+	WEAK(__fn); \
 	mov	w0, #ARM_PSCI_RET_NI; \
 	ret; \
 	ENDPROC(__fn); \
-	.weak __fn
 
 /* PSCI function and ID table definition*/
 #define PSCI_TABLE(__id, __fn) \
@@ -207,7 +206,7 @@ handle_smc64:
  * used for the return value, while in this PSCI environment, X0 usually holds
  * the SMC function identifier, so X0 should be saved by caller function.
  */
-ENTRY(psci_get_cpu_id)
+WEAK(psci_get_cpu_id)
 #ifdef CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER
 	mrs	x9, MPIDR_EL1
 	ubfx	x9, x9, #8, #8
@@ -221,7 +220,6 @@ ENTRY(psci_get_cpu_id)
 	add	x0, x10, x9
 	ret
 ENDPROC(psci_get_cpu_id)
-.weak psci_get_cpu_id
 
 /* CPU ID input in x0, stack top output in x0*/
 LENTRY(psci_get_cpu_stack_top)
@@ -261,10 +259,9 @@ handle_sync:
  * Override this function if custom error handling is
  * needed for asynchronous aborts
  */
-ENTRY(plat_error_handler)
+WEAK(plat_error_handler)
 	ret
 ENDPROC(plat_error_handler)
-.weak plat_error_handler
 
 handle_error:
 	bl	psci_get_cpu_id
@@ -323,9 +320,8 @@ ENTRY(psci_setup_vectors)
 	ret
 ENDPROC(psci_setup_vectors)
 
-ENTRY(psci_arch_init)
+WEAK(psci_arch_init)
 	ret
 ENDPROC(psci_arch_init)
-.weak psci_arch_init
 
 .popsection

+ 2 - 2
arch/arm/cpu/armv8/sec_firmware.c

@@ -198,7 +198,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img,
 		goto out;
 	}
 
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#ifdef CFG_SYS_MEM_RESERVE_SECURE
 	/*
 	 * The SEC Firmware must be stored in secure memory.
 	 * Append SEC Firmware to secure mmu table.
@@ -211,7 +211,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img,
 	sec_firmware_addr = (gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) +
 			gd->arch.tlb_size;
 #else
-#error "The CONFIG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
+#error "The CFG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
 #endif
 
 	/* Align SEC Firmware base address to 4K */

+ 3 - 0
arch/arm/dts/Makefile

@@ -1259,6 +1259,9 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
 dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
 			      k3-am625-r5-sk.dtb
 
+dtb-$(CONFIG_SOC_K3_AM625) += k3-am62a7-sk.dtb \
+			      k3-am62a7-r5-sk.dtb
+
 dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7622-rfb.dtb \
 	mt7623a-unielec-u7623-02-emmc.dtb \

+ 21 - 0
arch/arm/dts/at91-sam9x60_curiosity.dts

@@ -49,6 +49,13 @@
 						atmel,pins =
 							<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
 					};
+
+					usb1 {
+						pinctrl_usb_default: usb_default {
+							atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+									AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+						};
+					};
 			};
 		};
 	};
@@ -89,3 +96,17 @@
 	phy-mode = "rmii";
 	status = "okay";
 };
+
+&usb1 {
+	num-ports = <3>;
+	atmel,vbus-gpio = <0
+			   &pioD 15 GPIO_ACTIVE_HIGH
+			   &pioD 18 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_default>;
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};

+ 25 - 0
arch/arm/dts/at91-sama5d27_wlsom1_ek.dts

@@ -143,7 +143,32 @@
 					pinmux = <PIN_PC9__GPIO>;
 					bias-pull-up;
 				};
+
+				pinctrl_usb_default: usb_default {
+					pinmux = <PIN_PA10__GPIO>;
+					bias-disable;
+				};
+
+				pinctrl_usba_vbus: usba_vbus {
+					pinmux = <PIN_PA16__GPIO>;
+					bias-disable;
+				};
 			};
 		};
 	};
 };
+
+&usb1 {
+	num-ports = <3>;
+	atmel,vbus-gpio = <0
+			   &pioA PIN_PA10 GPIO_ACTIVE_HIGH
+			   0
+			  >;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_default>;
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};

+ 22 - 0
arch/arm/dts/at91-sama5d2_icp.dts

@@ -154,7 +154,29 @@
 						 <PIN_PA13__SDMMC0_CD>;
 					bias-disable;
 				};
+
+				pinctrl_usb_default: usb_default {
+					pinmux = <PIN_PC17__GPIO>;
+					bias-disable;
+				};
+
+				pinctrl_usba_vbus: usba_vbus {
+					pinmux = <PIN_PD23__GPIO>;
+					bias-disable;
+				};
 			};
 		};
 	};
 };
+
+&usb1 {
+	num-ports = <3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_default>;
+	status = "okay";
+};
+
+&usb2 {
+	phy_type = "hsic";
+	status = "okay";
+};

+ 108 - 0
arch/arm/dts/at91-sama7g5ek-u-boot.dtsi

@@ -10,13 +10,88 @@
  *
  */
 
+#include "sama7g5-pinfunc.h"
+#include <dt-bindings/reset/sama7g5-reset.h>
+#include <dt-bindings/clock/at91.h>
+
 / {
 	chosen {
 		u-boot,dm-pre-reloc;
 	};
 
+	utmi {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usb_phy0: phy@0 {
+			compatible = "microchip,sama7g5-usb-phy";
+			sfr-phandle = <&sfr>;
+			reg = <0>;
+			clocks = <&utmi_clk USB_UTMI1>;
+			clock-names = "utmi_clk";
+			status = "disabled";
+			#phy-cells = <0>;
+		};
+
+		usb_phy1: phy@1 {
+			compatible = "microchip,sama7g5-usb-phy";
+			sfr-phandle = <&sfr>;
+			reg = <1>;
+			clocks = <&utmi_clk USB_UTMI2>;
+			clock-names = "utmi_clk";
+			status = "disabled";
+			#phy-cells = <0>;
+		};
+
+		usb_phy2: phy@2 {
+			compatible = "microchip,sama7g5-usb-phy";
+			sfr-phandle = <&sfr>;
+			reg = <2>;
+			clocks = <&utmi_clk USB_UTMI3>;
+			clock-names = "utmi_clk";
+			status = "disabled";
+			#phy-cells = <0>;
+		};
+	};
+
+	utmi_clk: utmi-clk {
+		compatible = "microchip,sama7g5-utmi-clk";
+		sfr-phandle = <&sfr>;
+		#clock-cells = <1>;
+		clocks = <&pmc PMC_TYPE_CORE 27>;
+		clock-names = "utmi_clk";
+		resets = <&reset_controller SAMA7G5_RESET_USB_PHY1>,
+			 <&reset_controller SAMA7G5_RESET_USB_PHY2>,
+			 <&reset_controller SAMA7G5_RESET_USB_PHY3>;
+		reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
+	};
+
 	soc {
 		u-boot,dm-pre-reloc;
+
+		usb2: usb@400000 {
+			compatible = "microchip,sama7g5-ohci", "usb-ohci";
+			reg = <0x00400000 0x100000>;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 106>, <&utmi_clk USB_UTMI1>, <&usb_clk>;
+			clock-names = "ohci_clk", "hclk", "uhpck";
+			status = "disabled";
+		};
+
+		usb3: usb@500000 {
+			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+			reg = <0x00500000 0x100000>;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&usb_clk>, <&pmc PMC_TYPE_PERIPHERAL 106>;
+			clock-names = "usb_clk", "ehci_clk";
+			status = "disabled";
+		};
+
+		sfr: sfr@e1624000 {
+			compatible = "microchip,sama7g5-sfr", "syscon";
+			reg = <0xe1624000 0x4000>;
+		};
 	};
 };
 
@@ -38,6 +113,11 @@
 
 &pioA {
 	u-boot,dm-pre-reloc;
+
+	pinctrl_usb_default: usb_default {
+		pinmux = <PIN_PC6__GPIO>;
+		bias-disable;
+	};
 };
 
 &pit64b0 {
@@ -60,3 +140,31 @@
 	u-boot,dm-pre-reloc;
 };
 
+&usb2 {
+	num-ports = <3>;
+	atmel,vbus-gpio = <0
+			   0
+			   &pioA PIN_PC6 GPIO_ACTIVE_HIGH
+			  >;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_default>;
+	phys = <&usb_phy2>;
+	phy-names = "usb";
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
+
+&usb_phy0 {
+	status = "okay";
+};
+
+&usb_phy1 {
+	status = "okay";
+};
+
+&usb_phy2 {
+	status = "okay";
+};

+ 11 - 12
arch/arm/dts/at91-sama7g5ek.dts

@@ -45,13 +45,13 @@
 		};
 	};
 
-	gpio_keys {
+	gpio-keys {
 		compatible = "gpio-keys";
 
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_key_gpio_default>;
 
-		bp1 {
+		button {
 			label = "PB_USER";
 			gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_PROG1>;
@@ -244,8 +244,8 @@
 			regulators {
 				vdd_3v3: VDD_IO {
 					regulator-name = "VDD_IO";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <3700000>;
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
 					regulator-initial-mode = <2>;
 					regulator-allowed-modes = <2>, <4>;
 					regulator-always-on;
@@ -264,8 +264,8 @@
 
 				vddioddr: VDD_DDR {
 					regulator-name = "VDD_DDR";
-					regulator-min-microvolt = <1300000>;
-					regulator-max-microvolt = <1450000>;
+					regulator-min-microvolt = <1350000>;
+					regulator-max-microvolt = <1350000>;
 					regulator-initial-mode = <2>;
 					regulator-allowed-modes = <2>, <4>;
 					regulator-always-on;
@@ -285,8 +285,8 @@
 
 				vddcore: VDD_CORE {
 					regulator-name = "VDD_CORE";
-					regulator-min-microvolt = <1100000>;
-					regulator-max-microvolt = <1850000>;
+					regulator-min-microvolt = <1150000>;
+					regulator-max-microvolt = <1150000>;
 					regulator-initial-mode = <2>;
 					regulator-allowed-modes = <2>, <4>;
 					regulator-always-on;
@@ -306,7 +306,7 @@
 				vddcpu: VDD_OTHER {
 					regulator-name = "VDD_OTHER";
 					regulator-min-microvolt = <1050000>;
-					regulator-max-microvolt = <1850000>;
+					regulator-max-microvolt = <1250000>;
 					regulator-initial-mode = <2>;
 					regulator-allowed-modes = <2>, <4>;
 					regulator-ramp-delay = <3125>;
@@ -326,8 +326,8 @@
 
 				vldo1: LDO1 {
 					regulator-name = "LDO1";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <3700000>;
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
 					regulator-always-on;
 
 					regulator-state-standby {
@@ -707,7 +707,6 @@
 		ck_cd_rstn_vddsel {
 			pinmux = <PIN_PA0__SDMMC0_CK>,
 				 <PIN_PA2__SDMMC0_RSTN>,
-				 <PIN_PA14__SDMMC0_CD>,
 				 <PIN_PA11__SDMMC0_DS>;
 			slew-rate = <0>;
 			bias-pull-up;

+ 54 - 0
arch/arm/dts/k3-am62-main.dtsi

@@ -165,6 +165,19 @@
 		};
 	};
 
+	crypto: crypto@40900000 {
+		compatible = "ti,am62-sa3ul";
+		reg = <0x00 0x40900000 0x00 0x1200>;
+		power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
+
+		dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
+		       <&main_pktdma 0x7507 0>;
+		dma-names = "tx", "rx1", "rx2";
+	};
+
 	main_pmx0: pinctrl@f4000 {
 		compatible = "pinctrl-single";
 		reg = <0x00 0xf4000 0x00 0x2ac>;
@@ -530,4 +543,45 @@
 		ti,mbox-num-users = <4>;
 		ti,mbox-num-fifos = <16>;
 	};
+
+	ecap0: pwm@23100000 {
+		compatible = "ti,am3352-ecap";
+		#pwm-cells = <3>;
+		reg = <0x00 0x23100000 0x00 0x100>;
+		power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 51 0>;
+		clock-names = "fck";
+	};
+
+	ecap1: pwm@23110000 {
+		compatible = "ti,am3352-ecap";
+		#pwm-cells = <3>;
+		reg = <0x00 0x23110000 0x00 0x100>;
+		power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 52 0>;
+		clock-names = "fck";
+	};
+
+	ecap2: pwm@23120000 {
+		compatible = "ti,am3352-ecap";
+		#pwm-cells = <3>;
+		reg = <0x00 0x23120000 0x00 0x100>;
+		power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 53 0>;
+		clock-names = "fck";
+	};
+
+	main_mcan0: can@20701000 {
+		compatible = "bosch,m_can";
+		reg = <0x00 0x20701000 0x00 0x200>,
+		      <0x00 0x20708000 0x00 0x8000>;
+		reg-names = "m_can", "message_ram";
+		power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
+		clock-names = "hclk", "cclk";
+		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "int0", "int1";
+		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+	};
 };

+ 28 - 0
arch/arm/dts/k3-am62-mcu.dtsi

@@ -53,4 +53,32 @@
 		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 148 0>;
 	};
+
+	mcu_gpio_intr: interrupt-controller@4210000 {
+		compatible = "ti,sci-intr";
+		reg = <0x00 0x04210000 0x00 0x200>;
+		ti,intr-trigger-type = <1>;
+		interrupt-controller;
+		interrupt-parent = <&gic500>;
+		#interrupt-cells = <1>;
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <5>;
+		ti,interrupt-ranges = <0 104 4>;
+	};
+
+	mcu_gpio0: gpio@4201000 {
+		compatible = "ti,am64-gpio", "ti,keystone-gpio";
+		reg = <0x00 0x4201000 0x00 0x100>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&mcu_gpio_intr>;
+		interrupts = <30>, <31>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		ti,ngpio = <24>;
+		ti,davinci-gpio-unbanked = <0>;
+		power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 79 0>;
+		clock-names = "gpio";
+	};
 };

+ 1 - 0
arch/arm/dts/k3-am62.dtsi

@@ -66,6 +66,7 @@
 			 <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
 			 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
 			 <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
+			 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
 			 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
 			 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
 			 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */

+ 5 - 0
arch/arm/dts/k3-am625-r5-sk.dts

@@ -155,3 +155,8 @@
 	status = "okay";
 	u-boot,dm-spl;
 };
+
+&ospi0 {
+	reg = <0x00 0x0fc40000 0x00 0x100>,
+	      <0x00 0x60000000 0x00 0x08000000>;
+};

+ 24 - 0
arch/arm/dts/k3-am625-sk-u-boot.dtsi

@@ -102,3 +102,27 @@
 &main_mmc1_pins_default {
 	u-boot,dm-spl;
 };
+
+&fss {
+	u-boot,dm-spl;
+};
+
+&ospi0_pins_default {
+	u-boot,dm-spl;
+};
+
+&ospi0 {
+	u-boot,dm-spl;
+
+	flash@0 {
+		u-boot,dm-spl;
+
+		partitions {
+			u-boot,dm-spl;
+
+			partition@3fc0000 {
+				u-boot,dm-spl;
+			};
+		};
+	};
+};

+ 354 - 0
arch/arm/dts/k3-am625-sk.dts

@@ -18,7 +18,12 @@
 
 	aliases {
 		serial2 = &main_uart0;
+		mmc0 = &sdhci0;
 		mmc1 = &sdhci1;
+		mmc2 = &sdhci2;
+		spi0 = &ospi0;
+		ethernet0 = &cpsw_port1;
+		ethernet1 = &cpsw_port2;
 	};
 
 	chosen {
@@ -38,6 +43,15 @@
 		#size-cells = <2>;
 		ranges;
 
+		ramoops@9ca00000 {
+			compatible = "ramoops";
+			reg = <0x00 0x9ca00000 0x00 0x00100000>;
+			record-size = <0x8000>;
+			console-size = <0x8000>;
+			ftrace-size = <0x00>;
+			pmsg-size = <0x8000>;
+		};
+
 		secure_tfa_ddr: tfa@9e780000 {
 			reg = <0x00 0x9e780000 0x00 0x80000>;
 			alignment = <0x1000>;
@@ -56,6 +70,79 @@
 			no-map;
 		};
 	};
+
+	vmain_pd: regulator-0 {
+		/* TPS65988 PD CONTROLLER OUTPUT */
+		compatible = "regulator-fixed";
+		regulator-name = "vmain_pd";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_5v0: regulator-1 {
+		/* Output of LM34936 */
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vmain_pd>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_3v3_sys: regulator-2 {
+		/* output of LM61460-Q1 */
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_sys";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vmain_pd>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_mmc1: regulator-3 {
+		/* TPS22918DBVR */
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_mmc1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		enable-active-high;
+		vin-supply = <&vcc_3v3_sys>;
+		gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
+	};
+
+	vdd_sd_dv: regulator-4 {
+		/* Output of TLV71033 */
+		compatible = "regulator-gpio";
+		regulator-name = "tlv71033";
+		pinctrl-names = "default";
+		pinctrl-0 = <&vdd_sd_dv_pins_default>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		vin-supply = <&vcc_5v0>;
+		gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
+		states = <1800000 0x0>,
+			 <3300000 0x1>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&usr_led_pins_default>;
+
+		led-0 {
+			label = "am62-sk:green:heartbeat";
+			gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			function = LED_FUNCTION_HEARTBEAT;
+			default-state = "off";
+		};
+	};
 };
 
 &main_pmx0 {
@@ -66,6 +153,42 @@
 		>;
 	};
 
+	main_i2c0_pins_default: main-i2c0-pins-default {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
+			AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
+		>;
+	};
+
+	main_i2c1_pins_default: main-i2c1-pins-default {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
+			AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
+		>;
+	};
+
+	main_i2c2_pins_default: main-i2c2-pins-default {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
+			AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
+		>;
+	};
+
+	main_mmc0_pins_default: main-mmc0-pins-default {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
+			AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
+			AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
+			AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
+			AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
+			AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
+			AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
+			AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
+			AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
+			AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
+		>;
+	};
+
 	main_mmc1_pins_default: main-mmc1-pins-default {
 		pinctrl-single,pins = <
 			AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
@@ -77,6 +200,81 @@
 			AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
 		>;
 	};
+
+	usr_led_pins_default: usr-led-pins-default {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
+		>;
+	};
+
+	main_mdio1_pins_default: main-mdio1-pins-default {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
+			AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
+		>;
+	};
+
+	main_rgmii1_pins_default: main-rgmii1-pins-default {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
+			AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
+			AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
+			AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
+			AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
+			AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
+			AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
+			AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
+			AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
+			AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
+			AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
+			AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
+		>;
+	};
+
+	main_rgmii2_pins_default: main-rgmii2-pins-default {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
+			AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
+			AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
+			AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
+			AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
+			AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
+			AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
+			AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
+			AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
+			AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
+			AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
+			AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
+		>;
+	};
+
+	ospi0_pins_default: ospi0-pins-default {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
+			AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
+			AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
+			AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
+			AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
+			AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
+			AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
+			AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
+			AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
+			AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
+			AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
+		>;
+	};
+
+	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
+		>;
+	};
+
+	main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
+		>;
+	};
 };
 
 &wkup_uart0 {
@@ -128,10 +326,41 @@
 
 &main_i2c0 {
 	status = "disabled";
+	pinctrl-0 = <&main_i2c0_pins_default>;
+	clock-frequency = <400000>;
 };
 
 &main_i2c1 {
 	status = "disabled";
+	pinctrl-0 = <&main_i2c1_pins_default>;
+	clock-frequency = <400000>;
+
+	exp1: gpio@22 {
+		compatible = "ti,tca6424";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
+				   "PRU_DETECT", "MMC1_SD_EN",
+				   "VPP_LDO_EN", "EXP_PS_3V3_En",
+				   "EXP_PS_5V0_En", "EXP_HAT_DETECT",
+				   "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
+				   "UART1_FET_BUF_EN", "WL_LT_EN",
+				   "GPIO_HDMI_RSTn", "CSI_GPIO1",
+				   "CSI_GPIO2", "PRU_3V3_EN",
+				   "HDMI_INTn", "TEST_GPIO2",
+				   "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
+				   "MCASP1_FET_SEL", "UART1_FET_SEL",
+				   "TSINT#", "IO_EXP_TEST_LED";
+
+		interrupt-parent = <&main_gpio1>;
+		interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
+	};
 };
 
 &main_i2c2 {
@@ -142,9 +371,134 @@
 	status = "disabled";
 };
 
+&sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mmc0_pins_default>;
+	ti,driver-strength-ohm = <50>;
+	disable-wp;
+};
+
 &sdhci1 {
+	/* SD/MMC */
+	vmmc-supply = <&vdd_mmc1>;
+	vqmmc-supply = <&vdd_sd_dv>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_mmc1_pins_default>;
 	ti,driver-strength-ohm = <50>;
 	disable-wp;
 };
+
+&cpsw3g {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mdio1_pins_default
+		     &main_rgmii1_pins_default
+		     &main_rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&cpsw3g_phy1>;
+};
+
+&cpsw3g_mdio {
+	cpsw3g_phy0: ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,min-output-impedance;
+	};
+
+	cpsw3g_phy1: ethernet-phy@1 {
+		reg = <1>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,min-output-impedance;
+	};
+};
+
+&mailbox0_cluster0 {
+	mbox_m4_0: mbox-m4-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+&ospi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ospi0_pins_default>;
+
+	flash@0{
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-tx-bus-width = <8>;
+		spi-rx-bus-width = <8>;
+		spi-max-frequency = <25000000>;
+		cdns,tshsl-ns = <60>;
+		cdns,tsd2d-ns = <60>;
+		cdns,tchsh-ns = <60>;
+		cdns,tslch-ns = <60>;
+		cdns,read-delay = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "ospi.tiboot3";
+				reg = <0x0 0x80000>;
+			};
+
+			partition@80000 {
+				label = "ospi.tispl";
+				reg = <0x80000 0x200000>;
+			};
+
+			partition@280000 {
+				label = "ospi.u-boot";
+				reg = <0x280000 0x400000>;
+			};
+
+			partition@680000 {
+				label = "ospi.env";
+				reg = <0x680000 0x40000>;
+			};
+
+			partition@6c0000 {
+				label = "ospi.env.backup";
+				reg = <0x6c0000 0x40000>;
+			};
+
+			partition@800000 {
+				label = "ospi.rootfs";
+				reg = <0x800000 0x37c0000>;
+			};
+
+			partition@3fc0000 {
+				label = "ospi.phypattern";
+				reg = <0x3fc0000 0x40000>;
+			};
+		};
+	};
+};
+
+&ecap0 {
+	status = "disabled";
+};
+
+&ecap1 {
+	status = "disabled";
+};
+
+&ecap2 {
+	status = "disabled";
+};
+
+&main_mcan0 {
+	status = "disabled";
+};

+ 2798 - 0
arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi

@@ -0,0 +1,2798 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * This file was generated with the
+ * AM62A SysConfig DDR Subsystem Register Configuration Tool v0.09.01
+ * Wed Aug 10 2022 17:34:54 GMT-0500 (Central Daylight Time)
+ * DDR Type: LPDDR4
+ * F0 = 50MHz    F1 = NA     F2 = 1866MHz
+ * Density (per channel): 8Gb
+ * Number of Ranks: 2
+ */
+
+#define DDRSS_PLL_FHS_CNT 5
+#define DDRSS_PLL_FREQUENCY_1 933000000
+#define DDRSS_PLL_FREQUENCY_2 933000000
+
+#define DDRSS_CTL_0_DATA 0x00000B00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x00002710
+#define DDRSS_CTL_8_DATA 0x000186A0
+#define DDRSS_CTL_9_DATA 0x00000005
+#define DDRSS_CTL_10_DATA 0x00000064
+#define DDRSS_CTL_11_DATA 0x0005B18F
+#define DDRSS_CTL_12_DATA 0x0038EF90
+#define DDRSS_CTL_13_DATA 0x00000005
+#define DDRSS_CTL_14_DATA 0x00000E94
+#define DDRSS_CTL_15_DATA 0x0005B18F
+#define DDRSS_CTL_16_DATA 0x0038EF90
+#define DDRSS_CTL_17_DATA 0x00000005
+#define DDRSS_CTL_18_DATA 0x00000E94
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01010100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x0000000A
+#define DDRSS_CTL_24_DATA 0x000186A0
+#define DDRSS_CTL_25_DATA 0x00000000
+#define DDRSS_CTL_26_DATA 0x00000000
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00020200
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x08000010
+#define DDRSS_CTL_35_DATA 0x00004B4B
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x00000000
+#define DDRSS_CTL_39_DATA 0x00000000
+#define DDRSS_CTL_40_DATA 0x0000040C
+#define DDRSS_CTL_41_DATA 0x00000000
+#define DDRSS_CTL_42_DATA 0x00001040
+#define DDRSS_CTL_43_DATA 0x00000000
+#define DDRSS_CTL_44_DATA 0x00001040
+#define DDRSS_CTL_45_DATA 0x00000000
+#define DDRSS_CTL_46_DATA 0x05000804
+#define DDRSS_CTL_47_DATA 0x00000700
+#define DDRSS_CTL_48_DATA 0x09090004
+#define DDRSS_CTL_49_DATA 0x00000303
+#define DDRSS_CTL_50_DATA 0x00720014
+#define DDRSS_CTL_51_DATA 0x09140050
+#define DDRSS_CTL_52_DATA 0x00004D22
+#define DDRSS_CTL_53_DATA 0x00720014
+#define DDRSS_CTL_54_DATA 0x09140050
+#define DDRSS_CTL_55_DATA 0x09004D22
+#define DDRSS_CTL_56_DATA 0x000A0A09
+#define DDRSS_CTL_57_DATA 0x040006DB
+#define DDRSS_CTL_58_DATA 0x090F2005
+#define DDRSS_CTL_59_DATA 0x00001B13
+#define DDRSS_CTL_60_DATA 0x0E00FFCD
+#define DDRSS_CTL_61_DATA 0x090F200F
+#define DDRSS_CTL_62_DATA 0x00001B13
+#define DDRSS_CTL_63_DATA 0x0E00FFCD
+#define DDRSS_CTL_64_DATA 0x0304200F
+#define DDRSS_CTL_65_DATA 0x04050002
+#define DDRSS_CTL_66_DATA 0x24232423
+#define DDRSS_CTL_67_DATA 0x01010008
+#define DDRSS_CTL_68_DATA 0x04464607
+#define DDRSS_CTL_69_DATA 0x03282803
+#define DDRSS_CTL_70_DATA 0x00002828
+#define DDRSS_CTL_71_DATA 0x00000101
+#define DDRSS_CTL_72_DATA 0x00000000
+#define DDRSS_CTL_73_DATA 0x01000000
+#define DDRSS_CTL_74_DATA 0x000E0803
+#define DDRSS_CTL_75_DATA 0x000000BB
+#define DDRSS_CTL_76_DATA 0x0000020B
+#define DDRSS_CTL_77_DATA 0x00001C64
+#define DDRSS_CTL_78_DATA 0x0000020B
+#define DDRSS_CTL_79_DATA 0x00001C64
+#define DDRSS_CTL_80_DATA 0x00000005
+#define DDRSS_CTL_81_DATA 0x00000007
+#define DDRSS_CTL_82_DATA 0x00000010
+#define DDRSS_CTL_83_DATA 0x00000106
+#define DDRSS_CTL_84_DATA 0x00000386
+#define DDRSS_CTL_85_DATA 0x00000106
+#define DDRSS_CTL_86_DATA 0x00000386
+#define DDRSS_CTL_87_DATA 0x03004000
+#define DDRSS_CTL_88_DATA 0x00001201
+#define DDRSS_CTL_89_DATA 0x000E0005
+#define DDRSS_CTL_90_DATA 0x2608000E
+#define DDRSS_CTL_91_DATA 0x0A050526
+#define DDRSS_CTL_92_DATA 0x1B0E0A03
+#define DDRSS_CTL_93_DATA 0x1B0E0A04
+#define DDRSS_CTL_94_DATA 0x04010104
+#define DDRSS_CTL_95_DATA 0x00010401
+#define DDRSS_CTL_96_DATA 0x000F000F
+#define DDRSS_CTL_97_DATA 0x02190219
+#define DDRSS_CTL_98_DATA 0x02190219
+#define DDRSS_CTL_99_DATA 0x00000000
+#define DDRSS_CTL_100_DATA 0x03030000
+#define DDRSS_CTL_101_DATA 0x05050501
+#define DDRSS_CTL_102_DATA 0x04041C04
+#define DDRSS_CTL_103_DATA 0x0E0A0E0A
+#define DDRSS_CTL_104_DATA 0x0A04041C
+#define DDRSS_CTL_105_DATA 0x030E0A0E
+#define DDRSS_CTL_106_DATA 0x00000404
+#define DDRSS_CTL_107_DATA 0x00000301
+#define DDRSS_CTL_108_DATA 0x00000001
+#define DDRSS_CTL_109_DATA 0x00000000
+#define DDRSS_CTL_110_DATA 0x40020100
+#define DDRSS_CTL_111_DATA 0x00038010
+#define DDRSS_CTL_112_DATA 0x00050004
+#define DDRSS_CTL_113_DATA 0x00000004
+#define DDRSS_CTL_114_DATA 0x00040003
+#define DDRSS_CTL_115_DATA 0x00040005
+#define DDRSS_CTL_116_DATA 0x00030000
+#define DDRSS_CTL_117_DATA 0x00050004
+#define DDRSS_CTL_118_DATA 0x00000004
+#define DDRSS_CTL_119_DATA 0x00002EC0
+#define DDRSS_CTL_120_DATA 0x00002EC0
+#define DDRSS_CTL_121_DATA 0x00002EC0
+#define DDRSS_CTL_122_DATA 0x00002EC0
+#define DDRSS_CTL_123_DATA 0x00002EC0
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x0000051D
+#define DDRSS_CTL_126_DATA 0x00071900
+#define DDRSS_CTL_127_DATA 0x00071900
+#define DDRSS_CTL_128_DATA 0x00071900
+#define DDRSS_CTL_129_DATA 0x00071900
+#define DDRSS_CTL_130_DATA 0x00071900
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x0000C6BC
+#define DDRSS_CTL_133_DATA 0x00071900
+#define DDRSS_CTL_134_DATA 0x00071900
+#define DDRSS_CTL_135_DATA 0x00071900
+#define DDRSS_CTL_136_DATA 0x00071900
+#define DDRSS_CTL_137_DATA 0x00071900
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x0000C6BC
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x00000000
+#define DDRSS_CTL_157_DATA 0x00000000
+#define DDRSS_CTL_158_DATA 0x03050000
+#define DDRSS_CTL_159_DATA 0x040A040A
+#define DDRSS_CTL_160_DATA 0x00000000
+#define DDRSS_CTL_161_DATA 0x08010000
+#define DDRSS_CTL_162_DATA 0x000E0808
+#define DDRSS_CTL_163_DATA 0x01000000
+#define DDRSS_CTL_164_DATA 0x0E080808
+#define DDRSS_CTL_165_DATA 0x00000000
+#define DDRSS_CTL_166_DATA 0x08080801
+#define DDRSS_CTL_167_DATA 0x0000080E
+#define DDRSS_CTL_168_DATA 0x00040003
+#define DDRSS_CTL_169_DATA 0x00000007
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x00000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x01000000
+#define DDRSS_CTL_177_DATA 0x00000000
+#define DDRSS_CTL_178_DATA 0x00001700
+#define DDRSS_CTL_179_DATA 0x0000100E
+#define DDRSS_CTL_180_DATA 0x00000002
+#define DDRSS_CTL_181_DATA 0x00000000
+#define DDRSS_CTL_182_DATA 0x00000001
+#define DDRSS_CTL_183_DATA 0x00000002
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00008000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00008000
+#define DDRSS_CTL_188_DATA 0x00000C00
+#define DDRSS_CTL_189_DATA 0x00008000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x00000000
+#define DDRSS_CTL_193_DATA 0x00000000
+#define DDRSS_CTL_194_DATA 0x00000000
+#define DDRSS_CTL_195_DATA 0x0005000A
+#define DDRSS_CTL_196_DATA 0x0404000D
+#define DDRSS_CTL_197_DATA 0x0000000D
+#define DDRSS_CTL_198_DATA 0x00BB0176
+#define DDRSS_CTL_199_DATA 0x0E0E01D3
+#define DDRSS_CTL_200_DATA 0x000001D3
+#define DDRSS_CTL_201_DATA 0x00BB0176
+#define DDRSS_CTL_202_DATA 0x0E0E01D3
+#define DDRSS_CTL_203_DATA 0x000001D3
+#define DDRSS_CTL_204_DATA 0x00000000
+#define DDRSS_CTL_205_DATA 0x00000000
+#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_207_DATA 0x00000000
+#define DDRSS_CTL_208_DATA 0x00000004
+#define DDRSS_CTL_209_DATA 0x00000000
+#define DDRSS_CTL_210_DATA 0x00000000
+#define DDRSS_CTL_211_DATA 0x00000064
+#define DDRSS_CTL_212_DATA 0x00000036
+#define DDRSS_CTL_213_DATA 0x00000000
+#define DDRSS_CTL_214_DATA 0x00000064
+#define DDRSS_CTL_215_DATA 0x00000036
+#define DDRSS_CTL_216_DATA 0x00000000
+#define DDRSS_CTL_217_DATA 0x00000004
+#define DDRSS_CTL_218_DATA 0x00000000
+#define DDRSS_CTL_219_DATA 0x00000000
+#define DDRSS_CTL_220_DATA 0x00000064
+#define DDRSS_CTL_221_DATA 0x00000036
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x00000064
+#define DDRSS_CTL_224_DATA 0x00000036
+#define DDRSS_CTL_225_DATA 0x00000000
+#define DDRSS_CTL_226_DATA 0x00000000
+#define DDRSS_CTL_227_DATA 0x00000031
+#define DDRSS_CTL_228_DATA 0x000000B1
+#define DDRSS_CTL_229_DATA 0x000000B1
+#define DDRSS_CTL_230_DATA 0x00000031
+#define DDRSS_CTL_231_DATA 0x000000B1
+#define DDRSS_CTL_232_DATA 0x000000B1
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000000
+#define DDRSS_CTL_237_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0x00000000
+#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_240_DATA 0x00000000
+#define DDRSS_CTL_241_DATA 0x00000000
+#define DDRSS_CTL_242_DATA 0x00000000
+#define DDRSS_CTL_243_DATA 0x00000000
+#define DDRSS_CTL_244_DATA 0x00000000
+#define DDRSS_CTL_245_DATA 0x00000000
+#define DDRSS_CTL_246_DATA 0x00000000
+#define DDRSS_CTL_247_DATA 0x00000000
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x00000000
+#define DDRSS_CTL_255_DATA 0x00000000
+#define DDRSS_CTL_256_DATA 0x00000000
+#define DDRSS_CTL_257_DATA 0x55005555
+#define DDRSS_CTL_258_DATA 0x00002755
+#define DDRSS_CTL_259_DATA 0x00000027
+#define DDRSS_CTL_260_DATA 0x00000027
+#define DDRSS_CTL_261_DATA 0x00000027
+#define DDRSS_CTL_262_DATA 0x00000027
+#define DDRSS_CTL_263_DATA 0x00000027
+#define DDRSS_CTL_264_DATA 0x00000000
+#define DDRSS_CTL_265_DATA 0x00000000
+#define DDRSS_CTL_266_DATA 0x0000002B
+#define DDRSS_CTL_267_DATA 0x0000002B
+#define DDRSS_CTL_268_DATA 0x0000002B
+#define DDRSS_CTL_269_DATA 0x0000002B
+#define DDRSS_CTL_270_DATA 0x0000002B
+#define DDRSS_CTL_271_DATA 0x0000002B
+#define DDRSS_CTL_272_DATA 0x00000000
+#define DDRSS_CTL_273_DATA 0x00000000
+#define DDRSS_CTL_274_DATA 0x00000016
+#define DDRSS_CTL_275_DATA 0x00000016
+#define DDRSS_CTL_276_DATA 0x00000000
+#define DDRSS_CTL_277_DATA 0x00000016
+#define DDRSS_CTL_278_DATA 0x00000016
+#define DDRSS_CTL_279_DATA 0x00000020
+#define DDRSS_CTL_280_DATA 0x00010000
+#define DDRSS_CTL_281_DATA 0x00000100
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000101
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x00000000
+#define DDRSS_CTL_291_DATA 0x00000000
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x0C181511
+#define DDRSS_CTL_297_DATA 0x00000304
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00000000
+#define DDRSS_CTL_306_DATA 0x00000000
+#define DDRSS_CTL_307_DATA 0x00000000
+#define DDRSS_CTL_308_DATA 0x00000000
+#define DDRSS_CTL_309_DATA 0x00000000
+#define DDRSS_CTL_310_DATA 0x00000000
+#define DDRSS_CTL_311_DATA 0x00020000
+#define DDRSS_CTL_312_DATA 0x00400100
+#define DDRSS_CTL_313_DATA 0x00080032
+#define DDRSS_CTL_314_DATA 0x01000200
+#define DDRSS_CTL_315_DATA 0x074A0040
+#define DDRSS_CTL_316_DATA 0x00020038
+#define DDRSS_CTL_317_DATA 0x00400100
+#define DDRSS_CTL_318_DATA 0x0038074A
+#define DDRSS_CTL_319_DATA 0x00030000
+#define DDRSS_CTL_320_DATA 0x005E005E
+#define DDRSS_CTL_321_DATA 0x00000100
+#define DDRSS_CTL_322_DATA 0x01010000
+#define DDRSS_CTL_323_DATA 0x00000202
+#define DDRSS_CTL_324_DATA 0x0FFF0000
+#define DDRSS_CTL_325_DATA 0x000FFF00
+#define DDRSS_CTL_326_DATA 0x1FFF1000
+#define DDRSS_CTL_327_DATA 0x000FFF00
+#define DDRSS_CTL_328_DATA 0x0B000001
+#define DDRSS_CTL_329_DATA 0x0001FFFF
+#define DDRSS_CTL_330_DATA 0x01010101
+#define DDRSS_CTL_331_DATA 0x01010101
+#define DDRSS_CTL_332_DATA 0x00000118
+#define DDRSS_CTL_333_DATA 0x00000C03
+#define DDRSS_CTL_334_DATA 0x00040100
+#define DDRSS_CTL_335_DATA 0x00040100
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x01030303
+#define DDRSS_CTL_339_DATA 0x00000001
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x00000000
+#define DDRSS_CTL_371_DATA 0x00000000
+#define DDRSS_CTL_372_DATA 0x00000000
+#define DDRSS_CTL_373_DATA 0x00000000
+#define DDRSS_CTL_374_DATA 0x00000000
+#define DDRSS_CTL_375_DATA 0x00000000
+#define DDRSS_CTL_376_DATA 0x00000000
+#define DDRSS_CTL_377_DATA 0x00000000
+#define DDRSS_CTL_378_DATA 0x00000000
+#define DDRSS_CTL_379_DATA 0x00000000
+#define DDRSS_CTL_380_DATA 0x00000000
+#define DDRSS_CTL_381_DATA 0x00000000
+#define DDRSS_CTL_382_DATA 0x00000000
+#define DDRSS_CTL_383_DATA 0x01000101
+#define DDRSS_CTL_384_DATA 0x01010001
+#define DDRSS_CTL_385_DATA 0x00010101
+#define DDRSS_CTL_386_DATA 0x01090903
+#define DDRSS_CTL_387_DATA 0x05020201
+#define DDRSS_CTL_388_DATA 0x0E081B1B
+#define DDRSS_CTL_389_DATA 0x0008030E
+#define DDRSS_CTL_390_DATA 0x0B12030E
+#define DDRSS_CTL_391_DATA 0x0B120314
+#define DDRSS_CTL_392_DATA 0x12120814
+#define DDRSS_CTL_393_DATA 0x01000000
+#define DDRSS_CTL_394_DATA 0x07030701
+#define DDRSS_CTL_395_DATA 0x04000103
+#define DDRSS_CTL_396_DATA 0x1B000004
+#define DDRSS_CTL_397_DATA 0x00000176
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x00000200
+#define DDRSS_CTL_400_DATA 0x00000200
+#define DDRSS_CTL_401_DATA 0x00000200
+#define DDRSS_CTL_402_DATA 0x00000693
+#define DDRSS_CTL_403_DATA 0x00000E9C
+#define DDRSS_CTL_404_DATA 0x03050202
+#define DDRSS_CTL_405_DATA 0x37200201
+#define DDRSS_CTL_406_DATA 0x000038C8
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x00000200
+#define DDRSS_CTL_409_DATA 0x00000200
+#define DDRSS_CTL_410_DATA 0x00000200
+#define DDRSS_CTL_411_DATA 0x0000FF84
+#define DDRSS_CTL_412_DATA 0x000237D0
+#define DDRSS_CTL_413_DATA 0x111F0402
+#define DDRSS_CTL_414_DATA 0x37200C0D
+#define DDRSS_CTL_415_DATA 0x000038C8
+#define DDRSS_CTL_416_DATA 0x00000200
+#define DDRSS_CTL_417_DATA 0x00000200
+#define DDRSS_CTL_418_DATA 0x00000200
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x0000FF84
+#define DDRSS_CTL_421_DATA 0x000237D0
+#define DDRSS_CTL_422_DATA 0x111F0402
+#define DDRSS_CTL_423_DATA 0x00200C0D
+#define DDRSS_CTL_424_DATA 0x00000000
+#define DDRSS_CTL_425_DATA 0x02000A00
+#define DDRSS_CTL_426_DATA 0x00050003
+#define DDRSS_CTL_427_DATA 0x00010101
+#define DDRSS_CTL_428_DATA 0x00010101
+#define DDRSS_CTL_429_DATA 0x00010001
+#define DDRSS_CTL_430_DATA 0x00000101
+#define DDRSS_CTL_431_DATA 0x02000201
+#define DDRSS_CTL_432_DATA 0x02010000
+#define DDRSS_CTL_433_DATA 0x06000200
+#define DDRSS_CTL_434_DATA 0x00002222
+#define DDRSS_PI_0_DATA 0x00000B00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000002
+#define DDRSS_PI_12_DATA 0x00000005
+#define DDRSS_PI_13_DATA 0x000F0001
+#define DDRSS_PI_14_DATA 0x08000000
+#define DDRSS_PI_15_DATA 0x00010300
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00000000
+#define DDRSS_PI_24_DATA 0x00000000
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x01010000
+#define DDRSS_PI_27_DATA 0x0A000100
+#define DDRSS_PI_28_DATA 0x00000028
+#define DDRSS_PI_29_DATA 0x0F000000
+#define DDRSS_PI_30_DATA 0x00320000
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x01010102
+#define DDRSS_PI_34_DATA 0x00000000
+#define DDRSS_PI_35_DATA 0x00000000
+#define DDRSS_PI_36_DATA 0x00000000
+#define DDRSS_PI_37_DATA 0x00000001
+#define DDRSS_PI_38_DATA 0x000000AA
+#define DDRSS_PI_39_DATA 0x00000055
+#define DDRSS_PI_40_DATA 0x000000B5
+#define DDRSS_PI_41_DATA 0x0000004A
+#define DDRSS_PI_42_DATA 0x00000056
+#define DDRSS_PI_43_DATA 0x000000A9
+#define DDRSS_PI_44_DATA 0x000000A9
+#define DDRSS_PI_45_DATA 0x000000B5
+#define DDRSS_PI_46_DATA 0x00000000
+#define DDRSS_PI_47_DATA 0x00000000
+#define DDRSS_PI_48_DATA 0x000F0F00
+#define DDRSS_PI_49_DATA 0x0000001A
+#define DDRSS_PI_50_DATA 0x000007D0
+#define DDRSS_PI_51_DATA 0x00000300
+#define DDRSS_PI_52_DATA 0x00000000
+#define DDRSS_PI_53_DATA 0x00000000
+#define DDRSS_PI_54_DATA 0x01000000
+#define DDRSS_PI_55_DATA 0x00010101
+#define DDRSS_PI_56_DATA 0x01000000
+#define DDRSS_PI_57_DATA 0x03000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x0000170F
+#define DDRSS_PI_60_DATA 0x00000000
+#define DDRSS_PI_61_DATA 0x00000000
+#define DDRSS_PI_62_DATA 0x00000000
+#define DDRSS_PI_63_DATA 0x0A0A140A
+#define DDRSS_PI_64_DATA 0x10020101
+#define DDRSS_PI_65_DATA 0x01000210
+#define DDRSS_PI_66_DATA 0x05000404
+#define DDRSS_PI_67_DATA 0x00010001
+#define DDRSS_PI_68_DATA 0x0001000E
+#define DDRSS_PI_69_DATA 0x01010F00
+#define DDRSS_PI_70_DATA 0x00010000
+#define DDRSS_PI_71_DATA 0x00000034
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x0000FFFF
+#define DDRSS_PI_75_DATA 0x00000000
+#define DDRSS_PI_76_DATA 0x00000000
+#define DDRSS_PI_77_DATA 0x00000000
+#define DDRSS_PI_78_DATA 0x00000000
+#define DDRSS_PI_79_DATA 0x01000000
+#define DDRSS_PI_80_DATA 0x02010001
+#define DDRSS_PI_81_DATA 0x02000008
+#define DDRSS_PI_82_DATA 0x01000200
+#define DDRSS_PI_83_DATA 0x00000100
+#define DDRSS_PI_84_DATA 0x02000100
+#define DDRSS_PI_85_DATA 0x02000200
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000000
+#define DDRSS_PI_92_DATA 0x00000000
+#define DDRSS_PI_93_DATA 0x00000000
+#define DDRSS_PI_94_DATA 0x00000000
+#define DDRSS_PI_95_DATA 0x00000000
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00000000
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x01000400
+#define DDRSS_PI_100_DATA 0x0E0D0F10
+#define DDRSS_PI_101_DATA 0x080A1413
+#define DDRSS_PI_102_DATA 0x01000009
+#define DDRSS_PI_103_DATA 0x00000302
+#define DDRSS_PI_104_DATA 0x00000008
+#define DDRSS_PI_105_DATA 0x08000000
+#define DDRSS_PI_106_DATA 0x00000100
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x0000AA00
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00010000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000000
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00000000
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x00000008
+#define DDRSS_PI_137_DATA 0x00000000
+#define DDRSS_PI_138_DATA 0x00000000
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x00000000
+#define DDRSS_PI_145_DATA 0x00010000
+#define DDRSS_PI_146_DATA 0x00000000
+#define DDRSS_PI_147_DATA 0x00000000
+#define DDRSS_PI_148_DATA 0x0000000A
+#define DDRSS_PI_149_DATA 0x000186A0
+#define DDRSS_PI_150_DATA 0x00000100
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00000000
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x01000000
+#define DDRSS_PI_157_DATA 0x00010003
+#define DDRSS_PI_158_DATA 0x02000101
+#define DDRSS_PI_159_DATA 0x01030001
+#define DDRSS_PI_160_DATA 0x00010400
+#define DDRSS_PI_161_DATA 0x06000105
+#define DDRSS_PI_162_DATA 0x01070001
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00000000
+#define DDRSS_PI_165_DATA 0x00000000
+#define DDRSS_PI_166_DATA 0x00010001
+#define DDRSS_PI_167_DATA 0x00000000
+#define DDRSS_PI_168_DATA 0x00000000
+#define DDRSS_PI_169_DATA 0x00000000
+#define DDRSS_PI_170_DATA 0x00000000
+#define DDRSS_PI_171_DATA 0x00010000
+#define DDRSS_PI_172_DATA 0x00000004
+#define DDRSS_PI_173_DATA 0x00000000
+#define DDRSS_PI_174_DATA 0x00010000
+#define DDRSS_PI_175_DATA 0x00000000
+#define DDRSS_PI_176_DATA 0x00080000
+#define DDRSS_PI_177_DATA 0x01180118
+#define DDRSS_PI_178_DATA 0x00262601
+#define DDRSS_PI_179_DATA 0x00000034
+#define DDRSS_PI_180_DATA 0x0000005E
+#define DDRSS_PI_181_DATA 0x0002005E
+#define DDRSS_PI_182_DATA 0x02000200
+#define DDRSS_PI_183_DATA 0x00000004
+#define DDRSS_PI_184_DATA 0x0000100C
+#define DDRSS_PI_185_DATA 0x00104000
+#define DDRSS_PI_186_DATA 0x00400000
+#define DDRSS_PI_187_DATA 0x0000000E
+#define DDRSS_PI_188_DATA 0x000000BB
+#define DDRSS_PI_189_DATA 0x0000020B
+#define DDRSS_PI_190_DATA 0x00001C64
+#define DDRSS_PI_191_DATA 0x0000020B
+#define DDRSS_PI_192_DATA 0x04001C64
+#define DDRSS_PI_193_DATA 0x01010404
+#define DDRSS_PI_194_DATA 0x00001501
+#define DDRSS_PI_195_DATA 0x00270027
+#define DDRSS_PI_196_DATA 0x01000100
+#define DDRSS_PI_197_DATA 0x00000100
+#define DDRSS_PI_198_DATA 0x00000000
+#define DDRSS_PI_199_DATA 0x05090903
+#define DDRSS_PI_200_DATA 0x01011B1B
+#define DDRSS_PI_201_DATA 0x01010101
+#define DDRSS_PI_202_DATA 0x000C0C0A
+#define DDRSS_PI_203_DATA 0x00000000
+#define DDRSS_PI_204_DATA 0x00000000
+#define DDRSS_PI_205_DATA 0x04000000
+#define DDRSS_PI_206_DATA 0x0C021212
+#define DDRSS_PI_207_DATA 0x0404020C
+#define DDRSS_PI_208_DATA 0x00090031
+#define DDRSS_PI_209_DATA 0x001B0043
+#define DDRSS_PI_210_DATA 0x001B0043
+#define DDRSS_PI_211_DATA 0x01010101
+#define DDRSS_PI_212_DATA 0x0003000D
+#define DDRSS_PI_213_DATA 0x000301D3
+#define DDRSS_PI_214_DATA 0x010001D3
+#define DDRSS_PI_215_DATA 0x000E000E
+#define DDRSS_PI_216_DATA 0x01D40100
+#define DDRSS_PI_217_DATA 0x010001D4
+#define DDRSS_PI_218_DATA 0x01D401D4
+#define DDRSS_PI_219_DATA 0x32103200
+#define DDRSS_PI_220_DATA 0x01013210
+#define DDRSS_PI_221_DATA 0x0A070601
+#define DDRSS_PI_222_DATA 0x1C11090D
+#define DDRSS_PI_223_DATA 0x1C110913
+#define DDRSS_PI_224_DATA 0x000C0013
+#define DDRSS_PI_225_DATA 0x00001000
+#define DDRSS_PI_226_DATA 0x00000C00
+#define DDRSS_PI_227_DATA 0x00001000
+#define DDRSS_PI_228_DATA 0x00000C00
+#define DDRSS_PI_229_DATA 0x02001000
+#define DDRSS_PI_230_DATA 0x0021000D
+#define DDRSS_PI_231_DATA 0x002101D3
+#define DDRSS_PI_232_DATA 0x000001D3
+#define DDRSS_PI_233_DATA 0x00001900
+#define DDRSS_PI_234_DATA 0x32000056
+#define DDRSS_PI_235_DATA 0x06000101
+#define DDRSS_PI_236_DATA 0x00250204
+#define DDRSS_PI_237_DATA 0x3212005A
+#define DDRSS_PI_238_DATA 0x17000101
+#define DDRSS_PI_239_DATA 0x00250C12
+#define DDRSS_PI_240_DATA 0x3212005A
+#define DDRSS_PI_241_DATA 0x17000101
+#define DDRSS_PI_242_DATA 0x00000C12
+#define DDRSS_PI_243_DATA 0x05030900
+#define DDRSS_PI_244_DATA 0x00040900
+#define DDRSS_PI_245_DATA 0x0000062B
+#define DDRSS_PI_246_DATA 0x20010004
+#define DDRSS_PI_247_DATA 0x0A0A0A03
+#define DDRSS_PI_248_DATA 0x280F0000
+#define DDRSS_PI_249_DATA 0x24090023
+#define DDRSS_PI_250_DATA 0x0000E638
+#define DDRSS_PI_251_DATA 0x20070050
+#define DDRSS_PI_252_DATA 0x1B131B1C
+#define DDRSS_PI_253_DATA 0x280F0000
+#define DDRSS_PI_254_DATA 0x24090023
+#define DDRSS_PI_255_DATA 0x0000E638
+#define DDRSS_PI_256_DATA 0x20070050
+#define DDRSS_PI_257_DATA 0x1B131B1C
+#define DDRSS_PI_258_DATA 0x00000000
+#define DDRSS_PI_259_DATA 0x00000176
+#define DDRSS_PI_260_DATA 0x00000E9C
+#define DDRSS_PI_261_DATA 0x000038C8
+#define DDRSS_PI_262_DATA 0x000237D0
+#define DDRSS_PI_263_DATA 0x000038C8
+#define DDRSS_PI_264_DATA 0x000237D0
+#define DDRSS_PI_265_DATA 0x0219000F
+#define DDRSS_PI_266_DATA 0x03030219
+#define DDRSS_PI_267_DATA 0x00000003
+#define DDRSS_PI_268_DATA 0x00000000
+#define DDRSS_PI_269_DATA 0x0A040503
+#define DDRSS_PI_270_DATA 0x00000A04
+#define DDRSS_PI_271_DATA 0x00002710
+#define DDRSS_PI_272_DATA 0x000186A0
+#define DDRSS_PI_273_DATA 0x00000005
+#define DDRSS_PI_274_DATA 0x00000064
+#define DDRSS_PI_275_DATA 0x0000000F
+#define DDRSS_PI_276_DATA 0x0005B18F
+#define DDRSS_PI_277_DATA 0x000186A0
+#define DDRSS_PI_278_DATA 0x00000005
+#define DDRSS_PI_279_DATA 0x00000E94
+#define DDRSS_PI_280_DATA 0x00000219
+#define DDRSS_PI_281_DATA 0x0005B18F
+#define DDRSS_PI_282_DATA 0x000186A0
+#define DDRSS_PI_283_DATA 0x00000005
+#define DDRSS_PI_284_DATA 0x00000E94
+#define DDRSS_PI_285_DATA 0x01000219
+#define DDRSS_PI_286_DATA 0x00320040
+#define DDRSS_PI_287_DATA 0x00010008
+#define DDRSS_PI_288_DATA 0x074A0040
+#define DDRSS_PI_289_DATA 0x00010038
+#define DDRSS_PI_290_DATA 0x074A0040
+#define DDRSS_PI_291_DATA 0x00000338
+#define DDRSS_PI_292_DATA 0x0028005D
+#define DDRSS_PI_293_DATA 0x03040404
+#define DDRSS_PI_294_DATA 0x00000303
+#define DDRSS_PI_295_DATA 0x01010000
+#define DDRSS_PI_296_DATA 0x04040202
+#define DDRSS_PI_297_DATA 0x67670808
+#define DDRSS_PI_298_DATA 0x67676767
+#define DDRSS_PI_299_DATA 0x67676767
+#define DDRSS_PI_300_DATA 0x67676767
+#define DDRSS_PI_301_DATA 0x00006767
+#define DDRSS_PI_302_DATA 0x00000000
+#define DDRSS_PI_303_DATA 0x00000000
+#define DDRSS_PI_304_DATA 0x00000000
+#define DDRSS_PI_305_DATA 0x00000000
+#define DDRSS_PI_306_DATA 0x55000000
+#define DDRSS_PI_307_DATA 0x00000000
+#define DDRSS_PI_308_DATA 0x3C00005A
+#define DDRSS_PI_309_DATA 0x00005500
+#define DDRSS_PI_310_DATA 0x00005A00
+#define DDRSS_PI_311_DATA 0x0055003C
+#define DDRSS_PI_312_DATA 0x00000000
+#define DDRSS_PI_313_DATA 0x3C00005A
+#define DDRSS_PI_314_DATA 0x00005500
+#define DDRSS_PI_315_DATA 0x00005A00
+#define DDRSS_PI_316_DATA 0x1716153C
+#define DDRSS_PI_317_DATA 0x13121118
+#define DDRSS_PI_318_DATA 0x06050414
+#define DDRSS_PI_319_DATA 0x02010007
+#define DDRSS_PI_320_DATA 0x00000003
+#define DDRSS_PI_321_DATA 0x00000000
+#define DDRSS_PI_322_DATA 0x00000000
+#define DDRSS_PI_323_DATA 0x01000000
+#define DDRSS_PI_324_DATA 0x04020201
+#define DDRSS_PI_325_DATA 0x00080804
+#define DDRSS_PI_326_DATA 0x00000000
+#define DDRSS_PI_327_DATA 0x00000000
+#define DDRSS_PI_328_DATA 0x00000000
+#define DDRSS_PI_329_DATA 0x00000004
+#define DDRSS_PI_330_DATA 0x00000000
+#define DDRSS_PI_331_DATA 0x00000031
+#define DDRSS_PI_332_DATA 0x00000000
+#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_334_DATA 0x00000000
+#define DDRSS_PI_335_DATA 0x20002B27
+#define DDRSS_PI_336_DATA 0x00000000
+#define DDRSS_PI_337_DATA 0x00000064
+#define DDRSS_PI_338_DATA 0x00000036
+#define DDRSS_PI_339_DATA 0x000000B1
+#define DDRSS_PI_340_DATA 0x00000000
+#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_342_DATA 0x55000000
+#define DDRSS_PI_343_DATA 0x20162B27
+#define DDRSS_PI_344_DATA 0x00000000
+#define DDRSS_PI_345_DATA 0x00000064
+#define DDRSS_PI_346_DATA 0x00000036
+#define DDRSS_PI_347_DATA 0x000000B1
+#define DDRSS_PI_348_DATA 0x00000000
+#define DDRSS_PI_349_DATA 0x00000000
+#define DDRSS_PI_350_DATA 0x55000000
+#define DDRSS_PI_351_DATA 0x20162B27
+#define DDRSS_PI_352_DATA 0x00000000
+#define DDRSS_PI_353_DATA 0x00000004
+#define DDRSS_PI_354_DATA 0x00000000
+#define DDRSS_PI_355_DATA 0x00000031
+#define DDRSS_PI_356_DATA 0x00000000
+#define DDRSS_PI_357_DATA 0x00000000
+#define DDRSS_PI_358_DATA 0x00000000
+#define DDRSS_PI_359_DATA 0x20002B27
+#define DDRSS_PI_360_DATA 0x00000000
+#define DDRSS_PI_361_DATA 0x00000064
+#define DDRSS_PI_362_DATA 0x00000036
+#define DDRSS_PI_363_DATA 0x000000B1
+#define DDRSS_PI_364_DATA 0x00000000
+#define DDRSS_PI_365_DATA 0x00000000
+#define DDRSS_PI_366_DATA 0x55000000
+#define DDRSS_PI_367_DATA 0x20162B27
+#define DDRSS_PI_368_DATA 0x00000000
+#define DDRSS_PI_369_DATA 0x00000064
+#define DDRSS_PI_370_DATA 0x00000036
+#define DDRSS_PI_371_DATA 0x000000B1
+#define DDRSS_PI_372_DATA 0x00000000
+#define DDRSS_PI_373_DATA 0x00000000
+#define DDRSS_PI_374_DATA 0x55000000
+#define DDRSS_PI_375_DATA 0x20162B27
+#define DDRSS_PI_376_DATA 0x00000000
+#define DDRSS_PI_377_DATA 0x00000004
+#define DDRSS_PI_378_DATA 0x00000000
+#define DDRSS_PI_379_DATA 0x00000031
+#define DDRSS_PI_380_DATA 0x00000000
+#define DDRSS_PI_381_DATA 0x00000000
+#define DDRSS_PI_382_DATA 0x00000000
+#define DDRSS_PI_383_DATA 0x20002B27
+#define DDRSS_PI_384_DATA 0x00000000
+#define DDRSS_PI_385_DATA 0x00000064
+#define DDRSS_PI_386_DATA 0x00000036
+#define DDRSS_PI_387_DATA 0x000000B1
+#define DDRSS_PI_388_DATA 0x00000000
+#define DDRSS_PI_389_DATA 0x00000000
+#define DDRSS_PI_390_DATA 0x55000000
+#define DDRSS_PI_391_DATA 0x20162B27
+#define DDRSS_PI_392_DATA 0x00000000
+#define DDRSS_PI_393_DATA 0x00000064
+#define DDRSS_PI_394_DATA 0x00000036
+#define DDRSS_PI_395_DATA 0x000000B1
+#define DDRSS_PI_396_DATA 0x00000000
+#define DDRSS_PI_397_DATA 0x00000000
+#define DDRSS_PI_398_DATA 0x55000000
+#define DDRSS_PI_399_DATA 0x20162B27
+#define DDRSS_PI_400_DATA 0x00000000
+#define DDRSS_PI_401_DATA 0x00000004
+#define DDRSS_PI_402_DATA 0x00000000
+#define DDRSS_PI_403_DATA 0x00000031
+#define DDRSS_PI_404_DATA 0x00000000
+#define DDRSS_PI_405_DATA 0x00000000
+#define DDRSS_PI_406_DATA 0x00000000
+#define DDRSS_PI_407_DATA 0x20002B27
+#define DDRSS_PI_408_DATA 0x00000000
+#define DDRSS_PI_409_DATA 0x00000064
+#define DDRSS_PI_410_DATA 0x00000036
+#define DDRSS_PI_411_DATA 0x000000B1
+#define DDRSS_PI_412_DATA 0x00000000
+#define DDRSS_PI_413_DATA 0x00000000
+#define DDRSS_PI_414_DATA 0x55000000
+#define DDRSS_PI_415_DATA 0x20162B27
+#define DDRSS_PI_416_DATA 0x00000000
+#define DDRSS_PI_417_DATA 0x00000064
+#define DDRSS_PI_418_DATA 0x00000036
+#define DDRSS_PI_419_DATA 0x000000B1
+#define DDRSS_PI_420_DATA 0x00000000
+#define DDRSS_PI_421_DATA 0x00000000
+#define DDRSS_PI_422_DATA 0x55000000
+#define DDRSS_PI_423_DATA 0x20162B27
+#define DDRSS_PHY_0_DATA 0x04F00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00030200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x01030000
+#define DDRSS_PHY_6_DATA 0x00010000
+#define DDRSS_PHY_7_DATA 0x01030004
+#define DDRSS_PHY_8_DATA 0x01000000
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x00000000
+#define DDRSS_PHY_12_DATA 0x01010000
+#define DDRSS_PHY_13_DATA 0x00010000
+#define DDRSS_PHY_14_DATA 0x00C00001
+#define DDRSS_PHY_15_DATA 0x00CC0008
+#define DDRSS_PHY_16_DATA 0x00660601
+#define DDRSS_PHY_17_DATA 0x00000003
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x00000001
+#define DDRSS_PHY_20_DATA 0x0000AAAA
+#define DDRSS_PHY_21_DATA 0x00005555
+#define DDRSS_PHY_22_DATA 0x0000B5B5
+#define DDRSS_PHY_23_DATA 0x00004A4A
+#define DDRSS_PHY_24_DATA 0x00005656
+#define DDRSS_PHY_25_DATA 0x0000A9A9
+#define DDRSS_PHY_26_DATA 0x0000B7B7
+#define DDRSS_PHY_27_DATA 0x00004848
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x00000000
+#define DDRSS_PHY_30_DATA 0x08000000
+#define DDRSS_PHY_31_DATA 0x0F000008
+#define DDRSS_PHY_32_DATA 0x00000F0F
+#define DDRSS_PHY_33_DATA 0x00E4E400
+#define DDRSS_PHY_34_DATA 0x00071020
+#define DDRSS_PHY_35_DATA 0x000C0020
+#define DDRSS_PHY_36_DATA 0x00062000
+#define DDRSS_PHY_37_DATA 0x00000000
+#define DDRSS_PHY_38_DATA 0x55555555
+#define DDRSS_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS_PHY_40_DATA 0x55555555
+#define DDRSS_PHY_41_DATA 0xAAAAAAAA
+#define DDRSS_PHY_42_DATA 0x00005555
+#define DDRSS_PHY_43_DATA 0x01000100
+#define DDRSS_PHY_44_DATA 0x00800180
+#define DDRSS_PHY_45_DATA 0x00000001
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000000
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000004
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x00000000
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x081F07FF
+#define DDRSS_PHY_75_DATA 0x10200080
+#define DDRSS_PHY_76_DATA 0x00000008
+#define DDRSS_PHY_77_DATA 0x00000401
+#define DDRSS_PHY_78_DATA 0x00000000
+#define DDRSS_PHY_79_DATA 0x01CC0C01
+#define DDRSS_PHY_80_DATA 0x1003CC0C
+#define DDRSS_PHY_81_DATA 0x20000140
+#define DDRSS_PHY_82_DATA 0x07FF0200
+#define DDRSS_PHY_83_DATA 0x0000DD01
+#define DDRSS_PHY_84_DATA 0x00100303
+#define DDRSS_PHY_85_DATA 0x00000000
+#define DDRSS_PHY_86_DATA 0x00000000
+#define DDRSS_PHY_87_DATA 0x00041000
+#define DDRSS_PHY_88_DATA 0x00100010
+#define DDRSS_PHY_89_DATA 0x00100010
+#define DDRSS_PHY_90_DATA 0x00100010
+#define DDRSS_PHY_91_DATA 0x00100010
+#define DDRSS_PHY_92_DATA 0x02040010
+#define DDRSS_PHY_93_DATA 0x00000005
+#define DDRSS_PHY_94_DATA 0x51516042
+#define DDRSS_PHY_95_DATA 0x31C06000
+#define DDRSS_PHY_96_DATA 0x07AB0340
+#define DDRSS_PHY_97_DATA 0x00C0C001
+#define DDRSS_PHY_98_DATA 0x0D000000
+#define DDRSS_PHY_99_DATA 0x000D0C0C
+#define DDRSS_PHY_100_DATA 0x42100010
+#define DDRSS_PHY_101_DATA 0x010C073E
+#define DDRSS_PHY_102_DATA 0x000F0C32
+#define DDRSS_PHY_103_DATA 0x01000140
+#define DDRSS_PHY_104_DATA 0x011E0120
+#define DDRSS_PHY_105_DATA 0x00000C00
+#define DDRSS_PHY_106_DATA 0x000002DD
+#define DDRSS_PHY_107_DATA 0x00030200
+#define DDRSS_PHY_108_DATA 0x02800000
+#define DDRSS_PHY_109_DATA 0x80800000
+#define DDRSS_PHY_110_DATA 0x000D2010
+#define DDRSS_PHY_111_DATA 0x76543210
+#define DDRSS_PHY_112_DATA 0x00000008
+#define DDRSS_PHY_113_DATA 0x045D045D
+#define DDRSS_PHY_114_DATA 0x045D045D
+#define DDRSS_PHY_115_DATA 0x045D045D
+#define DDRSS_PHY_116_DATA 0x045D045D
+#define DDRSS_PHY_117_DATA 0x0000045D
+#define DDRSS_PHY_118_DATA 0x0000A000
+#define DDRSS_PHY_119_DATA 0x00A000A0
+#define DDRSS_PHY_120_DATA 0x00A000A0
+#define DDRSS_PHY_121_DATA 0x00A000A0
+#define DDRSS_PHY_122_DATA 0x00A000A0
+#define DDRSS_PHY_123_DATA 0x00A000A0
+#define DDRSS_PHY_124_DATA 0x00A000A0
+#define DDRSS_PHY_125_DATA 0x00A000A0
+#define DDRSS_PHY_126_DATA 0x00A000A0
+#define DDRSS_PHY_127_DATA 0x00B200A0
+#define DDRSS_PHY_128_DATA 0x01000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00080200
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x20202020
+#define DDRSS_PHY_134_DATA 0x20202020
+#define DDRSS_PHY_135_DATA 0xF0F02020
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04F00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00030200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x01030000
+#define DDRSS_PHY_262_DATA 0x00010000
+#define DDRSS_PHY_263_DATA 0x01030004
+#define DDRSS_PHY_264_DATA 0x01000000
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x00000000
+#define DDRSS_PHY_268_DATA 0x01010000
+#define DDRSS_PHY_269_DATA 0x00010000
+#define DDRSS_PHY_270_DATA 0x00C00001
+#define DDRSS_PHY_271_DATA 0x00CC0008
+#define DDRSS_PHY_272_DATA 0x00660601
+#define DDRSS_PHY_273_DATA 0x00000003
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x00000001
+#define DDRSS_PHY_276_DATA 0x0000AAAA
+#define DDRSS_PHY_277_DATA 0x00005555
+#define DDRSS_PHY_278_DATA 0x0000B5B5
+#define DDRSS_PHY_279_DATA 0x00004A4A
+#define DDRSS_PHY_280_DATA 0x00005656
+#define DDRSS_PHY_281_DATA 0x0000A9A9
+#define DDRSS_PHY_282_DATA 0x0000B7B7
+#define DDRSS_PHY_283_DATA 0x00004848
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x00000000
+#define DDRSS_PHY_286_DATA 0x08000000
+#define DDRSS_PHY_287_DATA 0x0F000008
+#define DDRSS_PHY_288_DATA 0x00000F0F
+#define DDRSS_PHY_289_DATA 0x00E4E400
+#define DDRSS_PHY_290_DATA 0x00071020
+#define DDRSS_PHY_291_DATA 0x000C0020
+#define DDRSS_PHY_292_DATA 0x00062000
+#define DDRSS_PHY_293_DATA 0x00000000
+#define DDRSS_PHY_294_DATA 0x55555555
+#define DDRSS_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS_PHY_296_DATA 0x55555555
+#define DDRSS_PHY_297_DATA 0xAAAAAAAA
+#define DDRSS_PHY_298_DATA 0x00005555
+#define DDRSS_PHY_299_DATA 0x01000100
+#define DDRSS_PHY_300_DATA 0x00800180
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000000
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000004
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x00000000
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x081F07FF
+#define DDRSS_PHY_331_DATA 0x10200080
+#define DDRSS_PHY_332_DATA 0x00000008
+#define DDRSS_PHY_333_DATA 0x00000401
+#define DDRSS_PHY_334_DATA 0x00000000
+#define DDRSS_PHY_335_DATA 0x01CC0C01
+#define DDRSS_PHY_336_DATA 0x1003CC0C
+#define DDRSS_PHY_337_DATA 0x20000140
+#define DDRSS_PHY_338_DATA 0x07FF0200
+#define DDRSS_PHY_339_DATA 0x0000DD01
+#define DDRSS_PHY_340_DATA 0x00100303
+#define DDRSS_PHY_341_DATA 0x00000000
+#define DDRSS_PHY_342_DATA 0x00000000
+#define DDRSS_PHY_343_DATA 0x00041000
+#define DDRSS_PHY_344_DATA 0x00100010
+#define DDRSS_PHY_345_DATA 0x00100010
+#define DDRSS_PHY_346_DATA 0x00100010
+#define DDRSS_PHY_347_DATA 0x00100010
+#define DDRSS_PHY_348_DATA 0x02040010
+#define DDRSS_PHY_349_DATA 0x00000005
+#define DDRSS_PHY_350_DATA 0x51516042
+#define DDRSS_PHY_351_DATA 0x31C06000
+#define DDRSS_PHY_352_DATA 0x07AB0340
+#define DDRSS_PHY_353_DATA 0x00C0C001
+#define DDRSS_PHY_354_DATA 0x0D000000
+#define DDRSS_PHY_355_DATA 0x000D0C0C
+#define DDRSS_PHY_356_DATA 0x42100010
+#define DDRSS_PHY_357_DATA 0x010C073E
+#define DDRSS_PHY_358_DATA 0x000F0C32
+#define DDRSS_PHY_359_DATA 0x01000140
+#define DDRSS_PHY_360_DATA 0x011E0120
+#define DDRSS_PHY_361_DATA 0x00000C00
+#define DDRSS_PHY_362_DATA 0x000002DD
+#define DDRSS_PHY_363_DATA 0x00030200
+#define DDRSS_PHY_364_DATA 0x02800000
+#define DDRSS_PHY_365_DATA 0x80800000
+#define DDRSS_PHY_366_DATA 0x000D2010
+#define DDRSS_PHY_367_DATA 0x76543210
+#define DDRSS_PHY_368_DATA 0x00000008
+#define DDRSS_PHY_369_DATA 0x045D045D
+#define DDRSS_PHY_370_DATA 0x045D045D
+#define DDRSS_PHY_371_DATA 0x045D045D
+#define DDRSS_PHY_372_DATA 0x045D045D
+#define DDRSS_PHY_373_DATA 0x0000045D
+#define DDRSS_PHY_374_DATA 0x0000A000
+#define DDRSS_PHY_375_DATA 0x00A000A0
+#define DDRSS_PHY_376_DATA 0x00A000A0
+#define DDRSS_PHY_377_DATA 0x00A000A0
+#define DDRSS_PHY_378_DATA 0x00A000A0
+#define DDRSS_PHY_379_DATA 0x00A000A0
+#define DDRSS_PHY_380_DATA 0x00A000A0
+#define DDRSS_PHY_381_DATA 0x00A000A0
+#define DDRSS_PHY_382_DATA 0x00A000A0
+#define DDRSS_PHY_383_DATA 0x00B200A0
+#define DDRSS_PHY_384_DATA 0x01000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00080200
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x20202020
+#define DDRSS_PHY_390_DATA 0x20202020
+#define DDRSS_PHY_391_DATA 0xF0F02020
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x04F00000
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00030200
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x01030000
+#define DDRSS_PHY_518_DATA 0x00010000
+#define DDRSS_PHY_519_DATA 0x01030004
+#define DDRSS_PHY_520_DATA 0x01000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00000000
+#define DDRSS_PHY_524_DATA 0x01010000
+#define DDRSS_PHY_525_DATA 0x00010000
+#define DDRSS_PHY_526_DATA 0x00C00001
+#define DDRSS_PHY_527_DATA 0x00CC0008
+#define DDRSS_PHY_528_DATA 0x00660601
+#define DDRSS_PHY_529_DATA 0x00000003
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000001
+#define DDRSS_PHY_532_DATA 0x0000AAAA
+#define DDRSS_PHY_533_DATA 0x00005555
+#define DDRSS_PHY_534_DATA 0x0000B5B5
+#define DDRSS_PHY_535_DATA 0x00004A4A
+#define DDRSS_PHY_536_DATA 0x00005656
+#define DDRSS_PHY_537_DATA 0x0000A9A9
+#define DDRSS_PHY_538_DATA 0x0000B7B7
+#define DDRSS_PHY_539_DATA 0x00004848
+#define DDRSS_PHY_540_DATA 0x00000000
+#define DDRSS_PHY_541_DATA 0x00000000
+#define DDRSS_PHY_542_DATA 0x08000000
+#define DDRSS_PHY_543_DATA 0x0F000008
+#define DDRSS_PHY_544_DATA 0x00000F0F
+#define DDRSS_PHY_545_DATA 0x00E4E400
+#define DDRSS_PHY_546_DATA 0x00071020
+#define DDRSS_PHY_547_DATA 0x000C0020
+#define DDRSS_PHY_548_DATA 0x00062000
+#define DDRSS_PHY_549_DATA 0x00000000
+#define DDRSS_PHY_550_DATA 0x55555555
+#define DDRSS_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS_PHY_552_DATA 0x55555555
+#define DDRSS_PHY_553_DATA 0xAAAAAAAA
+#define DDRSS_PHY_554_DATA 0x00005555
+#define DDRSS_PHY_555_DATA 0x01000100
+#define DDRSS_PHY_556_DATA 0x00800180
+#define DDRSS_PHY_557_DATA 0x00000001
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000004
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x081F07FF
+#define DDRSS_PHY_587_DATA 0x10200080
+#define DDRSS_PHY_588_DATA 0x00000008
+#define DDRSS_PHY_589_DATA 0x00000401
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x01CC0C01
+#define DDRSS_PHY_592_DATA 0x1003CC0C
+#define DDRSS_PHY_593_DATA 0x20000140
+#define DDRSS_PHY_594_DATA 0x07FF0200
+#define DDRSS_PHY_595_DATA 0x0000DD01
+#define DDRSS_PHY_596_DATA 0x00100303
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00041000
+#define DDRSS_PHY_600_DATA 0x00100010
+#define DDRSS_PHY_601_DATA 0x00100010
+#define DDRSS_PHY_602_DATA 0x00100010
+#define DDRSS_PHY_603_DATA 0x00100010
+#define DDRSS_PHY_604_DATA 0x02040010
+#define DDRSS_PHY_605_DATA 0x00000005
+#define DDRSS_PHY_606_DATA 0x51516042
+#define DDRSS_PHY_607_DATA 0x31C06000
+#define DDRSS_PHY_608_DATA 0x07AB0340
+#define DDRSS_PHY_609_DATA 0x00C0C001
+#define DDRSS_PHY_610_DATA 0x0D000000
+#define DDRSS_PHY_611_DATA 0x000D0C0C
+#define DDRSS_PHY_612_DATA 0x42100010
+#define DDRSS_PHY_613_DATA 0x010C073E
+#define DDRSS_PHY_614_DATA 0x000F0C32
+#define DDRSS_PHY_615_DATA 0x01000140
+#define DDRSS_PHY_616_DATA 0x011E0120
+#define DDRSS_PHY_617_DATA 0x00000C00
+#define DDRSS_PHY_618_DATA 0x000002DD
+#define DDRSS_PHY_619_DATA 0x00030200
+#define DDRSS_PHY_620_DATA 0x02800000
+#define DDRSS_PHY_621_DATA 0x80800000
+#define DDRSS_PHY_622_DATA 0x000D2010
+#define DDRSS_PHY_623_DATA 0x76543210
+#define DDRSS_PHY_624_DATA 0x00000008
+#define DDRSS_PHY_625_DATA 0x045D045D
+#define DDRSS_PHY_626_DATA 0x045D045D
+#define DDRSS_PHY_627_DATA 0x045D045D
+#define DDRSS_PHY_628_DATA 0x045D045D
+#define DDRSS_PHY_629_DATA 0x0000045D
+#define DDRSS_PHY_630_DATA 0x0000A000
+#define DDRSS_PHY_631_DATA 0x00A000A0
+#define DDRSS_PHY_632_DATA 0x00A000A0
+#define DDRSS_PHY_633_DATA 0x00A000A0
+#define DDRSS_PHY_634_DATA 0x00A000A0
+#define DDRSS_PHY_635_DATA 0x00A000A0
+#define DDRSS_PHY_636_DATA 0x00A000A0
+#define DDRSS_PHY_637_DATA 0x00A000A0
+#define DDRSS_PHY_638_DATA 0x00A000A0
+#define DDRSS_PHY_639_DATA 0x00B200A0
+#define DDRSS_PHY_640_DATA 0x01000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00080200
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x20202020
+#define DDRSS_PHY_646_DATA 0x20202020
+#define DDRSS_PHY_647_DATA 0xF0F02020
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x04F00000
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00030200
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x01030000
+#define DDRSS_PHY_774_DATA 0x00010000
+#define DDRSS_PHY_775_DATA 0x01030004
+#define DDRSS_PHY_776_DATA 0x01000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00000000
+#define DDRSS_PHY_780_DATA 0x01010000
+#define DDRSS_PHY_781_DATA 0x00010000
+#define DDRSS_PHY_782_DATA 0x00C00001
+#define DDRSS_PHY_783_DATA 0x00CC0008
+#define DDRSS_PHY_784_DATA 0x00660601
+#define DDRSS_PHY_785_DATA 0x00000003
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000001
+#define DDRSS_PHY_788_DATA 0x0000AAAA
+#define DDRSS_PHY_789_DATA 0x00005555
+#define DDRSS_PHY_790_DATA 0x0000B5B5
+#define DDRSS_PHY_791_DATA 0x00004A4A
+#define DDRSS_PHY_792_DATA 0x00005656
+#define DDRSS_PHY_793_DATA 0x0000A9A9
+#define DDRSS_PHY_794_DATA 0x0000B7B7
+#define DDRSS_PHY_795_DATA 0x00004848
+#define DDRSS_PHY_796_DATA 0x00000000
+#define DDRSS_PHY_797_DATA 0x00000000
+#define DDRSS_PHY_798_DATA 0x08000000
+#define DDRSS_PHY_799_DATA 0x0F000008
+#define DDRSS_PHY_800_DATA 0x00000F0F
+#define DDRSS_PHY_801_DATA 0x00E4E400
+#define DDRSS_PHY_802_DATA 0x00071020
+#define DDRSS_PHY_803_DATA 0x000C0020
+#define DDRSS_PHY_804_DATA 0x00062000
+#define DDRSS_PHY_805_DATA 0x00000000
+#define DDRSS_PHY_806_DATA 0x55555555
+#define DDRSS_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS_PHY_808_DATA 0x55555555
+#define DDRSS_PHY_809_DATA 0xAAAAAAAA
+#define DDRSS_PHY_810_DATA 0x00005555
+#define DDRSS_PHY_811_DATA 0x01000100
+#define DDRSS_PHY_812_DATA 0x00800180
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000004
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x081F07FF
+#define DDRSS_PHY_843_DATA 0x10200080
+#define DDRSS_PHY_844_DATA 0x00000008
+#define DDRSS_PHY_845_DATA 0x00000401
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x01CC0C01
+#define DDRSS_PHY_848_DATA 0x1003CC0C
+#define DDRSS_PHY_849_DATA 0x20000140
+#define DDRSS_PHY_850_DATA 0x07FF0200
+#define DDRSS_PHY_851_DATA 0x0000DD01
+#define DDRSS_PHY_852_DATA 0x00100303
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00041000
+#define DDRSS_PHY_856_DATA 0x00100010
+#define DDRSS_PHY_857_DATA 0x00100010
+#define DDRSS_PHY_858_DATA 0x00100010
+#define DDRSS_PHY_859_DATA 0x00100010
+#define DDRSS_PHY_860_DATA 0x02040010
+#define DDRSS_PHY_861_DATA 0x00000005
+#define DDRSS_PHY_862_DATA 0x51516042
+#define DDRSS_PHY_863_DATA 0x31C06000
+#define DDRSS_PHY_864_DATA 0x07AB0340
+#define DDRSS_PHY_865_DATA 0x00C0C001
+#define DDRSS_PHY_866_DATA 0x0D000000
+#define DDRSS_PHY_867_DATA 0x000D0C0C
+#define DDRSS_PHY_868_DATA 0x42100010
+#define DDRSS_PHY_869_DATA 0x010C073E
+#define DDRSS_PHY_870_DATA 0x000F0C32
+#define DDRSS_PHY_871_DATA 0x01000140
+#define DDRSS_PHY_872_DATA 0x011E0120
+#define DDRSS_PHY_873_DATA 0x00000C00
+#define DDRSS_PHY_874_DATA 0x000002DD
+#define DDRSS_PHY_875_DATA 0x00030200
+#define DDRSS_PHY_876_DATA 0x02800000
+#define DDRSS_PHY_877_DATA 0x80800000
+#define DDRSS_PHY_878_DATA 0x000D2010
+#define DDRSS_PHY_879_DATA 0x76543210
+#define DDRSS_PHY_880_DATA 0x00000008
+#define DDRSS_PHY_881_DATA 0x045D045D
+#define DDRSS_PHY_882_DATA 0x045D045D
+#define DDRSS_PHY_883_DATA 0x045D045D
+#define DDRSS_PHY_884_DATA 0x045D045D
+#define DDRSS_PHY_885_DATA 0x0000045D
+#define DDRSS_PHY_886_DATA 0x0000A000
+#define DDRSS_PHY_887_DATA 0x00A000A0
+#define DDRSS_PHY_888_DATA 0x00A000A0
+#define DDRSS_PHY_889_DATA 0x00A000A0
+#define DDRSS_PHY_890_DATA 0x00A000A0
+#define DDRSS_PHY_891_DATA 0x00A000A0
+#define DDRSS_PHY_892_DATA 0x00A000A0
+#define DDRSS_PHY_893_DATA 0x00A000A0
+#define DDRSS_PHY_894_DATA 0x00A000A0
+#define DDRSS_PHY_895_DATA 0x00B200A0
+#define DDRSS_PHY_896_DATA 0x01000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00080200
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x20202020
+#define DDRSS_PHY_902_DATA 0x20202020
+#define DDRSS_PHY_903_DATA 0xF0F02020
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000000
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000200
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00400000
+#define DDRSS_PHY_1036_DATA 0x00000080
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x03000000
+#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x00000000
+#define DDRSS_PHY_1045_DATA 0x0000002A
+#define DDRSS_PHY_1046_DATA 0x00000015
+#define DDRSS_PHY_1047_DATA 0x00000015
+#define DDRSS_PHY_1048_DATA 0x0000002A
+#define DDRSS_PHY_1049_DATA 0x00000033
+#define DDRSS_PHY_1050_DATA 0x0000000C
+#define DDRSS_PHY_1051_DATA 0x0000000C
+#define DDRSS_PHY_1052_DATA 0x00000033
+#define DDRSS_PHY_1053_DATA 0x0A418820
+#define DDRSS_PHY_1054_DATA 0x003F0000
+#define DDRSS_PHY_1055_DATA 0x000F013F
+#define DDRSS_PHY_1056_DATA 0x20202003
+#define DDRSS_PHY_1057_DATA 0x00202020
+#define DDRSS_PHY_1058_DATA 0x20008008
+#define DDRSS_PHY_1059_DATA 0x00000810
+#define DDRSS_PHY_1060_DATA 0x00000F00
+#define DDRSS_PHY_1061_DATA 0x000405CC
+#define DDRSS_PHY_1062_DATA 0x03000004
+#define DDRSS_PHY_1063_DATA 0x00030000
+#define DDRSS_PHY_1064_DATA 0x00000300
+#define DDRSS_PHY_1065_DATA 0x00000300
+#define DDRSS_PHY_1066_DATA 0x00000300
+#define DDRSS_PHY_1067_DATA 0x00000300
+#define DDRSS_PHY_1068_DATA 0x42080010
+#define DDRSS_PHY_1069_DATA 0x0000803E
+#define DDRSS_PHY_1070_DATA 0x00000001
+#define DDRSS_PHY_1071_DATA 0x01000002
+#define DDRSS_PHY_1072_DATA 0x00008000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00000000
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000100
+#define DDRSS_PHY_1286_DATA 0x00000200
+#define DDRSS_PHY_1287_DATA 0x00000000
+#define DDRSS_PHY_1288_DATA 0x00000000
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00400000
+#define DDRSS_PHY_1292_DATA 0x00000080
+#define DDRSS_PHY_1293_DATA 0x00DCBA98
+#define DDRSS_PHY_1294_DATA 0x03000000
+#define DDRSS_PHY_1295_DATA 0x00200000
+#define DDRSS_PHY_1296_DATA 0x00000000
+#define DDRSS_PHY_1297_DATA 0x00000000
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x00000000
+#define DDRSS_PHY_1300_DATA 0x00000000
+#define DDRSS_PHY_1301_DATA 0x0000002A
+#define DDRSS_PHY_1302_DATA 0x00000015
+#define DDRSS_PHY_1303_DATA 0x00000015
+#define DDRSS_PHY_1304_DATA 0x0000002A
+#define DDRSS_PHY_1305_DATA 0x00000033
+#define DDRSS_PHY_1306_DATA 0x0000000C
+#define DDRSS_PHY_1307_DATA 0x0000000C
+#define DDRSS_PHY_1308_DATA 0x00000033
+#define DDRSS_PHY_1309_DATA 0x0A418820
+#define DDRSS_PHY_1310_DATA 0x00000000
+#define DDRSS_PHY_1311_DATA 0x000F0000
+#define DDRSS_PHY_1312_DATA 0x20202003
+#define DDRSS_PHY_1313_DATA 0x00202020
+#define DDRSS_PHY_1314_DATA 0x20008008
+#define DDRSS_PHY_1315_DATA 0x00000810
+#define DDRSS_PHY_1316_DATA 0x00000F00
+#define DDRSS_PHY_1317_DATA 0x000405CC
+#define DDRSS_PHY_1318_DATA 0x03000004
+#define DDRSS_PHY_1319_DATA 0x00030000
+#define DDRSS_PHY_1320_DATA 0x00000300
+#define DDRSS_PHY_1321_DATA 0x00000300
+#define DDRSS_PHY_1322_DATA 0x00000300
+#define DDRSS_PHY_1323_DATA 0x00000300
+#define DDRSS_PHY_1324_DATA 0x42080010
+#define DDRSS_PHY_1325_DATA 0x0000803E
+#define DDRSS_PHY_1326_DATA 0x00000001
+#define DDRSS_PHY_1327_DATA 0x01000002
+#define DDRSS_PHY_1328_DATA 0x00008000
+#define DDRSS_PHY_1329_DATA 0x00000000
+#define DDRSS_PHY_1330_DATA 0x00000000
+#define DDRSS_PHY_1331_DATA 0x00000000
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000000
+#define DDRSS_PHY_1334_DATA 0x00000000
+#define DDRSS_PHY_1335_DATA 0x00000000
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x00000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x00000000
+#define DDRSS_PHY_1346_DATA 0x00000000
+#define DDRSS_PHY_1347_DATA 0x00000000
+#define DDRSS_PHY_1348_DATA 0x00000000
+#define DDRSS_PHY_1349_DATA 0x00000000
+#define DDRSS_PHY_1350_DATA 0x00000000
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000000
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x00000000
+#define DDRSS_PHY_1360_DATA 0x00000000
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00000000
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000000
+#define DDRSS_PHY_1369_DATA 0x00000000
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x00000000
+#define DDRSS_PHY_1372_DATA 0x00000000
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00000000
+#define DDRSS_PHY_1375_DATA 0x00000000
+#define DDRSS_PHY_1376_DATA 0x00000000
+#define DDRSS_PHY_1377_DATA 0x00000000
+#define DDRSS_PHY_1378_DATA 0x00000000
+#define DDRSS_PHY_1379_DATA 0x00000000
+#define DDRSS_PHY_1380_DATA 0x00000000
+#define DDRSS_PHY_1381_DATA 0x00000000
+#define DDRSS_PHY_1382_DATA 0x00000000
+#define DDRSS_PHY_1383_DATA 0x00000000
+#define DDRSS_PHY_1384_DATA 0x00000000
+#define DDRSS_PHY_1385_DATA 0x00000000
+#define DDRSS_PHY_1386_DATA 0x00000000
+#define DDRSS_PHY_1387_DATA 0x00000000
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x00000000
+#define DDRSS_PHY_1390_DATA 0x00000000
+#define DDRSS_PHY_1391_DATA 0x00000000
+#define DDRSS_PHY_1392_DATA 0x00000000
+#define DDRSS_PHY_1393_DATA 0x00000000
+#define DDRSS_PHY_1394_DATA 0x00000000
+#define DDRSS_PHY_1395_DATA 0x00000000
+#define DDRSS_PHY_1396_DATA 0x00000000
+#define DDRSS_PHY_1397_DATA 0x00000000
+#define DDRSS_PHY_1398_DATA 0x00000000
+#define DDRSS_PHY_1399_DATA 0x00000000
+#define DDRSS_PHY_1400_DATA 0x00000000
+#define DDRSS_PHY_1401_DATA 0x00000000
+#define DDRSS_PHY_1402_DATA 0x00000000
+#define DDRSS_PHY_1403_DATA 0x00000000
+#define DDRSS_PHY_1404_DATA 0x00000000
+#define DDRSS_PHY_1405_DATA 0x00000000
+#define DDRSS_PHY_1406_DATA 0x00000000
+#define DDRSS_PHY_1407_DATA 0x00000000
+#define DDRSS_PHY_1408_DATA 0x00000000
+#define DDRSS_PHY_1409_DATA 0x00000000
+#define DDRSS_PHY_1410_DATA 0x00000000
+#define DDRSS_PHY_1411_DATA 0x00000000
+#define DDRSS_PHY_1412_DATA 0x00000000
+#define DDRSS_PHY_1413_DATA 0x00000000
+#define DDRSS_PHY_1414_DATA 0x00000000
+#define DDRSS_PHY_1415_DATA 0x00000000
+#define DDRSS_PHY_1416_DATA 0x00000000
+#define DDRSS_PHY_1417_DATA 0x00000000
+#define DDRSS_PHY_1418_DATA 0x00000000
+#define DDRSS_PHY_1419_DATA 0x00000000
+#define DDRSS_PHY_1420_DATA 0x00000000
+#define DDRSS_PHY_1421_DATA 0x00000000
+#define DDRSS_PHY_1422_DATA 0x00000000
+#define DDRSS_PHY_1423_DATA 0x00000000
+#define DDRSS_PHY_1424_DATA 0x00000000
+#define DDRSS_PHY_1425_DATA 0x00000000
+#define DDRSS_PHY_1426_DATA 0x00000000
+#define DDRSS_PHY_1427_DATA 0x00000000
+#define DDRSS_PHY_1428_DATA 0x00000000
+#define DDRSS_PHY_1429_DATA 0x00000000
+#define DDRSS_PHY_1430_DATA 0x00000000
+#define DDRSS_PHY_1431_DATA 0x00000000
+#define DDRSS_PHY_1432_DATA 0x00000000
+#define DDRSS_PHY_1433_DATA 0x00000000
+#define DDRSS_PHY_1434_DATA 0x00000000
+#define DDRSS_PHY_1435_DATA 0x00000000
+#define DDRSS_PHY_1436_DATA 0x00000000
+#define DDRSS_PHY_1437_DATA 0x00000000
+#define DDRSS_PHY_1438_DATA 0x00000000
+#define DDRSS_PHY_1439_DATA 0x00000000
+#define DDRSS_PHY_1440_DATA 0x00000000
+#define DDRSS_PHY_1441_DATA 0x00000000
+#define DDRSS_PHY_1442_DATA 0x00000000
+#define DDRSS_PHY_1443_DATA 0x00000000
+#define DDRSS_PHY_1444_DATA 0x00000000
+#define DDRSS_PHY_1445_DATA 0x00000000
+#define DDRSS_PHY_1446_DATA 0x00000000
+#define DDRSS_PHY_1447_DATA 0x00000000
+#define DDRSS_PHY_1448_DATA 0x00000000
+#define DDRSS_PHY_1449_DATA 0x00000000
+#define DDRSS_PHY_1450_DATA 0x00000000
+#define DDRSS_PHY_1451_DATA 0x00000000
+#define DDRSS_PHY_1452_DATA 0x00000000
+#define DDRSS_PHY_1453_DATA 0x00000000
+#define DDRSS_PHY_1454_DATA 0x00000000
+#define DDRSS_PHY_1455_DATA 0x00000000
+#define DDRSS_PHY_1456_DATA 0x00000000
+#define DDRSS_PHY_1457_DATA 0x00000000
+#define DDRSS_PHY_1458_DATA 0x00000000
+#define DDRSS_PHY_1459_DATA 0x00000000
+#define DDRSS_PHY_1460_DATA 0x00000000
+#define DDRSS_PHY_1461_DATA 0x00000000
+#define DDRSS_PHY_1462_DATA 0x00000000
+#define DDRSS_PHY_1463_DATA 0x00000000
+#define DDRSS_PHY_1464_DATA 0x00000000
+#define DDRSS_PHY_1465_DATA 0x00000000
+#define DDRSS_PHY_1466_DATA 0x00000000
+#define DDRSS_PHY_1467_DATA 0x00000000
+#define DDRSS_PHY_1468_DATA 0x00000000
+#define DDRSS_PHY_1469_DATA 0x00000000
+#define DDRSS_PHY_1470_DATA 0x00000000
+#define DDRSS_PHY_1471_DATA 0x00000000
+#define DDRSS_PHY_1472_DATA 0x00000000
+#define DDRSS_PHY_1473_DATA 0x00000000
+#define DDRSS_PHY_1474_DATA 0x00000000
+#define DDRSS_PHY_1475_DATA 0x00000000
+#define DDRSS_PHY_1476_DATA 0x00000000
+#define DDRSS_PHY_1477_DATA 0x00000000
+#define DDRSS_PHY_1478_DATA 0x00000000
+#define DDRSS_PHY_1479_DATA 0x00000000
+#define DDRSS_PHY_1480_DATA 0x00000000
+#define DDRSS_PHY_1481_DATA 0x00000000
+#define DDRSS_PHY_1482_DATA 0x00000000
+#define DDRSS_PHY_1483_DATA 0x00000000
+#define DDRSS_PHY_1484_DATA 0x00000000
+#define DDRSS_PHY_1485_DATA 0x00000000
+#define DDRSS_PHY_1486_DATA 0x00000000
+#define DDRSS_PHY_1487_DATA 0x00000000
+#define DDRSS_PHY_1488_DATA 0x00000000
+#define DDRSS_PHY_1489_DATA 0x00000000
+#define DDRSS_PHY_1490_DATA 0x00000000
+#define DDRSS_PHY_1491_DATA 0x00000000
+#define DDRSS_PHY_1492_DATA 0x00000000
+#define DDRSS_PHY_1493_DATA 0x00000000
+#define DDRSS_PHY_1494_DATA 0x00000000
+#define DDRSS_PHY_1495_DATA 0x00000000
+#define DDRSS_PHY_1496_DATA 0x00000000
+#define DDRSS_PHY_1497_DATA 0x00000000
+#define DDRSS_PHY_1498_DATA 0x00000000
+#define DDRSS_PHY_1499_DATA 0x00000000
+#define DDRSS_PHY_1500_DATA 0x00000000
+#define DDRSS_PHY_1501_DATA 0x00000000
+#define DDRSS_PHY_1502_DATA 0x00000000
+#define DDRSS_PHY_1503_DATA 0x00000000
+#define DDRSS_PHY_1504_DATA 0x00000000
+#define DDRSS_PHY_1505_DATA 0x00000000
+#define DDRSS_PHY_1506_DATA 0x00000000
+#define DDRSS_PHY_1507_DATA 0x00000000
+#define DDRSS_PHY_1508_DATA 0x00000000
+#define DDRSS_PHY_1509_DATA 0x00000000
+#define DDRSS_PHY_1510_DATA 0x00000000
+#define DDRSS_PHY_1511_DATA 0x00000000
+#define DDRSS_PHY_1512_DATA 0x00000000
+#define DDRSS_PHY_1513_DATA 0x00000000
+#define DDRSS_PHY_1514_DATA 0x00000000
+#define DDRSS_PHY_1515_DATA 0x00000000
+#define DDRSS_PHY_1516_DATA 0x00000000
+#define DDRSS_PHY_1517_DATA 0x00000000
+#define DDRSS_PHY_1518_DATA 0x00000000
+#define DDRSS_PHY_1519_DATA 0x00000000
+#define DDRSS_PHY_1520_DATA 0x00000000
+#define DDRSS_PHY_1521_DATA 0x00000000
+#define DDRSS_PHY_1522_DATA 0x00000000
+#define DDRSS_PHY_1523_DATA 0x00000000
+#define DDRSS_PHY_1524_DATA 0x00000000
+#define DDRSS_PHY_1525_DATA 0x00000000
+#define DDRSS_PHY_1526_DATA 0x00000000
+#define DDRSS_PHY_1527_DATA 0x00000000
+#define DDRSS_PHY_1528_DATA 0x00000000
+#define DDRSS_PHY_1529_DATA 0x00000000
+#define DDRSS_PHY_1530_DATA 0x00000000
+#define DDRSS_PHY_1531_DATA 0x00000000
+#define DDRSS_PHY_1532_DATA 0x00000000
+#define DDRSS_PHY_1533_DATA 0x00000000
+#define DDRSS_PHY_1534_DATA 0x00000000
+#define DDRSS_PHY_1535_DATA 0x00000000
+#define DDRSS_PHY_1536_DATA 0x00000000
+#define DDRSS_PHY_1537_DATA 0x00000000
+#define DDRSS_PHY_1538_DATA 0x00000000
+#define DDRSS_PHY_1539_DATA 0x00000000
+#define DDRSS_PHY_1540_DATA 0x00000000
+#define DDRSS_PHY_1541_DATA 0x00000100
+#define DDRSS_PHY_1542_DATA 0x00000200
+#define DDRSS_PHY_1543_DATA 0x00000000
+#define DDRSS_PHY_1544_DATA 0x00000000
+#define DDRSS_PHY_1545_DATA 0x00000000
+#define DDRSS_PHY_1546_DATA 0x00000000
+#define DDRSS_PHY_1547_DATA 0x00400000
+#define DDRSS_PHY_1548_DATA 0x00000080
+#define DDRSS_PHY_1549_DATA 0x00DCBA98
+#define DDRSS_PHY_1550_DATA 0x03000000
+#define DDRSS_PHY_1551_DATA 0x00200000
+#define DDRSS_PHY_1552_DATA 0x00000000
+#define DDRSS_PHY_1553_DATA 0x00000000
+#define DDRSS_PHY_1554_DATA 0x00000000
+#define DDRSS_PHY_1555_DATA 0x00000000
+#define DDRSS_PHY_1556_DATA 0x00000000
+#define DDRSS_PHY_1557_DATA 0x0000002A
+#define DDRSS_PHY_1558_DATA 0x00000015
+#define DDRSS_PHY_1559_DATA 0x00000015
+#define DDRSS_PHY_1560_DATA 0x0000002A
+#define DDRSS_PHY_1561_DATA 0x00000033
+#define DDRSS_PHY_1562_DATA 0x0000000C
+#define DDRSS_PHY_1563_DATA 0x0000000C
+#define DDRSS_PHY_1564_DATA 0x00000033
+#define DDRSS_PHY_1565_DATA 0x0A418820
+#define DDRSS_PHY_1566_DATA 0x10000000
+#define DDRSS_PHY_1567_DATA 0x000F0000
+#define DDRSS_PHY_1568_DATA 0x20202003
+#define DDRSS_PHY_1569_DATA 0x00202020
+#define DDRSS_PHY_1570_DATA 0x20008008
+#define DDRSS_PHY_1571_DATA 0x00000810
+#define DDRSS_PHY_1572_DATA 0x00000F00
+#define DDRSS_PHY_1573_DATA 0x000405CC
+#define DDRSS_PHY_1574_DATA 0x03000004
+#define DDRSS_PHY_1575_DATA 0x00030000
+#define DDRSS_PHY_1576_DATA 0x00000300
+#define DDRSS_PHY_1577_DATA 0x00000300
+#define DDRSS_PHY_1578_DATA 0x00000300
+#define DDRSS_PHY_1579_DATA 0x00000300
+#define DDRSS_PHY_1580_DATA 0x42080010
+#define DDRSS_PHY_1581_DATA 0x0000803E
+#define DDRSS_PHY_1582_DATA 0x00000001
+#define DDRSS_PHY_1583_DATA 0x01000002
+#define DDRSS_PHY_1584_DATA 0x00008000
+#define DDRSS_PHY_1585_DATA 0x00000000
+#define DDRSS_PHY_1586_DATA 0x00000000
+#define DDRSS_PHY_1587_DATA 0x00000000
+#define DDRSS_PHY_1588_DATA 0x00000000
+#define DDRSS_PHY_1589_DATA 0x00000000
+#define DDRSS_PHY_1590_DATA 0x00000000
+#define DDRSS_PHY_1591_DATA 0x00000000
+#define DDRSS_PHY_1592_DATA 0x00000000
+#define DDRSS_PHY_1593_DATA 0x00000000
+#define DDRSS_PHY_1594_DATA 0x00000000
+#define DDRSS_PHY_1595_DATA 0x00000000
+#define DDRSS_PHY_1596_DATA 0x00000000
+#define DDRSS_PHY_1597_DATA 0x00000000
+#define DDRSS_PHY_1598_DATA 0x00000000
+#define DDRSS_PHY_1599_DATA 0x00000000
+#define DDRSS_PHY_1600_DATA 0x00000000
+#define DDRSS_PHY_1601_DATA 0x00000000
+#define DDRSS_PHY_1602_DATA 0x00000000
+#define DDRSS_PHY_1603_DATA 0x00000000
+#define DDRSS_PHY_1604_DATA 0x00000000
+#define DDRSS_PHY_1605_DATA 0x00000000
+#define DDRSS_PHY_1606_DATA 0x00000000
+#define DDRSS_PHY_1607_DATA 0x00000000
+#define DDRSS_PHY_1608_DATA 0x00000000
+#define DDRSS_PHY_1609_DATA 0x00000000
+#define DDRSS_PHY_1610_DATA 0x00000000
+#define DDRSS_PHY_1611_DATA 0x00000000
+#define DDRSS_PHY_1612_DATA 0x00000000
+#define DDRSS_PHY_1613_DATA 0x00000000
+#define DDRSS_PHY_1614_DATA 0x00000000
+#define DDRSS_PHY_1615_DATA 0x00000000
+#define DDRSS_PHY_1616_DATA 0x00000000
+#define DDRSS_PHY_1617_DATA 0x00000000
+#define DDRSS_PHY_1618_DATA 0x00000000
+#define DDRSS_PHY_1619_DATA 0x00000000
+#define DDRSS_PHY_1620_DATA 0x00000000
+#define DDRSS_PHY_1621_DATA 0x00000000
+#define DDRSS_PHY_1622_DATA 0x00000000
+#define DDRSS_PHY_1623_DATA 0x00000000
+#define DDRSS_PHY_1624_DATA 0x00000000
+#define DDRSS_PHY_1625_DATA 0x00000000
+#define DDRSS_PHY_1626_DATA 0x00000000
+#define DDRSS_PHY_1627_DATA 0x00000000
+#define DDRSS_PHY_1628_DATA 0x00000000
+#define DDRSS_PHY_1629_DATA 0x00000000
+#define DDRSS_PHY_1630_DATA 0x00000000
+#define DDRSS_PHY_1631_DATA 0x00000000
+#define DDRSS_PHY_1632_DATA 0x00000000
+#define DDRSS_PHY_1633_DATA 0x00000000
+#define DDRSS_PHY_1634_DATA 0x00000000
+#define DDRSS_PHY_1635_DATA 0x00000000
+#define DDRSS_PHY_1636_DATA 0x00000000
+#define DDRSS_PHY_1637_DATA 0x00000000
+#define DDRSS_PHY_1638_DATA 0x00000000
+#define DDRSS_PHY_1639_DATA 0x00000000
+#define DDRSS_PHY_1640_DATA 0x00000000
+#define DDRSS_PHY_1641_DATA 0x00000000
+#define DDRSS_PHY_1642_DATA 0x00000000
+#define DDRSS_PHY_1643_DATA 0x00000000
+#define DDRSS_PHY_1644_DATA 0x00000000
+#define DDRSS_PHY_1645_DATA 0x00000000
+#define DDRSS_PHY_1646_DATA 0x00000000
+#define DDRSS_PHY_1647_DATA 0x00000000
+#define DDRSS_PHY_1648_DATA 0x00000000
+#define DDRSS_PHY_1649_DATA 0x00000000
+#define DDRSS_PHY_1650_DATA 0x00000000
+#define DDRSS_PHY_1651_DATA 0x00000000
+#define DDRSS_PHY_1652_DATA 0x00000000
+#define DDRSS_PHY_1653_DATA 0x00000000
+#define DDRSS_PHY_1654_DATA 0x00000000
+#define DDRSS_PHY_1655_DATA 0x00000000
+#define DDRSS_PHY_1656_DATA 0x00000000
+#define DDRSS_PHY_1657_DATA 0x00000000
+#define DDRSS_PHY_1658_DATA 0x00000000
+#define DDRSS_PHY_1659_DATA 0x00000000
+#define DDRSS_PHY_1660_DATA 0x00000000
+#define DDRSS_PHY_1661_DATA 0x00000000
+#define DDRSS_PHY_1662_DATA 0x00000000
+#define DDRSS_PHY_1663_DATA 0x00000000
+#define DDRSS_PHY_1664_DATA 0x00000000
+#define DDRSS_PHY_1665_DATA 0x00000000
+#define DDRSS_PHY_1666_DATA 0x00000000
+#define DDRSS_PHY_1667_DATA 0x00000000
+#define DDRSS_PHY_1668_DATA 0x00000000
+#define DDRSS_PHY_1669_DATA 0x00000000
+#define DDRSS_PHY_1670_DATA 0x00000000
+#define DDRSS_PHY_1671_DATA 0x00000000
+#define DDRSS_PHY_1672_DATA 0x00000000
+#define DDRSS_PHY_1673_DATA 0x00000000
+#define DDRSS_PHY_1674_DATA 0x00000000
+#define DDRSS_PHY_1675_DATA 0x00000000
+#define DDRSS_PHY_1676_DATA 0x00000000
+#define DDRSS_PHY_1677_DATA 0x00000000
+#define DDRSS_PHY_1678_DATA 0x00000000
+#define DDRSS_PHY_1679_DATA 0x00000000
+#define DDRSS_PHY_1680_DATA 0x00000000
+#define DDRSS_PHY_1681_DATA 0x00000000
+#define DDRSS_PHY_1682_DATA 0x00000000
+#define DDRSS_PHY_1683_DATA 0x00000000
+#define DDRSS_PHY_1684_DATA 0x00000000
+#define DDRSS_PHY_1685_DATA 0x00000000
+#define DDRSS_PHY_1686_DATA 0x00000000
+#define DDRSS_PHY_1687_DATA 0x00000000
+#define DDRSS_PHY_1688_DATA 0x00000000
+#define DDRSS_PHY_1689_DATA 0x00000000
+#define DDRSS_PHY_1690_DATA 0x00000000
+#define DDRSS_PHY_1691_DATA 0x00000000
+#define DDRSS_PHY_1692_DATA 0x00000000
+#define DDRSS_PHY_1693_DATA 0x00000000
+#define DDRSS_PHY_1694_DATA 0x00000000
+#define DDRSS_PHY_1695_DATA 0x00000000
+#define DDRSS_PHY_1696_DATA 0x00000000
+#define DDRSS_PHY_1697_DATA 0x00000000
+#define DDRSS_PHY_1698_DATA 0x00000000
+#define DDRSS_PHY_1699_DATA 0x00000000
+#define DDRSS_PHY_1700_DATA 0x00000000
+#define DDRSS_PHY_1701_DATA 0x00000000
+#define DDRSS_PHY_1702_DATA 0x00000000
+#define DDRSS_PHY_1703_DATA 0x00000000
+#define DDRSS_PHY_1704_DATA 0x00000000
+#define DDRSS_PHY_1705_DATA 0x00000000
+#define DDRSS_PHY_1706_DATA 0x00000000
+#define DDRSS_PHY_1707_DATA 0x00000000
+#define DDRSS_PHY_1708_DATA 0x00000000
+#define DDRSS_PHY_1709_DATA 0x00000000
+#define DDRSS_PHY_1710_DATA 0x00000000
+#define DDRSS_PHY_1711_DATA 0x00000000
+#define DDRSS_PHY_1712_DATA 0x00000000
+#define DDRSS_PHY_1713_DATA 0x00000000
+#define DDRSS_PHY_1714_DATA 0x00000000
+#define DDRSS_PHY_1715_DATA 0x00000000
+#define DDRSS_PHY_1716_DATA 0x00000000
+#define DDRSS_PHY_1717_DATA 0x00000000
+#define DDRSS_PHY_1718_DATA 0x00000000
+#define DDRSS_PHY_1719_DATA 0x00000000
+#define DDRSS_PHY_1720_DATA 0x00000000
+#define DDRSS_PHY_1721_DATA 0x00000000
+#define DDRSS_PHY_1722_DATA 0x00000000
+#define DDRSS_PHY_1723_DATA 0x00000000
+#define DDRSS_PHY_1724_DATA 0x00000000
+#define DDRSS_PHY_1725_DATA 0x00000000
+#define DDRSS_PHY_1726_DATA 0x00000000
+#define DDRSS_PHY_1727_DATA 0x00000000
+#define DDRSS_PHY_1728_DATA 0x00000000
+#define DDRSS_PHY_1729_DATA 0x00000000
+#define DDRSS_PHY_1730_DATA 0x00000000
+#define DDRSS_PHY_1731_DATA 0x00000000
+#define DDRSS_PHY_1732_DATA 0x00000000
+#define DDRSS_PHY_1733_DATA 0x00000000
+#define DDRSS_PHY_1734_DATA 0x00000000
+#define DDRSS_PHY_1735_DATA 0x00000000
+#define DDRSS_PHY_1736_DATA 0x00000000
+#define DDRSS_PHY_1737_DATA 0x00000000
+#define DDRSS_PHY_1738_DATA 0x00000000
+#define DDRSS_PHY_1739_DATA 0x00000000
+#define DDRSS_PHY_1740_DATA 0x00000000
+#define DDRSS_PHY_1741_DATA 0x00000000
+#define DDRSS_PHY_1742_DATA 0x00000000
+#define DDRSS_PHY_1743_DATA 0x00000000
+#define DDRSS_PHY_1744_DATA 0x00000000
+#define DDRSS_PHY_1745_DATA 0x00000000
+#define DDRSS_PHY_1746_DATA 0x00000000
+#define DDRSS_PHY_1747_DATA 0x00000000
+#define DDRSS_PHY_1748_DATA 0x00000000
+#define DDRSS_PHY_1749_DATA 0x00000000
+#define DDRSS_PHY_1750_DATA 0x00000000
+#define DDRSS_PHY_1751_DATA 0x00000000
+#define DDRSS_PHY_1752_DATA 0x00000000
+#define DDRSS_PHY_1753_DATA 0x00000000
+#define DDRSS_PHY_1754_DATA 0x00000000
+#define DDRSS_PHY_1755_DATA 0x00000000
+#define DDRSS_PHY_1756_DATA 0x00000000
+#define DDRSS_PHY_1757_DATA 0x00000000
+#define DDRSS_PHY_1758_DATA 0x00000000
+#define DDRSS_PHY_1759_DATA 0x00000000
+#define DDRSS_PHY_1760_DATA 0x00000000
+#define DDRSS_PHY_1761_DATA 0x00000000
+#define DDRSS_PHY_1762_DATA 0x00000000
+#define DDRSS_PHY_1763_DATA 0x00000000
+#define DDRSS_PHY_1764_DATA 0x00000000
+#define DDRSS_PHY_1765_DATA 0x00000000
+#define DDRSS_PHY_1766_DATA 0x00000000
+#define DDRSS_PHY_1767_DATA 0x00000000
+#define DDRSS_PHY_1768_DATA 0x00000000
+#define DDRSS_PHY_1769_DATA 0x00000000
+#define DDRSS_PHY_1770_DATA 0x00000000
+#define DDRSS_PHY_1771_DATA 0x00000000
+#define DDRSS_PHY_1772_DATA 0x00000000
+#define DDRSS_PHY_1773_DATA 0x00000000
+#define DDRSS_PHY_1774_DATA 0x00000000
+#define DDRSS_PHY_1775_DATA 0x00000000
+#define DDRSS_PHY_1776_DATA 0x00000000
+#define DDRSS_PHY_1777_DATA 0x00000000
+#define DDRSS_PHY_1778_DATA 0x00000000
+#define DDRSS_PHY_1779_DATA 0x00000000
+#define DDRSS_PHY_1780_DATA 0x00000000
+#define DDRSS_PHY_1781_DATA 0x00000000
+#define DDRSS_PHY_1782_DATA 0x00000000
+#define DDRSS_PHY_1783_DATA 0x00000000
+#define DDRSS_PHY_1784_DATA 0x00000000
+#define DDRSS_PHY_1785_DATA 0x00000000
+#define DDRSS_PHY_1786_DATA 0x00000000
+#define DDRSS_PHY_1787_DATA 0x00000000
+#define DDRSS_PHY_1788_DATA 0x00000000
+#define DDRSS_PHY_1789_DATA 0x00000000
+#define DDRSS_PHY_1790_DATA 0x00000000
+#define DDRSS_PHY_1791_DATA 0x00000000
+#define DDRSS_PHY_1792_DATA 0x00000000
+#define DDRSS_PHY_1793_DATA 0x00010100
+#define DDRSS_PHY_1794_DATA 0x00000000
+#define DDRSS_PHY_1795_DATA 0x00000000
+#define DDRSS_PHY_1796_DATA 0x00000000
+#define DDRSS_PHY_1797_DATA 0x00000000
+#define DDRSS_PHY_1798_DATA 0x00050000
+#define DDRSS_PHY_1799_DATA 0x04000000
+#define DDRSS_PHY_1800_DATA 0x00000055
+#define DDRSS_PHY_1801_DATA 0x00000000
+#define DDRSS_PHY_1802_DATA 0x00000000
+#define DDRSS_PHY_1803_DATA 0x00000000
+#define DDRSS_PHY_1804_DATA 0x00000000
+#define DDRSS_PHY_1805_DATA 0x00002001
+#define DDRSS_PHY_1806_DATA 0x00004003
+#define DDRSS_PHY_1807_DATA 0x50020028
+#define DDRSS_PHY_1808_DATA 0x01010000
+#define DDRSS_PHY_1809_DATA 0x80080001
+#define DDRSS_PHY_1810_DATA 0x10200000
+#define DDRSS_PHY_1811_DATA 0x00000008
+#define DDRSS_PHY_1812_DATA 0x00000000
+#define DDRSS_PHY_1813_DATA 0x06000000
+#define DDRSS_PHY_1814_DATA 0x010F0F0E
+#define DDRSS_PHY_1815_DATA 0x00040101
+#define DDRSS_PHY_1816_DATA 0x0000010F
+#define DDRSS_PHY_1817_DATA 0x00000000
+#define DDRSS_PHY_1818_DATA 0x00000064
+#define DDRSS_PHY_1819_DATA 0x00000000
+#define DDRSS_PHY_1820_DATA 0x00000000
+#define DDRSS_PHY_1821_DATA 0x0F0F0F01
+#define DDRSS_PHY_1822_DATA 0x0F0F0F02
+#define DDRSS_PHY_1823_DATA 0x0F0F0F0F
+#define DDRSS_PHY_1824_DATA 0x0F0F0804
+#define DDRSS_PHY_1825_DATA 0x00800120
+#define DDRSS_PHY_1826_DATA 0x00041B42
+#define DDRSS_PHY_1827_DATA 0x00005201
+#define DDRSS_PHY_1828_DATA 0x00000000
+#define DDRSS_PHY_1829_DATA 0x00000000
+#define DDRSS_PHY_1830_DATA 0x00000000
+#define DDRSS_PHY_1831_DATA 0x00000000
+#define DDRSS_PHY_1832_DATA 0x00000000
+#define DDRSS_PHY_1833_DATA 0x00000000
+#define DDRSS_PHY_1834_DATA 0x03010100
+#define DDRSS_PHY_1835_DATA 0x00540007
+#define DDRSS_PHY_1836_DATA 0x000040A2
+#define DDRSS_PHY_1837_DATA 0x00024410
+#define DDRSS_PHY_1838_DATA 0x00004410
+#define DDRSS_PHY_1839_DATA 0x00004410
+#define DDRSS_PHY_1840_DATA 0x00004410
+#define DDRSS_PHY_1841_DATA 0x00004410
+#define DDRSS_PHY_1842_DATA 0x00004410
+#define DDRSS_PHY_1843_DATA 0x00004410
+#define DDRSS_PHY_1844_DATA 0x00004410
+#define DDRSS_PHY_1845_DATA 0x00004410
+#define DDRSS_PHY_1846_DATA 0x00004410
+#define DDRSS_PHY_1847_DATA 0x00000000
+#define DDRSS_PHY_1848_DATA 0x00000076
+#define DDRSS_PHY_1849_DATA 0x00000400
+#define DDRSS_PHY_1850_DATA 0x00000008
+#define DDRSS_PHY_1851_DATA 0x00000000
+#define DDRSS_PHY_1852_DATA 0x00000000
+#define DDRSS_PHY_1853_DATA 0x00000000
+#define DDRSS_PHY_1854_DATA 0x00000000
+#define DDRSS_PHY_1855_DATA 0x00000000
+#define DDRSS_PHY_1856_DATA 0x03000000
+#define DDRSS_PHY_1857_DATA 0x00000000
+#define DDRSS_PHY_1858_DATA 0x00000000
+#define DDRSS_PHY_1859_DATA 0x00000000
+#define DDRSS_PHY_1860_DATA 0x04102006
+#define DDRSS_PHY_1861_DATA 0x00041020
+#define DDRSS_PHY_1862_DATA 0x01C98C98
+#define DDRSS_PHY_1863_DATA 0x3F400000
+#define DDRSS_PHY_1864_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1865_DATA 0x0000001F
+#define DDRSS_PHY_1866_DATA 0x00000000
+#define DDRSS_PHY_1867_DATA 0x00000000
+#define DDRSS_PHY_1868_DATA 0x00000000
+#define DDRSS_PHY_1869_DATA 0x00000001
+#define DDRSS_PHY_1870_DATA 0x00000000
+#define DDRSS_PHY_1871_DATA 0x00000000
+#define DDRSS_PHY_1872_DATA 0x00000000
+#define DDRSS_PHY_1873_DATA 0x00000000
+#define DDRSS_PHY_1874_DATA 0x76543210
+#define DDRSS_PHY_1875_DATA 0x06010198
+#define DDRSS_PHY_1876_DATA 0x00000000
+#define DDRSS_PHY_1877_DATA 0x00000000
+#define DDRSS_PHY_1878_DATA 0x00000000
+#define DDRSS_PHY_1879_DATA 0x00040700
+#define DDRSS_PHY_1880_DATA 0x00000000
+#define DDRSS_PHY_1881_DATA 0x00000000
+#define DDRSS_PHY_1882_DATA 0x00000000
+#define DDRSS_PHY_1883_DATA 0x00000000
+#define DDRSS_PHY_1884_DATA 0x00000000
+#define DDRSS_PHY_1885_DATA 0x00000002
+#define DDRSS_PHY_1886_DATA 0x00000000
+#define DDRSS_PHY_1887_DATA 0x00000000
+#define DDRSS_PHY_1888_DATA 0x00000AC4
+#define DDRSS_PHY_1889_DATA 0x04000004
+#define DDRSS_PHY_1890_DATA 0x00000000
+#define DDRSS_PHY_1891_DATA 0x00001142
+#define DDRSS_PHY_1892_DATA 0x01020000
+#define DDRSS_PHY_1893_DATA 0x00000080
+#define DDRSS_PHY_1894_DATA 0x03900390
+#define DDRSS_PHY_1895_DATA 0x03900390
+#define DDRSS_PHY_1896_DATA 0x03900390
+#define DDRSS_PHY_1897_DATA 0x03900390
+#define DDRSS_PHY_1898_DATA 0x03000300
+#define DDRSS_PHY_1899_DATA 0x03000300
+#define DDRSS_PHY_1900_DATA 0x00000300
+#define DDRSS_PHY_1901_DATA 0x00000300
+#define DDRSS_PHY_1902_DATA 0x00000300
+#define DDRSS_PHY_1903_DATA 0x00000300
+#define DDRSS_PHY_1904_DATA 0x00000005
+#define DDRSS_PHY_1905_DATA 0x3183BF77
+#define DDRSS_PHY_1906_DATA 0x00000000
+#define DDRSS_PHY_1907_DATA 0x0C000DFF
+#define DDRSS_PHY_1908_DATA 0x30000DFF
+#define DDRSS_PHY_1909_DATA 0x3F0DFF11
+#define DDRSS_PHY_1910_DATA 0x00EF0000
+#define DDRSS_PHY_1911_DATA 0x780DFFCC
+#define DDRSS_PHY_1912_DATA 0x00000C11
+#define DDRSS_PHY_1913_DATA 0x00018011
+#define DDRSS_PHY_1914_DATA 0x0089FF00
+#define DDRSS_PHY_1915_DATA 0x000C3F11
+#define DDRSS_PHY_1916_DATA 0x01990000
+#define DDRSS_PHY_1917_DATA 0x000C3F11
+#define DDRSS_PHY_1918_DATA 0x01990000
+#define DDRSS_PHY_1919_DATA 0x3F0DFF11
+#define DDRSS_PHY_1920_DATA 0x00EF0000
+#define DDRSS_PHY_1921_DATA 0x00018011
+#define DDRSS_PHY_1922_DATA 0x0089FF00
+#define DDRSS_PHY_1923_DATA 0x20040004

+ 2814 - 0
arch/arm/dts/k3-am62a-ddr.dtsi

@@ -0,0 +1,2814 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+	memorycontroller: memory-controller@f308000 {
+		compatible = "ti,am62a-ddrss";
+		reg = <0x00 0x0f308000 0x00 0x4000>,
+		      <0x00 0x43014000 0x00 0x100>;
+		reg-names = "cfg", "ctrl_mmr_lp4";
+		ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+		ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+		ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+
+		power-domains = <&k3_pds 170 TI_SCI_PD_SHARED>,
+			<&k3_pds 55 TI_SCI_PD_SHARED>;
+		clocks = <&k3_clks 170 1>, <&k3_clks 16 4>;
+
+		u-boot,dm-spl;
+
+		ti,ctl-data = <
+			DDRSS_CTL_0_DATA
+			DDRSS_CTL_1_DATA
+			DDRSS_CTL_2_DATA
+			DDRSS_CTL_3_DATA
+			DDRSS_CTL_4_DATA
+			DDRSS_CTL_5_DATA
+			DDRSS_CTL_6_DATA
+			DDRSS_CTL_7_DATA
+			DDRSS_CTL_8_DATA
+			DDRSS_CTL_9_DATA
+			DDRSS_CTL_10_DATA
+			DDRSS_CTL_11_DATA
+			DDRSS_CTL_12_DATA
+			DDRSS_CTL_13_DATA
+			DDRSS_CTL_14_DATA
+			DDRSS_CTL_15_DATA
+			DDRSS_CTL_16_DATA
+			DDRSS_CTL_17_DATA
+			DDRSS_CTL_18_DATA
+			DDRSS_CTL_19_DATA
+			DDRSS_CTL_20_DATA
+			DDRSS_CTL_21_DATA
+			DDRSS_CTL_22_DATA
+			DDRSS_CTL_23_DATA
+			DDRSS_CTL_24_DATA
+			DDRSS_CTL_25_DATA
+			DDRSS_CTL_26_DATA
+			DDRSS_CTL_27_DATA
+			DDRSS_CTL_28_DATA
+			DDRSS_CTL_29_DATA
+			DDRSS_CTL_30_DATA
+			DDRSS_CTL_31_DATA
+			DDRSS_CTL_32_DATA
+			DDRSS_CTL_33_DATA
+			DDRSS_CTL_34_DATA
+			DDRSS_CTL_35_DATA
+			DDRSS_CTL_36_DATA
+			DDRSS_CTL_37_DATA
+			DDRSS_CTL_38_DATA
+			DDRSS_CTL_39_DATA
+			DDRSS_CTL_40_DATA
+			DDRSS_CTL_41_DATA
+			DDRSS_CTL_42_DATA
+			DDRSS_CTL_43_DATA
+			DDRSS_CTL_44_DATA
+			DDRSS_CTL_45_DATA
+			DDRSS_CTL_46_DATA
+			DDRSS_CTL_47_DATA
+			DDRSS_CTL_48_DATA
+			DDRSS_CTL_49_DATA
+			DDRSS_CTL_50_DATA
+			DDRSS_CTL_51_DATA
+			DDRSS_CTL_52_DATA
+			DDRSS_CTL_53_DATA
+			DDRSS_CTL_54_DATA
+			DDRSS_CTL_55_DATA
+			DDRSS_CTL_56_DATA
+			DDRSS_CTL_57_DATA
+			DDRSS_CTL_58_DATA
+			DDRSS_CTL_59_DATA
+			DDRSS_CTL_60_DATA
+			DDRSS_CTL_61_DATA
+			DDRSS_CTL_62_DATA
+			DDRSS_CTL_63_DATA
+			DDRSS_CTL_64_DATA
+			DDRSS_CTL_65_DATA
+			DDRSS_CTL_66_DATA
+			DDRSS_CTL_67_DATA
+			DDRSS_CTL_68_DATA
+			DDRSS_CTL_69_DATA
+			DDRSS_CTL_70_DATA
+			DDRSS_CTL_71_DATA
+			DDRSS_CTL_72_DATA
+			DDRSS_CTL_73_DATA
+			DDRSS_CTL_74_DATA
+			DDRSS_CTL_75_DATA
+			DDRSS_CTL_76_DATA
+			DDRSS_CTL_77_DATA
+			DDRSS_CTL_78_DATA
+			DDRSS_CTL_79_DATA
+			DDRSS_CTL_80_DATA
+			DDRSS_CTL_81_DATA
+			DDRSS_CTL_82_DATA
+			DDRSS_CTL_83_DATA
+			DDRSS_CTL_84_DATA
+			DDRSS_CTL_85_DATA
+			DDRSS_CTL_86_DATA
+			DDRSS_CTL_87_DATA
+			DDRSS_CTL_88_DATA
+			DDRSS_CTL_89_DATA
+			DDRSS_CTL_90_DATA
+			DDRSS_CTL_91_DATA
+			DDRSS_CTL_92_DATA
+			DDRSS_CTL_93_DATA
+			DDRSS_CTL_94_DATA
+			DDRSS_CTL_95_DATA
+			DDRSS_CTL_96_DATA
+			DDRSS_CTL_97_DATA
+			DDRSS_CTL_98_DATA
+			DDRSS_CTL_99_DATA
+			DDRSS_CTL_100_DATA
+			DDRSS_CTL_101_DATA
+			DDRSS_CTL_102_DATA
+			DDRSS_CTL_103_DATA
+			DDRSS_CTL_104_DATA
+			DDRSS_CTL_105_DATA
+			DDRSS_CTL_106_DATA
+			DDRSS_CTL_107_DATA
+			DDRSS_CTL_108_DATA
+			DDRSS_CTL_109_DATA
+			DDRSS_CTL_110_DATA
+			DDRSS_CTL_111_DATA
+			DDRSS_CTL_112_DATA
+			DDRSS_CTL_113_DATA
+			DDRSS_CTL_114_DATA
+			DDRSS_CTL_115_DATA
+			DDRSS_CTL_116_DATA
+			DDRSS_CTL_117_DATA
+			DDRSS_CTL_118_DATA
+			DDRSS_CTL_119_DATA
+			DDRSS_CTL_120_DATA
+			DDRSS_CTL_121_DATA
+			DDRSS_CTL_122_DATA
+			DDRSS_CTL_123_DATA
+			DDRSS_CTL_124_DATA
+			DDRSS_CTL_125_DATA
+			DDRSS_CTL_126_DATA
+			DDRSS_CTL_127_DATA
+			DDRSS_CTL_128_DATA
+			DDRSS_CTL_129_DATA
+			DDRSS_CTL_130_DATA
+			DDRSS_CTL_131_DATA
+			DDRSS_CTL_132_DATA
+			DDRSS_CTL_133_DATA
+			DDRSS_CTL_134_DATA
+			DDRSS_CTL_135_DATA
+			DDRSS_CTL_136_DATA
+			DDRSS_CTL_137_DATA
+			DDRSS_CTL_138_DATA
+			DDRSS_CTL_139_DATA
+			DDRSS_CTL_140_DATA
+			DDRSS_CTL_141_DATA
+			DDRSS_CTL_142_DATA
+			DDRSS_CTL_143_DATA
+			DDRSS_CTL_144_DATA
+			DDRSS_CTL_145_DATA
+			DDRSS_CTL_146_DATA
+			DDRSS_CTL_147_DATA
+			DDRSS_CTL_148_DATA
+			DDRSS_CTL_149_DATA
+			DDRSS_CTL_150_DATA
+			DDRSS_CTL_151_DATA
+			DDRSS_CTL_152_DATA
+			DDRSS_CTL_153_DATA
+			DDRSS_CTL_154_DATA
+			DDRSS_CTL_155_DATA
+			DDRSS_CTL_156_DATA
+			DDRSS_CTL_157_DATA
+			DDRSS_CTL_158_DATA
+			DDRSS_CTL_159_DATA
+			DDRSS_CTL_160_DATA
+			DDRSS_CTL_161_DATA
+			DDRSS_CTL_162_DATA
+			DDRSS_CTL_163_DATA
+			DDRSS_CTL_164_DATA
+			DDRSS_CTL_165_DATA
+			DDRSS_CTL_166_DATA
+			DDRSS_CTL_167_DATA
+			DDRSS_CTL_168_DATA
+			DDRSS_CTL_169_DATA
+			DDRSS_CTL_170_DATA
+			DDRSS_CTL_171_DATA
+			DDRSS_CTL_172_DATA
+			DDRSS_CTL_173_DATA
+			DDRSS_CTL_174_DATA
+			DDRSS_CTL_175_DATA
+			DDRSS_CTL_176_DATA
+			DDRSS_CTL_177_DATA
+			DDRSS_CTL_178_DATA
+			DDRSS_CTL_179_DATA
+			DDRSS_CTL_180_DATA
+			DDRSS_CTL_181_DATA
+			DDRSS_CTL_182_DATA
+			DDRSS_CTL_183_DATA
+			DDRSS_CTL_184_DATA
+			DDRSS_CTL_185_DATA
+			DDRSS_CTL_186_DATA
+			DDRSS_CTL_187_DATA
+			DDRSS_CTL_188_DATA
+			DDRSS_CTL_189_DATA
+			DDRSS_CTL_190_DATA
+			DDRSS_CTL_191_DATA
+			DDRSS_CTL_192_DATA
+			DDRSS_CTL_193_DATA
+			DDRSS_CTL_194_DATA
+			DDRSS_CTL_195_DATA
+			DDRSS_CTL_196_DATA
+			DDRSS_CTL_197_DATA
+			DDRSS_CTL_198_DATA
+			DDRSS_CTL_199_DATA
+			DDRSS_CTL_200_DATA
+			DDRSS_CTL_201_DATA
+			DDRSS_CTL_202_DATA
+			DDRSS_CTL_203_DATA
+			DDRSS_CTL_204_DATA
+			DDRSS_CTL_205_DATA
+			DDRSS_CTL_206_DATA
+			DDRSS_CTL_207_DATA
+			DDRSS_CTL_208_DATA
+			DDRSS_CTL_209_DATA
+			DDRSS_CTL_210_DATA
+			DDRSS_CTL_211_DATA
+			DDRSS_CTL_212_DATA
+			DDRSS_CTL_213_DATA
+			DDRSS_CTL_214_DATA
+			DDRSS_CTL_215_DATA
+			DDRSS_CTL_216_DATA
+			DDRSS_CTL_217_DATA
+			DDRSS_CTL_218_DATA
+			DDRSS_CTL_219_DATA
+			DDRSS_CTL_220_DATA
+			DDRSS_CTL_221_DATA
+			DDRSS_CTL_222_DATA
+			DDRSS_CTL_223_DATA
+			DDRSS_CTL_224_DATA
+			DDRSS_CTL_225_DATA
+			DDRSS_CTL_226_DATA
+			DDRSS_CTL_227_DATA
+			DDRSS_CTL_228_DATA
+			DDRSS_CTL_229_DATA
+			DDRSS_CTL_230_DATA
+			DDRSS_CTL_231_DATA
+			DDRSS_CTL_232_DATA
+			DDRSS_CTL_233_DATA
+			DDRSS_CTL_234_DATA
+			DDRSS_CTL_235_DATA
+			DDRSS_CTL_236_DATA
+			DDRSS_CTL_237_DATA
+			DDRSS_CTL_238_DATA
+			DDRSS_CTL_239_DATA
+			DDRSS_CTL_240_DATA
+			DDRSS_CTL_241_DATA
+			DDRSS_CTL_242_DATA
+			DDRSS_CTL_243_DATA
+			DDRSS_CTL_244_DATA
+			DDRSS_CTL_245_DATA
+			DDRSS_CTL_246_DATA
+			DDRSS_CTL_247_DATA
+			DDRSS_CTL_248_DATA
+			DDRSS_CTL_249_DATA
+			DDRSS_CTL_250_DATA
+			DDRSS_CTL_251_DATA
+			DDRSS_CTL_252_DATA
+			DDRSS_CTL_253_DATA
+			DDRSS_CTL_254_DATA
+			DDRSS_CTL_255_DATA
+			DDRSS_CTL_256_DATA
+			DDRSS_CTL_257_DATA
+			DDRSS_CTL_258_DATA
+			DDRSS_CTL_259_DATA
+			DDRSS_CTL_260_DATA
+			DDRSS_CTL_261_DATA
+			DDRSS_CTL_262_DATA
+			DDRSS_CTL_263_DATA
+			DDRSS_CTL_264_DATA
+			DDRSS_CTL_265_DATA
+			DDRSS_CTL_266_DATA
+			DDRSS_CTL_267_DATA
+			DDRSS_CTL_268_DATA
+			DDRSS_CTL_269_DATA
+			DDRSS_CTL_270_DATA
+			DDRSS_CTL_271_DATA
+			DDRSS_CTL_272_DATA
+			DDRSS_CTL_273_DATA
+			DDRSS_CTL_274_DATA
+			DDRSS_CTL_275_DATA
+			DDRSS_CTL_276_DATA
+			DDRSS_CTL_277_DATA
+			DDRSS_CTL_278_DATA
+			DDRSS_CTL_279_DATA
+			DDRSS_CTL_280_DATA
+			DDRSS_CTL_281_DATA
+			DDRSS_CTL_282_DATA
+			DDRSS_CTL_283_DATA
+			DDRSS_CTL_284_DATA
+			DDRSS_CTL_285_DATA
+			DDRSS_CTL_286_DATA
+			DDRSS_CTL_287_DATA
+			DDRSS_CTL_288_DATA
+			DDRSS_CTL_289_DATA
+			DDRSS_CTL_290_DATA
+			DDRSS_CTL_291_DATA
+			DDRSS_CTL_292_DATA
+			DDRSS_CTL_293_DATA
+			DDRSS_CTL_294_DATA
+			DDRSS_CTL_295_DATA
+			DDRSS_CTL_296_DATA
+			DDRSS_CTL_297_DATA
+			DDRSS_CTL_298_DATA
+			DDRSS_CTL_299_DATA
+			DDRSS_CTL_300_DATA
+			DDRSS_CTL_301_DATA
+			DDRSS_CTL_302_DATA
+			DDRSS_CTL_303_DATA
+			DDRSS_CTL_304_DATA
+			DDRSS_CTL_305_DATA
+			DDRSS_CTL_306_DATA
+			DDRSS_CTL_307_DATA
+			DDRSS_CTL_308_DATA
+			DDRSS_CTL_309_DATA
+			DDRSS_CTL_310_DATA
+			DDRSS_CTL_311_DATA
+			DDRSS_CTL_312_DATA
+			DDRSS_CTL_313_DATA
+			DDRSS_CTL_314_DATA
+			DDRSS_CTL_315_DATA
+			DDRSS_CTL_316_DATA
+			DDRSS_CTL_317_DATA
+			DDRSS_CTL_318_DATA
+			DDRSS_CTL_319_DATA
+			DDRSS_CTL_320_DATA
+			DDRSS_CTL_321_DATA
+			DDRSS_CTL_322_DATA
+			DDRSS_CTL_323_DATA
+			DDRSS_CTL_324_DATA
+			DDRSS_CTL_325_DATA
+			DDRSS_CTL_326_DATA
+			DDRSS_CTL_327_DATA
+			DDRSS_CTL_328_DATA
+			DDRSS_CTL_329_DATA
+			DDRSS_CTL_330_DATA
+			DDRSS_CTL_331_DATA
+			DDRSS_CTL_332_DATA
+			DDRSS_CTL_333_DATA
+			DDRSS_CTL_334_DATA
+			DDRSS_CTL_335_DATA
+			DDRSS_CTL_336_DATA
+			DDRSS_CTL_337_DATA
+			DDRSS_CTL_338_DATA
+			DDRSS_CTL_339_DATA
+			DDRSS_CTL_340_DATA
+			DDRSS_CTL_341_DATA
+			DDRSS_CTL_342_DATA
+			DDRSS_CTL_343_DATA
+			DDRSS_CTL_344_DATA
+			DDRSS_CTL_345_DATA
+			DDRSS_CTL_346_DATA
+			DDRSS_CTL_347_DATA
+			DDRSS_CTL_348_DATA
+			DDRSS_CTL_349_DATA
+			DDRSS_CTL_350_DATA
+			DDRSS_CTL_351_DATA
+			DDRSS_CTL_352_DATA
+			DDRSS_CTL_353_DATA
+			DDRSS_CTL_354_DATA
+			DDRSS_CTL_355_DATA
+			DDRSS_CTL_356_DATA
+			DDRSS_CTL_357_DATA
+			DDRSS_CTL_358_DATA
+			DDRSS_CTL_359_DATA
+			DDRSS_CTL_360_DATA
+			DDRSS_CTL_361_DATA
+			DDRSS_CTL_362_DATA
+			DDRSS_CTL_363_DATA
+			DDRSS_CTL_364_DATA
+			DDRSS_CTL_365_DATA
+			DDRSS_CTL_366_DATA
+			DDRSS_CTL_367_DATA
+			DDRSS_CTL_368_DATA
+			DDRSS_CTL_369_DATA
+			DDRSS_CTL_370_DATA
+			DDRSS_CTL_371_DATA
+			DDRSS_CTL_372_DATA
+			DDRSS_CTL_373_DATA
+			DDRSS_CTL_374_DATA
+			DDRSS_CTL_375_DATA
+			DDRSS_CTL_376_DATA
+			DDRSS_CTL_377_DATA
+			DDRSS_CTL_378_DATA
+			DDRSS_CTL_379_DATA
+			DDRSS_CTL_380_DATA
+			DDRSS_CTL_381_DATA
+			DDRSS_CTL_382_DATA
+			DDRSS_CTL_383_DATA
+			DDRSS_CTL_384_DATA
+			DDRSS_CTL_385_DATA
+			DDRSS_CTL_386_DATA
+			DDRSS_CTL_387_DATA
+			DDRSS_CTL_388_DATA
+			DDRSS_CTL_389_DATA
+			DDRSS_CTL_390_DATA
+			DDRSS_CTL_391_DATA
+			DDRSS_CTL_392_DATA
+			DDRSS_CTL_393_DATA
+			DDRSS_CTL_394_DATA
+			DDRSS_CTL_395_DATA
+			DDRSS_CTL_396_DATA
+			DDRSS_CTL_397_DATA
+			DDRSS_CTL_398_DATA
+			DDRSS_CTL_399_DATA
+			DDRSS_CTL_400_DATA
+			DDRSS_CTL_401_DATA
+			DDRSS_CTL_402_DATA
+			DDRSS_CTL_403_DATA
+			DDRSS_CTL_404_DATA
+			DDRSS_CTL_405_DATA
+			DDRSS_CTL_406_DATA
+			DDRSS_CTL_407_DATA
+			DDRSS_CTL_408_DATA
+			DDRSS_CTL_409_DATA
+			DDRSS_CTL_410_DATA
+			DDRSS_CTL_411_DATA
+			DDRSS_CTL_412_DATA
+			DDRSS_CTL_413_DATA
+			DDRSS_CTL_414_DATA
+			DDRSS_CTL_415_DATA
+			DDRSS_CTL_416_DATA
+			DDRSS_CTL_417_DATA
+			DDRSS_CTL_418_DATA
+			DDRSS_CTL_419_DATA
+			DDRSS_CTL_420_DATA
+			DDRSS_CTL_421_DATA
+			DDRSS_CTL_422_DATA
+			DDRSS_CTL_423_DATA
+			DDRSS_CTL_424_DATA
+			DDRSS_CTL_425_DATA
+			DDRSS_CTL_426_DATA
+			DDRSS_CTL_427_DATA
+			DDRSS_CTL_428_DATA
+			DDRSS_CTL_429_DATA
+			DDRSS_CTL_430_DATA
+			DDRSS_CTL_431_DATA
+			DDRSS_CTL_432_DATA
+			DDRSS_CTL_433_DATA
+			DDRSS_CTL_434_DATA
+		>;
+
+		ti,pi-data = <
+			DDRSS_PI_0_DATA
+			DDRSS_PI_1_DATA
+			DDRSS_PI_2_DATA
+			DDRSS_PI_3_DATA
+			DDRSS_PI_4_DATA
+			DDRSS_PI_5_DATA
+			DDRSS_PI_6_DATA
+			DDRSS_PI_7_DATA
+			DDRSS_PI_8_DATA
+			DDRSS_PI_9_DATA
+			DDRSS_PI_10_DATA
+			DDRSS_PI_11_DATA
+			DDRSS_PI_12_DATA
+			DDRSS_PI_13_DATA
+			DDRSS_PI_14_DATA
+			DDRSS_PI_15_DATA
+			DDRSS_PI_16_DATA
+			DDRSS_PI_17_DATA
+			DDRSS_PI_18_DATA
+			DDRSS_PI_19_DATA
+			DDRSS_PI_20_DATA
+			DDRSS_PI_21_DATA
+			DDRSS_PI_22_DATA
+			DDRSS_PI_23_DATA
+			DDRSS_PI_24_DATA
+			DDRSS_PI_25_DATA
+			DDRSS_PI_26_DATA
+			DDRSS_PI_27_DATA
+			DDRSS_PI_28_DATA
+			DDRSS_PI_29_DATA
+			DDRSS_PI_30_DATA
+			DDRSS_PI_31_DATA
+			DDRSS_PI_32_DATA
+			DDRSS_PI_33_DATA
+			DDRSS_PI_34_DATA
+			DDRSS_PI_35_DATA
+			DDRSS_PI_36_DATA
+			DDRSS_PI_37_DATA
+			DDRSS_PI_38_DATA
+			DDRSS_PI_39_DATA
+			DDRSS_PI_40_DATA
+			DDRSS_PI_41_DATA
+			DDRSS_PI_42_DATA
+			DDRSS_PI_43_DATA
+			DDRSS_PI_44_DATA
+			DDRSS_PI_45_DATA
+			DDRSS_PI_46_DATA
+			DDRSS_PI_47_DATA
+			DDRSS_PI_48_DATA
+			DDRSS_PI_49_DATA
+			DDRSS_PI_50_DATA
+			DDRSS_PI_51_DATA
+			DDRSS_PI_52_DATA
+			DDRSS_PI_53_DATA
+			DDRSS_PI_54_DATA
+			DDRSS_PI_55_DATA
+			DDRSS_PI_56_DATA
+			DDRSS_PI_57_DATA
+			DDRSS_PI_58_DATA
+			DDRSS_PI_59_DATA
+			DDRSS_PI_60_DATA
+			DDRSS_PI_61_DATA
+			DDRSS_PI_62_DATA
+			DDRSS_PI_63_DATA
+			DDRSS_PI_64_DATA
+			DDRSS_PI_65_DATA
+			DDRSS_PI_66_DATA
+			DDRSS_PI_67_DATA
+			DDRSS_PI_68_DATA
+			DDRSS_PI_69_DATA
+			DDRSS_PI_70_DATA
+			DDRSS_PI_71_DATA
+			DDRSS_PI_72_DATA
+			DDRSS_PI_73_DATA
+			DDRSS_PI_74_DATA
+			DDRSS_PI_75_DATA
+			DDRSS_PI_76_DATA
+			DDRSS_PI_77_DATA
+			DDRSS_PI_78_DATA
+			DDRSS_PI_79_DATA
+			DDRSS_PI_80_DATA
+			DDRSS_PI_81_DATA
+			DDRSS_PI_82_DATA
+			DDRSS_PI_83_DATA
+			DDRSS_PI_84_DATA
+			DDRSS_PI_85_DATA
+			DDRSS_PI_86_DATA
+			DDRSS_PI_87_DATA
+			DDRSS_PI_88_DATA
+			DDRSS_PI_89_DATA
+			DDRSS_PI_90_DATA
+			DDRSS_PI_91_DATA
+			DDRSS_PI_92_DATA
+			DDRSS_PI_93_DATA
+			DDRSS_PI_94_DATA
+			DDRSS_PI_95_DATA
+			DDRSS_PI_96_DATA
+			DDRSS_PI_97_DATA
+			DDRSS_PI_98_DATA
+			DDRSS_PI_99_DATA
+			DDRSS_PI_100_DATA
+			DDRSS_PI_101_DATA
+			DDRSS_PI_102_DATA
+			DDRSS_PI_103_DATA
+			DDRSS_PI_104_DATA
+			DDRSS_PI_105_DATA
+			DDRSS_PI_106_DATA
+			DDRSS_PI_107_DATA
+			DDRSS_PI_108_DATA
+			DDRSS_PI_109_DATA
+			DDRSS_PI_110_DATA
+			DDRSS_PI_111_DATA
+			DDRSS_PI_112_DATA
+			DDRSS_PI_113_DATA
+			DDRSS_PI_114_DATA
+			DDRSS_PI_115_DATA
+			DDRSS_PI_116_DATA
+			DDRSS_PI_117_DATA
+			DDRSS_PI_118_DATA
+			DDRSS_PI_119_DATA
+			DDRSS_PI_120_DATA
+			DDRSS_PI_121_DATA
+			DDRSS_PI_122_DATA
+			DDRSS_PI_123_DATA
+			DDRSS_PI_124_DATA
+			DDRSS_PI_125_DATA
+			DDRSS_PI_126_DATA
+			DDRSS_PI_127_DATA
+			DDRSS_PI_128_DATA
+			DDRSS_PI_129_DATA
+			DDRSS_PI_130_DATA
+			DDRSS_PI_131_DATA
+			DDRSS_PI_132_DATA
+			DDRSS_PI_133_DATA
+			DDRSS_PI_134_DATA
+			DDRSS_PI_135_DATA
+			DDRSS_PI_136_DATA
+			DDRSS_PI_137_DATA
+			DDRSS_PI_138_DATA
+			DDRSS_PI_139_DATA
+			DDRSS_PI_140_DATA
+			DDRSS_PI_141_DATA
+			DDRSS_PI_142_DATA
+			DDRSS_PI_143_DATA
+			DDRSS_PI_144_DATA
+			DDRSS_PI_145_DATA
+			DDRSS_PI_146_DATA
+			DDRSS_PI_147_DATA
+			DDRSS_PI_148_DATA
+			DDRSS_PI_149_DATA
+			DDRSS_PI_150_DATA
+			DDRSS_PI_151_DATA
+			DDRSS_PI_152_DATA
+			DDRSS_PI_153_DATA
+			DDRSS_PI_154_DATA
+			DDRSS_PI_155_DATA
+			DDRSS_PI_156_DATA
+			DDRSS_PI_157_DATA
+			DDRSS_PI_158_DATA
+			DDRSS_PI_159_DATA
+			DDRSS_PI_160_DATA
+			DDRSS_PI_161_DATA
+			DDRSS_PI_162_DATA
+			DDRSS_PI_163_DATA
+			DDRSS_PI_164_DATA
+			DDRSS_PI_165_DATA
+			DDRSS_PI_166_DATA
+			DDRSS_PI_167_DATA
+			DDRSS_PI_168_DATA
+			DDRSS_PI_169_DATA
+			DDRSS_PI_170_DATA
+			DDRSS_PI_171_DATA
+			DDRSS_PI_172_DATA
+			DDRSS_PI_173_DATA
+			DDRSS_PI_174_DATA
+			DDRSS_PI_175_DATA
+			DDRSS_PI_176_DATA
+			DDRSS_PI_177_DATA
+			DDRSS_PI_178_DATA
+			DDRSS_PI_179_DATA
+			DDRSS_PI_180_DATA
+			DDRSS_PI_181_DATA
+			DDRSS_PI_182_DATA
+			DDRSS_PI_183_DATA
+			DDRSS_PI_184_DATA
+			DDRSS_PI_185_DATA
+			DDRSS_PI_186_DATA
+			DDRSS_PI_187_DATA
+			DDRSS_PI_188_DATA
+			DDRSS_PI_189_DATA
+			DDRSS_PI_190_DATA
+			DDRSS_PI_191_DATA
+			DDRSS_PI_192_DATA
+			DDRSS_PI_193_DATA
+			DDRSS_PI_194_DATA
+			DDRSS_PI_195_DATA
+			DDRSS_PI_196_DATA
+			DDRSS_PI_197_DATA
+			DDRSS_PI_198_DATA
+			DDRSS_PI_199_DATA
+			DDRSS_PI_200_DATA
+			DDRSS_PI_201_DATA
+			DDRSS_PI_202_DATA
+			DDRSS_PI_203_DATA
+			DDRSS_PI_204_DATA
+			DDRSS_PI_205_DATA
+			DDRSS_PI_206_DATA
+			DDRSS_PI_207_DATA
+			DDRSS_PI_208_DATA
+			DDRSS_PI_209_DATA
+			DDRSS_PI_210_DATA
+			DDRSS_PI_211_DATA
+			DDRSS_PI_212_DATA
+			DDRSS_PI_213_DATA
+			DDRSS_PI_214_DATA
+			DDRSS_PI_215_DATA
+			DDRSS_PI_216_DATA
+			DDRSS_PI_217_DATA
+			DDRSS_PI_218_DATA
+			DDRSS_PI_219_DATA
+			DDRSS_PI_220_DATA
+			DDRSS_PI_221_DATA
+			DDRSS_PI_222_DATA
+			DDRSS_PI_223_DATA
+			DDRSS_PI_224_DATA
+			DDRSS_PI_225_DATA
+			DDRSS_PI_226_DATA
+			DDRSS_PI_227_DATA
+			DDRSS_PI_228_DATA
+			DDRSS_PI_229_DATA
+			DDRSS_PI_230_DATA
+			DDRSS_PI_231_DATA
+			DDRSS_PI_232_DATA
+			DDRSS_PI_233_DATA
+			DDRSS_PI_234_DATA
+			DDRSS_PI_235_DATA
+			DDRSS_PI_236_DATA
+			DDRSS_PI_237_DATA
+			DDRSS_PI_238_DATA
+			DDRSS_PI_239_DATA
+			DDRSS_PI_240_DATA
+			DDRSS_PI_241_DATA
+			DDRSS_PI_242_DATA
+			DDRSS_PI_243_DATA
+			DDRSS_PI_244_DATA
+			DDRSS_PI_245_DATA
+			DDRSS_PI_246_DATA
+			DDRSS_PI_247_DATA
+			DDRSS_PI_248_DATA
+			DDRSS_PI_249_DATA
+			DDRSS_PI_250_DATA
+			DDRSS_PI_251_DATA
+			DDRSS_PI_252_DATA
+			DDRSS_PI_253_DATA
+			DDRSS_PI_254_DATA
+			DDRSS_PI_255_DATA
+			DDRSS_PI_256_DATA
+			DDRSS_PI_257_DATA
+			DDRSS_PI_258_DATA
+			DDRSS_PI_259_DATA
+			DDRSS_PI_260_DATA
+			DDRSS_PI_261_DATA
+			DDRSS_PI_262_DATA
+			DDRSS_PI_263_DATA
+			DDRSS_PI_264_DATA
+			DDRSS_PI_265_DATA
+			DDRSS_PI_266_DATA
+			DDRSS_PI_267_DATA
+			DDRSS_PI_268_DATA
+			DDRSS_PI_269_DATA
+			DDRSS_PI_270_DATA
+			DDRSS_PI_271_DATA
+			DDRSS_PI_272_DATA
+			DDRSS_PI_273_DATA
+			DDRSS_PI_274_DATA
+			DDRSS_PI_275_DATA
+			DDRSS_PI_276_DATA
+			DDRSS_PI_277_DATA
+			DDRSS_PI_278_DATA
+			DDRSS_PI_279_DATA
+			DDRSS_PI_280_DATA
+			DDRSS_PI_281_DATA
+			DDRSS_PI_282_DATA
+			DDRSS_PI_283_DATA
+			DDRSS_PI_284_DATA
+			DDRSS_PI_285_DATA
+			DDRSS_PI_286_DATA
+			DDRSS_PI_287_DATA
+			DDRSS_PI_288_DATA
+			DDRSS_PI_289_DATA
+			DDRSS_PI_290_DATA
+			DDRSS_PI_291_DATA
+			DDRSS_PI_292_DATA
+			DDRSS_PI_293_DATA
+			DDRSS_PI_294_DATA
+			DDRSS_PI_295_DATA
+			DDRSS_PI_296_DATA
+			DDRSS_PI_297_DATA
+			DDRSS_PI_298_DATA
+			DDRSS_PI_299_DATA
+			DDRSS_PI_300_DATA
+			DDRSS_PI_301_DATA
+			DDRSS_PI_302_DATA
+			DDRSS_PI_303_DATA
+			DDRSS_PI_304_DATA
+			DDRSS_PI_305_DATA
+			DDRSS_PI_306_DATA
+			DDRSS_PI_307_DATA
+			DDRSS_PI_308_DATA
+			DDRSS_PI_309_DATA
+			DDRSS_PI_310_DATA
+			DDRSS_PI_311_DATA
+			DDRSS_PI_312_DATA
+			DDRSS_PI_313_DATA
+			DDRSS_PI_314_DATA
+			DDRSS_PI_315_DATA
+			DDRSS_PI_316_DATA
+			DDRSS_PI_317_DATA
+			DDRSS_PI_318_DATA
+			DDRSS_PI_319_DATA
+			DDRSS_PI_320_DATA
+			DDRSS_PI_321_DATA
+			DDRSS_PI_322_DATA
+			DDRSS_PI_323_DATA
+			DDRSS_PI_324_DATA
+			DDRSS_PI_325_DATA
+			DDRSS_PI_326_DATA
+			DDRSS_PI_327_DATA
+			DDRSS_PI_328_DATA
+			DDRSS_PI_329_DATA
+			DDRSS_PI_330_DATA
+			DDRSS_PI_331_DATA
+			DDRSS_PI_332_DATA
+			DDRSS_PI_333_DATA
+			DDRSS_PI_334_DATA
+			DDRSS_PI_335_DATA
+			DDRSS_PI_336_DATA
+			DDRSS_PI_337_DATA
+			DDRSS_PI_338_DATA
+			DDRSS_PI_339_DATA
+			DDRSS_PI_340_DATA
+			DDRSS_PI_341_DATA
+			DDRSS_PI_342_DATA
+			DDRSS_PI_343_DATA
+			DDRSS_PI_344_DATA
+			DDRSS_PI_345_DATA
+			DDRSS_PI_346_DATA
+			DDRSS_PI_347_DATA
+			DDRSS_PI_348_DATA
+			DDRSS_PI_349_DATA
+			DDRSS_PI_350_DATA
+			DDRSS_PI_351_DATA
+			DDRSS_PI_352_DATA
+			DDRSS_PI_353_DATA
+			DDRSS_PI_354_DATA
+			DDRSS_PI_355_DATA
+			DDRSS_PI_356_DATA
+			DDRSS_PI_357_DATA
+			DDRSS_PI_358_DATA
+			DDRSS_PI_359_DATA
+			DDRSS_PI_360_DATA
+			DDRSS_PI_361_DATA
+			DDRSS_PI_362_DATA
+			DDRSS_PI_363_DATA
+			DDRSS_PI_364_DATA
+			DDRSS_PI_365_DATA
+			DDRSS_PI_366_DATA
+			DDRSS_PI_367_DATA
+			DDRSS_PI_368_DATA
+			DDRSS_PI_369_DATA
+			DDRSS_PI_370_DATA
+			DDRSS_PI_371_DATA
+			DDRSS_PI_372_DATA
+			DDRSS_PI_373_DATA
+			DDRSS_PI_374_DATA
+			DDRSS_PI_375_DATA
+			DDRSS_PI_376_DATA
+			DDRSS_PI_377_DATA
+			DDRSS_PI_378_DATA
+			DDRSS_PI_379_DATA
+			DDRSS_PI_380_DATA
+			DDRSS_PI_381_DATA
+			DDRSS_PI_382_DATA
+			DDRSS_PI_383_DATA
+			DDRSS_PI_384_DATA
+			DDRSS_PI_385_DATA
+			DDRSS_PI_386_DATA
+			DDRSS_PI_387_DATA
+			DDRSS_PI_388_DATA
+			DDRSS_PI_389_DATA
+			DDRSS_PI_390_DATA
+			DDRSS_PI_391_DATA
+			DDRSS_PI_392_DATA
+			DDRSS_PI_393_DATA
+			DDRSS_PI_394_DATA
+			DDRSS_PI_395_DATA
+			DDRSS_PI_396_DATA
+			DDRSS_PI_397_DATA
+			DDRSS_PI_398_DATA
+			DDRSS_PI_399_DATA
+			DDRSS_PI_400_DATA
+			DDRSS_PI_401_DATA
+			DDRSS_PI_402_DATA
+			DDRSS_PI_403_DATA
+			DDRSS_PI_404_DATA
+			DDRSS_PI_405_DATA
+			DDRSS_PI_406_DATA
+			DDRSS_PI_407_DATA
+			DDRSS_PI_408_DATA
+			DDRSS_PI_409_DATA
+			DDRSS_PI_410_DATA
+			DDRSS_PI_411_DATA
+			DDRSS_PI_412_DATA
+			DDRSS_PI_413_DATA
+			DDRSS_PI_414_DATA
+			DDRSS_PI_415_DATA
+			DDRSS_PI_416_DATA
+			DDRSS_PI_417_DATA
+			DDRSS_PI_418_DATA
+			DDRSS_PI_419_DATA
+			DDRSS_PI_420_DATA
+			DDRSS_PI_421_DATA
+			DDRSS_PI_422_DATA
+			DDRSS_PI_423_DATA
+		>;
+
+		ti,phy-data = <
+			DDRSS_PHY_0_DATA
+			DDRSS_PHY_1_DATA
+			DDRSS_PHY_2_DATA
+			DDRSS_PHY_3_DATA
+			DDRSS_PHY_4_DATA
+			DDRSS_PHY_5_DATA
+			DDRSS_PHY_6_DATA
+			DDRSS_PHY_7_DATA
+			DDRSS_PHY_8_DATA
+			DDRSS_PHY_9_DATA
+			DDRSS_PHY_10_DATA
+			DDRSS_PHY_11_DATA
+			DDRSS_PHY_12_DATA
+			DDRSS_PHY_13_DATA
+			DDRSS_PHY_14_DATA
+			DDRSS_PHY_15_DATA
+			DDRSS_PHY_16_DATA
+			DDRSS_PHY_17_DATA
+			DDRSS_PHY_18_DATA
+			DDRSS_PHY_19_DATA
+			DDRSS_PHY_20_DATA
+			DDRSS_PHY_21_DATA
+			DDRSS_PHY_22_DATA
+			DDRSS_PHY_23_DATA
+			DDRSS_PHY_24_DATA
+			DDRSS_PHY_25_DATA
+			DDRSS_PHY_26_DATA
+			DDRSS_PHY_27_DATA
+			DDRSS_PHY_28_DATA
+			DDRSS_PHY_29_DATA
+			DDRSS_PHY_30_DATA
+			DDRSS_PHY_31_DATA
+			DDRSS_PHY_32_DATA
+			DDRSS_PHY_33_DATA
+			DDRSS_PHY_34_DATA
+			DDRSS_PHY_35_DATA
+			DDRSS_PHY_36_DATA
+			DDRSS_PHY_37_DATA
+			DDRSS_PHY_38_DATA
+			DDRSS_PHY_39_DATA
+			DDRSS_PHY_40_DATA
+			DDRSS_PHY_41_DATA
+			DDRSS_PHY_42_DATA
+			DDRSS_PHY_43_DATA
+			DDRSS_PHY_44_DATA
+			DDRSS_PHY_45_DATA
+			DDRSS_PHY_46_DATA
+			DDRSS_PHY_47_DATA
+			DDRSS_PHY_48_DATA
+			DDRSS_PHY_49_DATA
+			DDRSS_PHY_50_DATA
+			DDRSS_PHY_51_DATA
+			DDRSS_PHY_52_DATA
+			DDRSS_PHY_53_DATA
+			DDRSS_PHY_54_DATA
+			DDRSS_PHY_55_DATA
+			DDRSS_PHY_56_DATA
+			DDRSS_PHY_57_DATA
+			DDRSS_PHY_58_DATA
+			DDRSS_PHY_59_DATA
+			DDRSS_PHY_60_DATA
+			DDRSS_PHY_61_DATA
+			DDRSS_PHY_62_DATA
+			DDRSS_PHY_63_DATA
+			DDRSS_PHY_64_DATA
+			DDRSS_PHY_65_DATA
+			DDRSS_PHY_66_DATA
+			DDRSS_PHY_67_DATA
+			DDRSS_PHY_68_DATA
+			DDRSS_PHY_69_DATA
+			DDRSS_PHY_70_DATA
+			DDRSS_PHY_71_DATA
+			DDRSS_PHY_72_DATA
+			DDRSS_PHY_73_DATA
+			DDRSS_PHY_74_DATA
+			DDRSS_PHY_75_DATA
+			DDRSS_PHY_76_DATA
+			DDRSS_PHY_77_DATA
+			DDRSS_PHY_78_DATA
+			DDRSS_PHY_79_DATA
+			DDRSS_PHY_80_DATA
+			DDRSS_PHY_81_DATA
+			DDRSS_PHY_82_DATA
+			DDRSS_PHY_83_DATA
+			DDRSS_PHY_84_DATA
+			DDRSS_PHY_85_DATA
+			DDRSS_PHY_86_DATA
+			DDRSS_PHY_87_DATA
+			DDRSS_PHY_88_DATA
+			DDRSS_PHY_89_DATA
+			DDRSS_PHY_90_DATA
+			DDRSS_PHY_91_DATA
+			DDRSS_PHY_92_DATA
+			DDRSS_PHY_93_DATA
+			DDRSS_PHY_94_DATA
+			DDRSS_PHY_95_DATA
+			DDRSS_PHY_96_DATA
+			DDRSS_PHY_97_DATA
+			DDRSS_PHY_98_DATA
+			DDRSS_PHY_99_DATA
+			DDRSS_PHY_100_DATA
+			DDRSS_PHY_101_DATA
+			DDRSS_PHY_102_DATA
+			DDRSS_PHY_103_DATA
+			DDRSS_PHY_104_DATA
+			DDRSS_PHY_105_DATA
+			DDRSS_PHY_106_DATA
+			DDRSS_PHY_107_DATA
+			DDRSS_PHY_108_DATA
+			DDRSS_PHY_109_DATA
+			DDRSS_PHY_110_DATA
+			DDRSS_PHY_111_DATA
+			DDRSS_PHY_112_DATA
+			DDRSS_PHY_113_DATA
+			DDRSS_PHY_114_DATA
+			DDRSS_PHY_115_DATA
+			DDRSS_PHY_116_DATA
+			DDRSS_PHY_117_DATA
+			DDRSS_PHY_118_DATA
+			DDRSS_PHY_119_DATA
+			DDRSS_PHY_120_DATA
+			DDRSS_PHY_121_DATA
+			DDRSS_PHY_122_DATA
+			DDRSS_PHY_123_DATA
+			DDRSS_PHY_124_DATA
+			DDRSS_PHY_125_DATA
+			DDRSS_PHY_126_DATA
+			DDRSS_PHY_127_DATA
+			DDRSS_PHY_128_DATA
+			DDRSS_PHY_129_DATA
+			DDRSS_PHY_130_DATA
+			DDRSS_PHY_131_DATA
+			DDRSS_PHY_132_DATA
+			DDRSS_PHY_133_DATA
+			DDRSS_PHY_134_DATA
+			DDRSS_PHY_135_DATA
+			DDRSS_PHY_136_DATA
+			DDRSS_PHY_137_DATA
+			DDRSS_PHY_138_DATA
+			DDRSS_PHY_139_DATA
+			DDRSS_PHY_140_DATA
+			DDRSS_PHY_141_DATA
+			DDRSS_PHY_142_DATA
+			DDRSS_PHY_143_DATA
+			DDRSS_PHY_144_DATA
+			DDRSS_PHY_145_DATA
+			DDRSS_PHY_146_DATA
+			DDRSS_PHY_147_DATA
+			DDRSS_PHY_148_DATA
+			DDRSS_PHY_149_DATA
+			DDRSS_PHY_150_DATA
+			DDRSS_PHY_151_DATA
+			DDRSS_PHY_152_DATA
+			DDRSS_PHY_153_DATA
+			DDRSS_PHY_154_DATA
+			DDRSS_PHY_155_DATA
+			DDRSS_PHY_156_DATA
+			DDRSS_PHY_157_DATA
+			DDRSS_PHY_158_DATA
+			DDRSS_PHY_159_DATA
+			DDRSS_PHY_160_DATA
+			DDRSS_PHY_161_DATA
+			DDRSS_PHY_162_DATA
+			DDRSS_PHY_163_DATA
+			DDRSS_PHY_164_DATA
+			DDRSS_PHY_165_DATA
+			DDRSS_PHY_166_DATA
+			DDRSS_PHY_167_DATA
+			DDRSS_PHY_168_DATA
+			DDRSS_PHY_169_DATA
+			DDRSS_PHY_170_DATA
+			DDRSS_PHY_171_DATA
+			DDRSS_PHY_172_DATA
+			DDRSS_PHY_173_DATA
+			DDRSS_PHY_174_DATA
+			DDRSS_PHY_175_DATA
+			DDRSS_PHY_176_DATA
+			DDRSS_PHY_177_DATA
+			DDRSS_PHY_178_DATA
+			DDRSS_PHY_179_DATA
+			DDRSS_PHY_180_DATA
+			DDRSS_PHY_181_DATA
+			DDRSS_PHY_182_DATA
+			DDRSS_PHY_183_DATA
+			DDRSS_PHY_184_DATA
+			DDRSS_PHY_185_DATA
+			DDRSS_PHY_186_DATA
+			DDRSS_PHY_187_DATA
+			DDRSS_PHY_188_DATA
+			DDRSS_PHY_189_DATA
+			DDRSS_PHY_190_DATA
+			DDRSS_PHY_191_DATA
+			DDRSS_PHY_192_DATA
+			DDRSS_PHY_193_DATA
+			DDRSS_PHY_194_DATA
+			DDRSS_PHY_195_DATA
+			DDRSS_PHY_196_DATA
+			DDRSS_PHY_197_DATA
+			DDRSS_PHY_198_DATA
+			DDRSS_PHY_199_DATA
+			DDRSS_PHY_200_DATA
+			DDRSS_PHY_201_DATA
+			DDRSS_PHY_202_DATA
+			DDRSS_PHY_203_DATA
+			DDRSS_PHY_204_DATA
+			DDRSS_PHY_205_DATA
+			DDRSS_PHY_206_DATA
+			DDRSS_PHY_207_DATA
+			DDRSS_PHY_208_DATA
+			DDRSS_PHY_209_DATA
+			DDRSS_PHY_210_DATA
+			DDRSS_PHY_211_DATA
+			DDRSS_PHY_212_DATA
+			DDRSS_PHY_213_DATA
+			DDRSS_PHY_214_DATA
+			DDRSS_PHY_215_DATA
+			DDRSS_PHY_216_DATA
+			DDRSS_PHY_217_DATA
+			DDRSS_PHY_218_DATA
+			DDRSS_PHY_219_DATA
+			DDRSS_PHY_220_DATA
+			DDRSS_PHY_221_DATA
+			DDRSS_PHY_222_DATA
+			DDRSS_PHY_223_DATA
+			DDRSS_PHY_224_DATA
+			DDRSS_PHY_225_DATA
+			DDRSS_PHY_226_DATA
+			DDRSS_PHY_227_DATA
+			DDRSS_PHY_228_DATA
+			DDRSS_PHY_229_DATA
+			DDRSS_PHY_230_DATA
+			DDRSS_PHY_231_DATA
+			DDRSS_PHY_232_DATA
+			DDRSS_PHY_233_DATA
+			DDRSS_PHY_234_DATA
+			DDRSS_PHY_235_DATA
+			DDRSS_PHY_236_DATA
+			DDRSS_PHY_237_DATA
+			DDRSS_PHY_238_DATA
+			DDRSS_PHY_239_DATA
+			DDRSS_PHY_240_DATA
+			DDRSS_PHY_241_DATA
+			DDRSS_PHY_242_DATA
+			DDRSS_PHY_243_DATA
+			DDRSS_PHY_244_DATA
+			DDRSS_PHY_245_DATA
+			DDRSS_PHY_246_DATA
+			DDRSS_PHY_247_DATA
+			DDRSS_PHY_248_DATA
+			DDRSS_PHY_249_DATA
+			DDRSS_PHY_250_DATA
+			DDRSS_PHY_251_DATA
+			DDRSS_PHY_252_DATA
+			DDRSS_PHY_253_DATA
+			DDRSS_PHY_254_DATA
+			DDRSS_PHY_255_DATA
+			DDRSS_PHY_256_DATA
+			DDRSS_PHY_257_DATA
+			DDRSS_PHY_258_DATA
+			DDRSS_PHY_259_DATA
+			DDRSS_PHY_260_DATA
+			DDRSS_PHY_261_DATA
+			DDRSS_PHY_262_DATA
+			DDRSS_PHY_263_DATA
+			DDRSS_PHY_264_DATA
+			DDRSS_PHY_265_DATA
+			DDRSS_PHY_266_DATA
+			DDRSS_PHY_267_DATA
+			DDRSS_PHY_268_DATA
+			DDRSS_PHY_269_DATA
+			DDRSS_PHY_270_DATA
+			DDRSS_PHY_271_DATA
+			DDRSS_PHY_272_DATA
+			DDRSS_PHY_273_DATA
+			DDRSS_PHY_274_DATA
+			DDRSS_PHY_275_DATA
+			DDRSS_PHY_276_DATA
+			DDRSS_PHY_277_DATA
+			DDRSS_PHY_278_DATA
+			DDRSS_PHY_279_DATA
+			DDRSS_PHY_280_DATA
+			DDRSS_PHY_281_DATA
+			DDRSS_PHY_282_DATA
+			DDRSS_PHY_283_DATA
+			DDRSS_PHY_284_DATA
+			DDRSS_PHY_285_DATA
+			DDRSS_PHY_286_DATA
+			DDRSS_PHY_287_DATA
+			DDRSS_PHY_288_DATA
+			DDRSS_PHY_289_DATA
+			DDRSS_PHY_290_DATA
+			DDRSS_PHY_291_DATA
+			DDRSS_PHY_292_DATA
+			DDRSS_PHY_293_DATA
+			DDRSS_PHY_294_DATA
+			DDRSS_PHY_295_DATA
+			DDRSS_PHY_296_DATA
+			DDRSS_PHY_297_DATA
+			DDRSS_PHY_298_DATA
+			DDRSS_PHY_299_DATA
+			DDRSS_PHY_300_DATA
+			DDRSS_PHY_301_DATA
+			DDRSS_PHY_302_DATA
+			DDRSS_PHY_303_DATA
+			DDRSS_PHY_304_DATA
+			DDRSS_PHY_305_DATA
+			DDRSS_PHY_306_DATA
+			DDRSS_PHY_307_DATA
+			DDRSS_PHY_308_DATA
+			DDRSS_PHY_309_DATA
+			DDRSS_PHY_310_DATA
+			DDRSS_PHY_311_DATA
+			DDRSS_PHY_312_DATA
+			DDRSS_PHY_313_DATA
+			DDRSS_PHY_314_DATA
+			DDRSS_PHY_315_DATA
+			DDRSS_PHY_316_DATA
+			DDRSS_PHY_317_DATA
+			DDRSS_PHY_318_DATA
+			DDRSS_PHY_319_DATA
+			DDRSS_PHY_320_DATA
+			DDRSS_PHY_321_DATA
+			DDRSS_PHY_322_DATA
+			DDRSS_PHY_323_DATA
+			DDRSS_PHY_324_DATA
+			DDRSS_PHY_325_DATA
+			DDRSS_PHY_326_DATA
+			DDRSS_PHY_327_DATA
+			DDRSS_PHY_328_DATA
+			DDRSS_PHY_329_DATA
+			DDRSS_PHY_330_DATA
+			DDRSS_PHY_331_DATA
+			DDRSS_PHY_332_DATA
+			DDRSS_PHY_333_DATA
+			DDRSS_PHY_334_DATA
+			DDRSS_PHY_335_DATA
+			DDRSS_PHY_336_DATA
+			DDRSS_PHY_337_DATA
+			DDRSS_PHY_338_DATA
+			DDRSS_PHY_339_DATA
+			DDRSS_PHY_340_DATA
+			DDRSS_PHY_341_DATA
+			DDRSS_PHY_342_DATA
+			DDRSS_PHY_343_DATA
+			DDRSS_PHY_344_DATA
+			DDRSS_PHY_345_DATA
+			DDRSS_PHY_346_DATA
+			DDRSS_PHY_347_DATA
+			DDRSS_PHY_348_DATA
+			DDRSS_PHY_349_DATA
+			DDRSS_PHY_350_DATA
+			DDRSS_PHY_351_DATA
+			DDRSS_PHY_352_DATA
+			DDRSS_PHY_353_DATA
+			DDRSS_PHY_354_DATA
+			DDRSS_PHY_355_DATA
+			DDRSS_PHY_356_DATA
+			DDRSS_PHY_357_DATA
+			DDRSS_PHY_358_DATA
+			DDRSS_PHY_359_DATA
+			DDRSS_PHY_360_DATA
+			DDRSS_PHY_361_DATA
+			DDRSS_PHY_362_DATA
+			DDRSS_PHY_363_DATA
+			DDRSS_PHY_364_DATA
+			DDRSS_PHY_365_DATA
+			DDRSS_PHY_366_DATA
+			DDRSS_PHY_367_DATA
+			DDRSS_PHY_368_DATA
+			DDRSS_PHY_369_DATA
+			DDRSS_PHY_370_DATA
+			DDRSS_PHY_371_DATA
+			DDRSS_PHY_372_DATA
+			DDRSS_PHY_373_DATA
+			DDRSS_PHY_374_DATA
+			DDRSS_PHY_375_DATA
+			DDRSS_PHY_376_DATA
+			DDRSS_PHY_377_DATA
+			DDRSS_PHY_378_DATA
+			DDRSS_PHY_379_DATA
+			DDRSS_PHY_380_DATA
+			DDRSS_PHY_381_DATA
+			DDRSS_PHY_382_DATA
+			DDRSS_PHY_383_DATA
+			DDRSS_PHY_384_DATA
+			DDRSS_PHY_385_DATA
+			DDRSS_PHY_386_DATA
+			DDRSS_PHY_387_DATA
+			DDRSS_PHY_388_DATA
+			DDRSS_PHY_389_DATA
+			DDRSS_PHY_390_DATA
+			DDRSS_PHY_391_DATA
+			DDRSS_PHY_392_DATA
+			DDRSS_PHY_393_DATA
+			DDRSS_PHY_394_DATA
+			DDRSS_PHY_395_DATA
+			DDRSS_PHY_396_DATA
+			DDRSS_PHY_397_DATA
+			DDRSS_PHY_398_DATA
+			DDRSS_PHY_399_DATA
+			DDRSS_PHY_400_DATA
+			DDRSS_PHY_401_DATA
+			DDRSS_PHY_402_DATA
+			DDRSS_PHY_403_DATA
+			DDRSS_PHY_404_DATA
+			DDRSS_PHY_405_DATA
+			DDRSS_PHY_406_DATA
+			DDRSS_PHY_407_DATA
+			DDRSS_PHY_408_DATA
+			DDRSS_PHY_409_DATA
+			DDRSS_PHY_410_DATA
+			DDRSS_PHY_411_DATA
+			DDRSS_PHY_412_DATA
+			DDRSS_PHY_413_DATA
+			DDRSS_PHY_414_DATA
+			DDRSS_PHY_415_DATA
+			DDRSS_PHY_416_DATA
+			DDRSS_PHY_417_DATA
+			DDRSS_PHY_418_DATA
+			DDRSS_PHY_419_DATA
+			DDRSS_PHY_420_DATA
+			DDRSS_PHY_421_DATA
+			DDRSS_PHY_422_DATA
+			DDRSS_PHY_423_DATA
+			DDRSS_PHY_424_DATA
+			DDRSS_PHY_425_DATA
+			DDRSS_PHY_426_DATA
+			DDRSS_PHY_427_DATA
+			DDRSS_PHY_428_DATA
+			DDRSS_PHY_429_DATA
+			DDRSS_PHY_430_DATA
+			DDRSS_PHY_431_DATA
+			DDRSS_PHY_432_DATA
+			DDRSS_PHY_433_DATA
+			DDRSS_PHY_434_DATA
+			DDRSS_PHY_435_DATA
+			DDRSS_PHY_436_DATA
+			DDRSS_PHY_437_DATA
+			DDRSS_PHY_438_DATA
+			DDRSS_PHY_439_DATA
+			DDRSS_PHY_440_DATA
+			DDRSS_PHY_441_DATA
+			DDRSS_PHY_442_DATA
+			DDRSS_PHY_443_DATA
+			DDRSS_PHY_444_DATA
+			DDRSS_PHY_445_DATA
+			DDRSS_PHY_446_DATA
+			DDRSS_PHY_447_DATA
+			DDRSS_PHY_448_DATA
+			DDRSS_PHY_449_DATA
+			DDRSS_PHY_450_DATA
+			DDRSS_PHY_451_DATA
+			DDRSS_PHY_452_DATA
+			DDRSS_PHY_453_DATA
+			DDRSS_PHY_454_DATA
+			DDRSS_PHY_455_DATA
+			DDRSS_PHY_456_DATA
+			DDRSS_PHY_457_DATA
+			DDRSS_PHY_458_DATA
+			DDRSS_PHY_459_DATA
+			DDRSS_PHY_460_DATA
+			DDRSS_PHY_461_DATA
+			DDRSS_PHY_462_DATA
+			DDRSS_PHY_463_DATA
+			DDRSS_PHY_464_DATA
+			DDRSS_PHY_465_DATA
+			DDRSS_PHY_466_DATA
+			DDRSS_PHY_467_DATA
+			DDRSS_PHY_468_DATA
+			DDRSS_PHY_469_DATA
+			DDRSS_PHY_470_DATA
+			DDRSS_PHY_471_DATA
+			DDRSS_PHY_472_DATA
+			DDRSS_PHY_473_DATA
+			DDRSS_PHY_474_DATA
+			DDRSS_PHY_475_DATA
+			DDRSS_PHY_476_DATA
+			DDRSS_PHY_477_DATA
+			DDRSS_PHY_478_DATA
+			DDRSS_PHY_479_DATA
+			DDRSS_PHY_480_DATA
+			DDRSS_PHY_481_DATA
+			DDRSS_PHY_482_DATA
+			DDRSS_PHY_483_DATA
+			DDRSS_PHY_484_DATA
+			DDRSS_PHY_485_DATA
+			DDRSS_PHY_486_DATA
+			DDRSS_PHY_487_DATA
+			DDRSS_PHY_488_DATA
+			DDRSS_PHY_489_DATA
+			DDRSS_PHY_490_DATA
+			DDRSS_PHY_491_DATA
+			DDRSS_PHY_492_DATA
+			DDRSS_PHY_493_DATA
+			DDRSS_PHY_494_DATA
+			DDRSS_PHY_495_DATA
+			DDRSS_PHY_496_DATA
+			DDRSS_PHY_497_DATA
+			DDRSS_PHY_498_DATA
+			DDRSS_PHY_499_DATA
+			DDRSS_PHY_500_DATA
+			DDRSS_PHY_501_DATA
+			DDRSS_PHY_502_DATA
+			DDRSS_PHY_503_DATA
+			DDRSS_PHY_504_DATA
+			DDRSS_PHY_505_DATA
+			DDRSS_PHY_506_DATA
+			DDRSS_PHY_507_DATA
+			DDRSS_PHY_508_DATA
+			DDRSS_PHY_509_DATA
+			DDRSS_PHY_510_DATA
+			DDRSS_PHY_511_DATA
+			DDRSS_PHY_512_DATA
+			DDRSS_PHY_513_DATA
+			DDRSS_PHY_514_DATA
+			DDRSS_PHY_515_DATA
+			DDRSS_PHY_516_DATA
+			DDRSS_PHY_517_DATA
+			DDRSS_PHY_518_DATA
+			DDRSS_PHY_519_DATA
+			DDRSS_PHY_520_DATA
+			DDRSS_PHY_521_DATA
+			DDRSS_PHY_522_DATA
+			DDRSS_PHY_523_DATA
+			DDRSS_PHY_524_DATA
+			DDRSS_PHY_525_DATA
+			DDRSS_PHY_526_DATA
+			DDRSS_PHY_527_DATA
+			DDRSS_PHY_528_DATA
+			DDRSS_PHY_529_DATA
+			DDRSS_PHY_530_DATA
+			DDRSS_PHY_531_DATA
+			DDRSS_PHY_532_DATA
+			DDRSS_PHY_533_DATA
+			DDRSS_PHY_534_DATA
+			DDRSS_PHY_535_DATA
+			DDRSS_PHY_536_DATA
+			DDRSS_PHY_537_DATA
+			DDRSS_PHY_538_DATA
+			DDRSS_PHY_539_DATA
+			DDRSS_PHY_540_DATA
+			DDRSS_PHY_541_DATA
+			DDRSS_PHY_542_DATA
+			DDRSS_PHY_543_DATA
+			DDRSS_PHY_544_DATA
+			DDRSS_PHY_545_DATA
+			DDRSS_PHY_546_DATA
+			DDRSS_PHY_547_DATA
+			DDRSS_PHY_548_DATA
+			DDRSS_PHY_549_DATA
+			DDRSS_PHY_550_DATA
+			DDRSS_PHY_551_DATA
+			DDRSS_PHY_552_DATA
+			DDRSS_PHY_553_DATA
+			DDRSS_PHY_554_DATA
+			DDRSS_PHY_555_DATA
+			DDRSS_PHY_556_DATA
+			DDRSS_PHY_557_DATA
+			DDRSS_PHY_558_DATA
+			DDRSS_PHY_559_DATA
+			DDRSS_PHY_560_DATA
+			DDRSS_PHY_561_DATA
+			DDRSS_PHY_562_DATA
+			DDRSS_PHY_563_DATA
+			DDRSS_PHY_564_DATA
+			DDRSS_PHY_565_DATA
+			DDRSS_PHY_566_DATA
+			DDRSS_PHY_567_DATA
+			DDRSS_PHY_568_DATA
+			DDRSS_PHY_569_DATA
+			DDRSS_PHY_570_DATA
+			DDRSS_PHY_571_DATA
+			DDRSS_PHY_572_DATA
+			DDRSS_PHY_573_DATA
+			DDRSS_PHY_574_DATA
+			DDRSS_PHY_575_DATA
+			DDRSS_PHY_576_DATA
+			DDRSS_PHY_577_DATA
+			DDRSS_PHY_578_DATA
+			DDRSS_PHY_579_DATA
+			DDRSS_PHY_580_DATA
+			DDRSS_PHY_581_DATA
+			DDRSS_PHY_582_DATA
+			DDRSS_PHY_583_DATA
+			DDRSS_PHY_584_DATA
+			DDRSS_PHY_585_DATA
+			DDRSS_PHY_586_DATA
+			DDRSS_PHY_587_DATA
+			DDRSS_PHY_588_DATA
+			DDRSS_PHY_589_DATA
+			DDRSS_PHY_590_DATA
+			DDRSS_PHY_591_DATA
+			DDRSS_PHY_592_DATA
+			DDRSS_PHY_593_DATA
+			DDRSS_PHY_594_DATA
+			DDRSS_PHY_595_DATA
+			DDRSS_PHY_596_DATA
+			DDRSS_PHY_597_DATA
+			DDRSS_PHY_598_DATA
+			DDRSS_PHY_599_DATA
+			DDRSS_PHY_600_DATA
+			DDRSS_PHY_601_DATA
+			DDRSS_PHY_602_DATA
+			DDRSS_PHY_603_DATA
+			DDRSS_PHY_604_DATA
+			DDRSS_PHY_605_DATA
+			DDRSS_PHY_606_DATA
+			DDRSS_PHY_607_DATA
+			DDRSS_PHY_608_DATA
+			DDRSS_PHY_609_DATA
+			DDRSS_PHY_610_DATA
+			DDRSS_PHY_611_DATA
+			DDRSS_PHY_612_DATA
+			DDRSS_PHY_613_DATA
+			DDRSS_PHY_614_DATA
+			DDRSS_PHY_615_DATA
+			DDRSS_PHY_616_DATA
+			DDRSS_PHY_617_DATA
+			DDRSS_PHY_618_DATA
+			DDRSS_PHY_619_DATA
+			DDRSS_PHY_620_DATA
+			DDRSS_PHY_621_DATA
+			DDRSS_PHY_622_DATA
+			DDRSS_PHY_623_DATA
+			DDRSS_PHY_624_DATA
+			DDRSS_PHY_625_DATA
+			DDRSS_PHY_626_DATA
+			DDRSS_PHY_627_DATA
+			DDRSS_PHY_628_DATA
+			DDRSS_PHY_629_DATA
+			DDRSS_PHY_630_DATA
+			DDRSS_PHY_631_DATA
+			DDRSS_PHY_632_DATA
+			DDRSS_PHY_633_DATA
+			DDRSS_PHY_634_DATA
+			DDRSS_PHY_635_DATA
+			DDRSS_PHY_636_DATA
+			DDRSS_PHY_637_DATA
+			DDRSS_PHY_638_DATA
+			DDRSS_PHY_639_DATA
+			DDRSS_PHY_640_DATA
+			DDRSS_PHY_641_DATA
+			DDRSS_PHY_642_DATA
+			DDRSS_PHY_643_DATA
+			DDRSS_PHY_644_DATA
+			DDRSS_PHY_645_DATA
+			DDRSS_PHY_646_DATA
+			DDRSS_PHY_647_DATA
+			DDRSS_PHY_648_DATA
+			DDRSS_PHY_649_DATA
+			DDRSS_PHY_650_DATA
+			DDRSS_PHY_651_DATA
+			DDRSS_PHY_652_DATA
+			DDRSS_PHY_653_DATA
+			DDRSS_PHY_654_DATA
+			DDRSS_PHY_655_DATA
+			DDRSS_PHY_656_DATA
+			DDRSS_PHY_657_DATA
+			DDRSS_PHY_658_DATA
+			DDRSS_PHY_659_DATA
+			DDRSS_PHY_660_DATA
+			DDRSS_PHY_661_DATA
+			DDRSS_PHY_662_DATA
+			DDRSS_PHY_663_DATA
+			DDRSS_PHY_664_DATA
+			DDRSS_PHY_665_DATA
+			DDRSS_PHY_666_DATA
+			DDRSS_PHY_667_DATA
+			DDRSS_PHY_668_DATA
+			DDRSS_PHY_669_DATA
+			DDRSS_PHY_670_DATA
+			DDRSS_PHY_671_DATA
+			DDRSS_PHY_672_DATA
+			DDRSS_PHY_673_DATA
+			DDRSS_PHY_674_DATA
+			DDRSS_PHY_675_DATA
+			DDRSS_PHY_676_DATA
+			DDRSS_PHY_677_DATA
+			DDRSS_PHY_678_DATA
+			DDRSS_PHY_679_DATA
+			DDRSS_PHY_680_DATA
+			DDRSS_PHY_681_DATA
+			DDRSS_PHY_682_DATA
+			DDRSS_PHY_683_DATA
+			DDRSS_PHY_684_DATA
+			DDRSS_PHY_685_DATA
+			DDRSS_PHY_686_DATA
+			DDRSS_PHY_687_DATA
+			DDRSS_PHY_688_DATA
+			DDRSS_PHY_689_DATA
+			DDRSS_PHY_690_DATA
+			DDRSS_PHY_691_DATA
+			DDRSS_PHY_692_DATA
+			DDRSS_PHY_693_DATA
+			DDRSS_PHY_694_DATA
+			DDRSS_PHY_695_DATA
+			DDRSS_PHY_696_DATA
+			DDRSS_PHY_697_DATA
+			DDRSS_PHY_698_DATA
+			DDRSS_PHY_699_DATA
+			DDRSS_PHY_700_DATA
+			DDRSS_PHY_701_DATA
+			DDRSS_PHY_702_DATA
+			DDRSS_PHY_703_DATA
+			DDRSS_PHY_704_DATA
+			DDRSS_PHY_705_DATA
+			DDRSS_PHY_706_DATA
+			DDRSS_PHY_707_DATA
+			DDRSS_PHY_708_DATA
+			DDRSS_PHY_709_DATA
+			DDRSS_PHY_710_DATA
+			DDRSS_PHY_711_DATA
+			DDRSS_PHY_712_DATA
+			DDRSS_PHY_713_DATA
+			DDRSS_PHY_714_DATA
+			DDRSS_PHY_715_DATA
+			DDRSS_PHY_716_DATA
+			DDRSS_PHY_717_DATA
+			DDRSS_PHY_718_DATA
+			DDRSS_PHY_719_DATA
+			DDRSS_PHY_720_DATA
+			DDRSS_PHY_721_DATA
+			DDRSS_PHY_722_DATA
+			DDRSS_PHY_723_DATA
+			DDRSS_PHY_724_DATA
+			DDRSS_PHY_725_DATA
+			DDRSS_PHY_726_DATA
+			DDRSS_PHY_727_DATA
+			DDRSS_PHY_728_DATA
+			DDRSS_PHY_729_DATA
+			DDRSS_PHY_730_DATA
+			DDRSS_PHY_731_DATA
+			DDRSS_PHY_732_DATA
+			DDRSS_PHY_733_DATA
+			DDRSS_PHY_734_DATA
+			DDRSS_PHY_735_DATA
+			DDRSS_PHY_736_DATA
+			DDRSS_PHY_737_DATA
+			DDRSS_PHY_738_DATA
+			DDRSS_PHY_739_DATA
+			DDRSS_PHY_740_DATA
+			DDRSS_PHY_741_DATA
+			DDRSS_PHY_742_DATA
+			DDRSS_PHY_743_DATA
+			DDRSS_PHY_744_DATA
+			DDRSS_PHY_745_DATA
+			DDRSS_PHY_746_DATA
+			DDRSS_PHY_747_DATA
+			DDRSS_PHY_748_DATA
+			DDRSS_PHY_749_DATA
+			DDRSS_PHY_750_DATA
+			DDRSS_PHY_751_DATA
+			DDRSS_PHY_752_DATA
+			DDRSS_PHY_753_DATA
+			DDRSS_PHY_754_DATA
+			DDRSS_PHY_755_DATA
+			DDRSS_PHY_756_DATA
+			DDRSS_PHY_757_DATA
+			DDRSS_PHY_758_DATA
+			DDRSS_PHY_759_DATA
+			DDRSS_PHY_760_DATA
+			DDRSS_PHY_761_DATA
+			DDRSS_PHY_762_DATA
+			DDRSS_PHY_763_DATA
+			DDRSS_PHY_764_DATA
+			DDRSS_PHY_765_DATA
+			DDRSS_PHY_766_DATA
+			DDRSS_PHY_767_DATA
+			DDRSS_PHY_768_DATA
+			DDRSS_PHY_769_DATA
+			DDRSS_PHY_770_DATA
+			DDRSS_PHY_771_DATA
+			DDRSS_PHY_772_DATA
+			DDRSS_PHY_773_DATA
+			DDRSS_PHY_774_DATA
+			DDRSS_PHY_775_DATA
+			DDRSS_PHY_776_DATA
+			DDRSS_PHY_777_DATA
+			DDRSS_PHY_778_DATA
+			DDRSS_PHY_779_DATA
+			DDRSS_PHY_780_DATA
+			DDRSS_PHY_781_DATA
+			DDRSS_PHY_782_DATA
+			DDRSS_PHY_783_DATA
+			DDRSS_PHY_784_DATA
+			DDRSS_PHY_785_DATA
+			DDRSS_PHY_786_DATA
+			DDRSS_PHY_787_DATA
+			DDRSS_PHY_788_DATA
+			DDRSS_PHY_789_DATA
+			DDRSS_PHY_790_DATA
+			DDRSS_PHY_791_DATA
+			DDRSS_PHY_792_DATA
+			DDRSS_PHY_793_DATA
+			DDRSS_PHY_794_DATA
+			DDRSS_PHY_795_DATA
+			DDRSS_PHY_796_DATA
+			DDRSS_PHY_797_DATA
+			DDRSS_PHY_798_DATA
+			DDRSS_PHY_799_DATA
+			DDRSS_PHY_800_DATA
+			DDRSS_PHY_801_DATA
+			DDRSS_PHY_802_DATA
+			DDRSS_PHY_803_DATA
+			DDRSS_PHY_804_DATA
+			DDRSS_PHY_805_DATA
+			DDRSS_PHY_806_DATA
+			DDRSS_PHY_807_DATA
+			DDRSS_PHY_808_DATA
+			DDRSS_PHY_809_DATA
+			DDRSS_PHY_810_DATA
+			DDRSS_PHY_811_DATA
+			DDRSS_PHY_812_DATA
+			DDRSS_PHY_813_DATA
+			DDRSS_PHY_814_DATA
+			DDRSS_PHY_815_DATA
+			DDRSS_PHY_816_DATA
+			DDRSS_PHY_817_DATA
+			DDRSS_PHY_818_DATA
+			DDRSS_PHY_819_DATA
+			DDRSS_PHY_820_DATA
+			DDRSS_PHY_821_DATA
+			DDRSS_PHY_822_DATA
+			DDRSS_PHY_823_DATA
+			DDRSS_PHY_824_DATA
+			DDRSS_PHY_825_DATA
+			DDRSS_PHY_826_DATA
+			DDRSS_PHY_827_DATA
+			DDRSS_PHY_828_DATA
+			DDRSS_PHY_829_DATA
+			DDRSS_PHY_830_DATA
+			DDRSS_PHY_831_DATA
+			DDRSS_PHY_832_DATA
+			DDRSS_PHY_833_DATA
+			DDRSS_PHY_834_DATA
+			DDRSS_PHY_835_DATA
+			DDRSS_PHY_836_DATA
+			DDRSS_PHY_837_DATA
+			DDRSS_PHY_838_DATA
+			DDRSS_PHY_839_DATA
+			DDRSS_PHY_840_DATA
+			DDRSS_PHY_841_DATA
+			DDRSS_PHY_842_DATA
+			DDRSS_PHY_843_DATA
+			DDRSS_PHY_844_DATA
+			DDRSS_PHY_845_DATA
+			DDRSS_PHY_846_DATA
+			DDRSS_PHY_847_DATA
+			DDRSS_PHY_848_DATA
+			DDRSS_PHY_849_DATA
+			DDRSS_PHY_850_DATA
+			DDRSS_PHY_851_DATA
+			DDRSS_PHY_852_DATA
+			DDRSS_PHY_853_DATA
+			DDRSS_PHY_854_DATA
+			DDRSS_PHY_855_DATA
+			DDRSS_PHY_856_DATA
+			DDRSS_PHY_857_DATA
+			DDRSS_PHY_858_DATA
+			DDRSS_PHY_859_DATA
+			DDRSS_PHY_860_DATA
+			DDRSS_PHY_861_DATA
+			DDRSS_PHY_862_DATA
+			DDRSS_PHY_863_DATA
+			DDRSS_PHY_864_DATA
+			DDRSS_PHY_865_DATA
+			DDRSS_PHY_866_DATA
+			DDRSS_PHY_867_DATA
+			DDRSS_PHY_868_DATA
+			DDRSS_PHY_869_DATA
+			DDRSS_PHY_870_DATA
+			DDRSS_PHY_871_DATA
+			DDRSS_PHY_872_DATA
+			DDRSS_PHY_873_DATA
+			DDRSS_PHY_874_DATA
+			DDRSS_PHY_875_DATA
+			DDRSS_PHY_876_DATA
+			DDRSS_PHY_877_DATA
+			DDRSS_PHY_878_DATA
+			DDRSS_PHY_879_DATA
+			DDRSS_PHY_880_DATA
+			DDRSS_PHY_881_DATA
+			DDRSS_PHY_882_DATA
+			DDRSS_PHY_883_DATA
+			DDRSS_PHY_884_DATA
+			DDRSS_PHY_885_DATA
+			DDRSS_PHY_886_DATA
+			DDRSS_PHY_887_DATA
+			DDRSS_PHY_888_DATA
+			DDRSS_PHY_889_DATA
+			DDRSS_PHY_890_DATA
+			DDRSS_PHY_891_DATA
+			DDRSS_PHY_892_DATA
+			DDRSS_PHY_893_DATA
+			DDRSS_PHY_894_DATA
+			DDRSS_PHY_895_DATA
+			DDRSS_PHY_896_DATA
+			DDRSS_PHY_897_DATA
+			DDRSS_PHY_898_DATA
+			DDRSS_PHY_899_DATA
+			DDRSS_PHY_900_DATA
+			DDRSS_PHY_901_DATA
+			DDRSS_PHY_902_DATA
+			DDRSS_PHY_903_DATA
+			DDRSS_PHY_904_DATA
+			DDRSS_PHY_905_DATA
+			DDRSS_PHY_906_DATA
+			DDRSS_PHY_907_DATA
+			DDRSS_PHY_908_DATA
+			DDRSS_PHY_909_DATA
+			DDRSS_PHY_910_DATA
+			DDRSS_PHY_911_DATA
+			DDRSS_PHY_912_DATA
+			DDRSS_PHY_913_DATA
+			DDRSS_PHY_914_DATA
+			DDRSS_PHY_915_DATA
+			DDRSS_PHY_916_DATA
+			DDRSS_PHY_917_DATA
+			DDRSS_PHY_918_DATA
+			DDRSS_PHY_919_DATA
+			DDRSS_PHY_920_DATA
+			DDRSS_PHY_921_DATA
+			DDRSS_PHY_922_DATA
+			DDRSS_PHY_923_DATA
+			DDRSS_PHY_924_DATA
+			DDRSS_PHY_925_DATA
+			DDRSS_PHY_926_DATA
+			DDRSS_PHY_927_DATA
+			DDRSS_PHY_928_DATA
+			DDRSS_PHY_929_DATA
+			DDRSS_PHY_930_DATA
+			DDRSS_PHY_931_DATA
+			DDRSS_PHY_932_DATA
+			DDRSS_PHY_933_DATA
+			DDRSS_PHY_934_DATA
+			DDRSS_PHY_935_DATA
+			DDRSS_PHY_936_DATA
+			DDRSS_PHY_937_DATA
+			DDRSS_PHY_938_DATA
+			DDRSS_PHY_939_DATA
+			DDRSS_PHY_940_DATA
+			DDRSS_PHY_941_DATA
+			DDRSS_PHY_942_DATA
+			DDRSS_PHY_943_DATA
+			DDRSS_PHY_944_DATA
+			DDRSS_PHY_945_DATA
+			DDRSS_PHY_946_DATA
+			DDRSS_PHY_947_DATA
+			DDRSS_PHY_948_DATA
+			DDRSS_PHY_949_DATA
+			DDRSS_PHY_950_DATA
+			DDRSS_PHY_951_DATA
+			DDRSS_PHY_952_DATA
+			DDRSS_PHY_953_DATA
+			DDRSS_PHY_954_DATA
+			DDRSS_PHY_955_DATA
+			DDRSS_PHY_956_DATA
+			DDRSS_PHY_957_DATA
+			DDRSS_PHY_958_DATA
+			DDRSS_PHY_959_DATA
+			DDRSS_PHY_960_DATA
+			DDRSS_PHY_961_DATA
+			DDRSS_PHY_962_DATA
+			DDRSS_PHY_963_DATA
+			DDRSS_PHY_964_DATA
+			DDRSS_PHY_965_DATA
+			DDRSS_PHY_966_DATA
+			DDRSS_PHY_967_DATA
+			DDRSS_PHY_968_DATA
+			DDRSS_PHY_969_DATA
+			DDRSS_PHY_970_DATA
+			DDRSS_PHY_971_DATA
+			DDRSS_PHY_972_DATA
+			DDRSS_PHY_973_DATA
+			DDRSS_PHY_974_DATA
+			DDRSS_PHY_975_DATA
+			DDRSS_PHY_976_DATA
+			DDRSS_PHY_977_DATA
+			DDRSS_PHY_978_DATA
+			DDRSS_PHY_979_DATA
+			DDRSS_PHY_980_DATA
+			DDRSS_PHY_981_DATA
+			DDRSS_PHY_982_DATA
+			DDRSS_PHY_983_DATA
+			DDRSS_PHY_984_DATA
+			DDRSS_PHY_985_DATA
+			DDRSS_PHY_986_DATA
+			DDRSS_PHY_987_DATA
+			DDRSS_PHY_988_DATA
+			DDRSS_PHY_989_DATA
+			DDRSS_PHY_990_DATA
+			DDRSS_PHY_991_DATA
+			DDRSS_PHY_992_DATA
+			DDRSS_PHY_993_DATA
+			DDRSS_PHY_994_DATA
+			DDRSS_PHY_995_DATA
+			DDRSS_PHY_996_DATA
+			DDRSS_PHY_997_DATA
+			DDRSS_PHY_998_DATA
+			DDRSS_PHY_999_DATA
+			DDRSS_PHY_1000_DATA
+			DDRSS_PHY_1001_DATA
+			DDRSS_PHY_1002_DATA
+			DDRSS_PHY_1003_DATA
+			DDRSS_PHY_1004_DATA
+			DDRSS_PHY_1005_DATA
+			DDRSS_PHY_1006_DATA
+			DDRSS_PHY_1007_DATA
+			DDRSS_PHY_1008_DATA
+			DDRSS_PHY_1009_DATA
+			DDRSS_PHY_1010_DATA
+			DDRSS_PHY_1011_DATA
+			DDRSS_PHY_1012_DATA
+			DDRSS_PHY_1013_DATA
+			DDRSS_PHY_1014_DATA
+			DDRSS_PHY_1015_DATA
+			DDRSS_PHY_1016_DATA
+			DDRSS_PHY_1017_DATA
+			DDRSS_PHY_1018_DATA
+			DDRSS_PHY_1019_DATA
+			DDRSS_PHY_1020_DATA
+			DDRSS_PHY_1021_DATA
+			DDRSS_PHY_1022_DATA
+			DDRSS_PHY_1023_DATA
+			DDRSS_PHY_1024_DATA
+			DDRSS_PHY_1025_DATA
+			DDRSS_PHY_1026_DATA
+			DDRSS_PHY_1027_DATA
+			DDRSS_PHY_1028_DATA
+			DDRSS_PHY_1029_DATA
+			DDRSS_PHY_1030_DATA
+			DDRSS_PHY_1031_DATA
+			DDRSS_PHY_1032_DATA
+			DDRSS_PHY_1033_DATA
+			DDRSS_PHY_1034_DATA
+			DDRSS_PHY_1035_DATA
+			DDRSS_PHY_1036_DATA
+			DDRSS_PHY_1037_DATA
+			DDRSS_PHY_1038_DATA
+			DDRSS_PHY_1039_DATA
+			DDRSS_PHY_1040_DATA
+			DDRSS_PHY_1041_DATA
+			DDRSS_PHY_1042_DATA
+			DDRSS_PHY_1043_DATA
+			DDRSS_PHY_1044_DATA
+			DDRSS_PHY_1045_DATA
+			DDRSS_PHY_1046_DATA
+			DDRSS_PHY_1047_DATA
+			DDRSS_PHY_1048_DATA
+			DDRSS_PHY_1049_DATA
+			DDRSS_PHY_1050_DATA
+			DDRSS_PHY_1051_DATA
+			DDRSS_PHY_1052_DATA
+			DDRSS_PHY_1053_DATA
+			DDRSS_PHY_1054_DATA
+			DDRSS_PHY_1055_DATA
+			DDRSS_PHY_1056_DATA
+			DDRSS_PHY_1057_DATA
+			DDRSS_PHY_1058_DATA
+			DDRSS_PHY_1059_DATA
+			DDRSS_PHY_1060_DATA
+			DDRSS_PHY_1061_DATA
+			DDRSS_PHY_1062_DATA
+			DDRSS_PHY_1063_DATA
+			DDRSS_PHY_1064_DATA
+			DDRSS_PHY_1065_DATA
+			DDRSS_PHY_1066_DATA
+			DDRSS_PHY_1067_DATA
+			DDRSS_PHY_1068_DATA
+			DDRSS_PHY_1069_DATA
+			DDRSS_PHY_1070_DATA
+			DDRSS_PHY_1071_DATA
+			DDRSS_PHY_1072_DATA
+			DDRSS_PHY_1073_DATA
+			DDRSS_PHY_1074_DATA
+			DDRSS_PHY_1075_DATA
+			DDRSS_PHY_1076_DATA
+			DDRSS_PHY_1077_DATA
+			DDRSS_PHY_1078_DATA
+			DDRSS_PHY_1079_DATA
+			DDRSS_PHY_1080_DATA
+			DDRSS_PHY_1081_DATA
+			DDRSS_PHY_1082_DATA
+			DDRSS_PHY_1083_DATA
+			DDRSS_PHY_1084_DATA
+			DDRSS_PHY_1085_DATA
+			DDRSS_PHY_1086_DATA
+			DDRSS_PHY_1087_DATA
+			DDRSS_PHY_1088_DATA
+			DDRSS_PHY_1089_DATA
+			DDRSS_PHY_1090_DATA
+			DDRSS_PHY_1091_DATA
+			DDRSS_PHY_1092_DATA
+			DDRSS_PHY_1093_DATA
+			DDRSS_PHY_1094_DATA
+			DDRSS_PHY_1095_DATA
+			DDRSS_PHY_1096_DATA
+			DDRSS_PHY_1097_DATA
+			DDRSS_PHY_1098_DATA
+			DDRSS_PHY_1099_DATA
+			DDRSS_PHY_1100_DATA
+			DDRSS_PHY_1101_DATA
+			DDRSS_PHY_1102_DATA
+			DDRSS_PHY_1103_DATA
+			DDRSS_PHY_1104_DATA
+			DDRSS_PHY_1105_DATA
+			DDRSS_PHY_1106_DATA
+			DDRSS_PHY_1107_DATA
+			DDRSS_PHY_1108_DATA
+			DDRSS_PHY_1109_DATA
+			DDRSS_PHY_1110_DATA
+			DDRSS_PHY_1111_DATA
+			DDRSS_PHY_1112_DATA
+			DDRSS_PHY_1113_DATA
+			DDRSS_PHY_1114_DATA
+			DDRSS_PHY_1115_DATA
+			DDRSS_PHY_1116_DATA
+			DDRSS_PHY_1117_DATA
+			DDRSS_PHY_1118_DATA
+			DDRSS_PHY_1119_DATA
+			DDRSS_PHY_1120_DATA
+			DDRSS_PHY_1121_DATA
+			DDRSS_PHY_1122_DATA
+			DDRSS_PHY_1123_DATA
+			DDRSS_PHY_1124_DATA
+			DDRSS_PHY_1125_DATA
+			DDRSS_PHY_1126_DATA
+			DDRSS_PHY_1127_DATA
+			DDRSS_PHY_1128_DATA
+			DDRSS_PHY_1129_DATA
+			DDRSS_PHY_1130_DATA
+			DDRSS_PHY_1131_DATA
+			DDRSS_PHY_1132_DATA
+			DDRSS_PHY_1133_DATA
+			DDRSS_PHY_1134_DATA
+			DDRSS_PHY_1135_DATA
+			DDRSS_PHY_1136_DATA
+			DDRSS_PHY_1137_DATA
+			DDRSS_PHY_1138_DATA
+			DDRSS_PHY_1139_DATA
+			DDRSS_PHY_1140_DATA
+			DDRSS_PHY_1141_DATA
+			DDRSS_PHY_1142_DATA
+			DDRSS_PHY_1143_DATA
+			DDRSS_PHY_1144_DATA
+			DDRSS_PHY_1145_DATA
+			DDRSS_PHY_1146_DATA
+			DDRSS_PHY_1147_DATA
+			DDRSS_PHY_1148_DATA
+			DDRSS_PHY_1149_DATA
+			DDRSS_PHY_1150_DATA
+			DDRSS_PHY_1151_DATA
+			DDRSS_PHY_1152_DATA
+			DDRSS_PHY_1153_DATA
+			DDRSS_PHY_1154_DATA
+			DDRSS_PHY_1155_DATA
+			DDRSS_PHY_1156_DATA
+			DDRSS_PHY_1157_DATA
+			DDRSS_PHY_1158_DATA
+			DDRSS_PHY_1159_DATA
+			DDRSS_PHY_1160_DATA
+			DDRSS_PHY_1161_DATA
+			DDRSS_PHY_1162_DATA
+			DDRSS_PHY_1163_DATA
+			DDRSS_PHY_1164_DATA
+			DDRSS_PHY_1165_DATA
+			DDRSS_PHY_1166_DATA
+			DDRSS_PHY_1167_DATA
+			DDRSS_PHY_1168_DATA
+			DDRSS_PHY_1169_DATA
+			DDRSS_PHY_1170_DATA
+			DDRSS_PHY_1171_DATA
+			DDRSS_PHY_1172_DATA
+			DDRSS_PHY_1173_DATA
+			DDRSS_PHY_1174_DATA
+			DDRSS_PHY_1175_DATA
+			DDRSS_PHY_1176_DATA
+			DDRSS_PHY_1177_DATA
+			DDRSS_PHY_1178_DATA
+			DDRSS_PHY_1179_DATA
+			DDRSS_PHY_1180_DATA
+			DDRSS_PHY_1181_DATA
+			DDRSS_PHY_1182_DATA
+			DDRSS_PHY_1183_DATA
+			DDRSS_PHY_1184_DATA
+			DDRSS_PHY_1185_DATA
+			DDRSS_PHY_1186_DATA
+			DDRSS_PHY_1187_DATA
+			DDRSS_PHY_1188_DATA
+			DDRSS_PHY_1189_DATA
+			DDRSS_PHY_1190_DATA
+			DDRSS_PHY_1191_DATA
+			DDRSS_PHY_1192_DATA
+			DDRSS_PHY_1193_DATA
+			DDRSS_PHY_1194_DATA
+			DDRSS_PHY_1195_DATA
+			DDRSS_PHY_1196_DATA
+			DDRSS_PHY_1197_DATA
+			DDRSS_PHY_1198_DATA
+			DDRSS_PHY_1199_DATA
+			DDRSS_PHY_1200_DATA
+			DDRSS_PHY_1201_DATA
+			DDRSS_PHY_1202_DATA
+			DDRSS_PHY_1203_DATA
+			DDRSS_PHY_1204_DATA
+			DDRSS_PHY_1205_DATA
+			DDRSS_PHY_1206_DATA
+			DDRSS_PHY_1207_DATA
+			DDRSS_PHY_1208_DATA
+			DDRSS_PHY_1209_DATA
+			DDRSS_PHY_1210_DATA
+			DDRSS_PHY_1211_DATA
+			DDRSS_PHY_1212_DATA
+			DDRSS_PHY_1213_DATA
+			DDRSS_PHY_1214_DATA
+			DDRSS_PHY_1215_DATA
+			DDRSS_PHY_1216_DATA
+			DDRSS_PHY_1217_DATA
+			DDRSS_PHY_1218_DATA
+			DDRSS_PHY_1219_DATA
+			DDRSS_PHY_1220_DATA
+			DDRSS_PHY_1221_DATA
+			DDRSS_PHY_1222_DATA
+			DDRSS_PHY_1223_DATA
+			DDRSS_PHY_1224_DATA
+			DDRSS_PHY_1225_DATA
+			DDRSS_PHY_1226_DATA
+			DDRSS_PHY_1227_DATA
+			DDRSS_PHY_1228_DATA
+			DDRSS_PHY_1229_DATA
+			DDRSS_PHY_1230_DATA
+			DDRSS_PHY_1231_DATA
+			DDRSS_PHY_1232_DATA
+			DDRSS_PHY_1233_DATA
+			DDRSS_PHY_1234_DATA
+			DDRSS_PHY_1235_DATA
+			DDRSS_PHY_1236_DATA
+			DDRSS_PHY_1237_DATA
+			DDRSS_PHY_1238_DATA
+			DDRSS_PHY_1239_DATA
+			DDRSS_PHY_1240_DATA
+			DDRSS_PHY_1241_DATA
+			DDRSS_PHY_1242_DATA
+			DDRSS_PHY_1243_DATA
+			DDRSS_PHY_1244_DATA
+			DDRSS_PHY_1245_DATA
+			DDRSS_PHY_1246_DATA
+			DDRSS_PHY_1247_DATA
+			DDRSS_PHY_1248_DATA
+			DDRSS_PHY_1249_DATA
+			DDRSS_PHY_1250_DATA
+			DDRSS_PHY_1251_DATA
+			DDRSS_PHY_1252_DATA
+			DDRSS_PHY_1253_DATA
+			DDRSS_PHY_1254_DATA
+			DDRSS_PHY_1255_DATA
+			DDRSS_PHY_1256_DATA
+			DDRSS_PHY_1257_DATA
+			DDRSS_PHY_1258_DATA
+			DDRSS_PHY_1259_DATA
+			DDRSS_PHY_1260_DATA
+			DDRSS_PHY_1261_DATA
+			DDRSS_PHY_1262_DATA
+			DDRSS_PHY_1263_DATA
+			DDRSS_PHY_1264_DATA
+			DDRSS_PHY_1265_DATA
+			DDRSS_PHY_1266_DATA
+			DDRSS_PHY_1267_DATA
+			DDRSS_PHY_1268_DATA
+			DDRSS_PHY_1269_DATA
+			DDRSS_PHY_1270_DATA
+			DDRSS_PHY_1271_DATA
+			DDRSS_PHY_1272_DATA
+			DDRSS_PHY_1273_DATA
+			DDRSS_PHY_1274_DATA
+			DDRSS_PHY_1275_DATA
+			DDRSS_PHY_1276_DATA
+			DDRSS_PHY_1277_DATA
+			DDRSS_PHY_1278_DATA
+			DDRSS_PHY_1279_DATA
+			DDRSS_PHY_1280_DATA
+			DDRSS_PHY_1281_DATA
+			DDRSS_PHY_1282_DATA
+			DDRSS_PHY_1283_DATA
+			DDRSS_PHY_1284_DATA
+			DDRSS_PHY_1285_DATA
+			DDRSS_PHY_1286_DATA
+			DDRSS_PHY_1287_DATA
+			DDRSS_PHY_1288_DATA
+			DDRSS_PHY_1289_DATA
+			DDRSS_PHY_1290_DATA
+			DDRSS_PHY_1291_DATA
+			DDRSS_PHY_1292_DATA
+			DDRSS_PHY_1293_DATA
+			DDRSS_PHY_1294_DATA
+			DDRSS_PHY_1295_DATA
+			DDRSS_PHY_1296_DATA
+			DDRSS_PHY_1297_DATA
+			DDRSS_PHY_1298_DATA
+			DDRSS_PHY_1299_DATA
+			DDRSS_PHY_1300_DATA
+			DDRSS_PHY_1301_DATA
+			DDRSS_PHY_1302_DATA
+			DDRSS_PHY_1303_DATA
+			DDRSS_PHY_1304_DATA
+			DDRSS_PHY_1305_DATA
+			DDRSS_PHY_1306_DATA
+			DDRSS_PHY_1307_DATA
+			DDRSS_PHY_1308_DATA
+			DDRSS_PHY_1309_DATA
+			DDRSS_PHY_1310_DATA
+			DDRSS_PHY_1311_DATA
+			DDRSS_PHY_1312_DATA
+			DDRSS_PHY_1313_DATA
+			DDRSS_PHY_1314_DATA
+			DDRSS_PHY_1315_DATA
+			DDRSS_PHY_1316_DATA
+			DDRSS_PHY_1317_DATA
+			DDRSS_PHY_1318_DATA
+			DDRSS_PHY_1319_DATA
+			DDRSS_PHY_1320_DATA
+			DDRSS_PHY_1321_DATA
+			DDRSS_PHY_1322_DATA
+			DDRSS_PHY_1323_DATA
+			DDRSS_PHY_1324_DATA
+			DDRSS_PHY_1325_DATA
+			DDRSS_PHY_1326_DATA
+			DDRSS_PHY_1327_DATA
+			DDRSS_PHY_1328_DATA
+			DDRSS_PHY_1329_DATA
+			DDRSS_PHY_1330_DATA
+			DDRSS_PHY_1331_DATA
+			DDRSS_PHY_1332_DATA
+			DDRSS_PHY_1333_DATA
+			DDRSS_PHY_1334_DATA
+			DDRSS_PHY_1335_DATA
+			DDRSS_PHY_1336_DATA
+			DDRSS_PHY_1337_DATA
+			DDRSS_PHY_1338_DATA
+			DDRSS_PHY_1339_DATA
+			DDRSS_PHY_1340_DATA
+			DDRSS_PHY_1341_DATA
+			DDRSS_PHY_1342_DATA
+			DDRSS_PHY_1343_DATA
+			DDRSS_PHY_1344_DATA
+			DDRSS_PHY_1345_DATA
+			DDRSS_PHY_1346_DATA
+			DDRSS_PHY_1347_DATA
+			DDRSS_PHY_1348_DATA
+			DDRSS_PHY_1349_DATA
+			DDRSS_PHY_1350_DATA
+			DDRSS_PHY_1351_DATA
+			DDRSS_PHY_1352_DATA
+			DDRSS_PHY_1353_DATA
+			DDRSS_PHY_1354_DATA
+			DDRSS_PHY_1355_DATA
+			DDRSS_PHY_1356_DATA
+			DDRSS_PHY_1357_DATA
+			DDRSS_PHY_1358_DATA
+			DDRSS_PHY_1359_DATA
+			DDRSS_PHY_1360_DATA
+			DDRSS_PHY_1361_DATA
+			DDRSS_PHY_1362_DATA
+			DDRSS_PHY_1363_DATA
+			DDRSS_PHY_1364_DATA
+			DDRSS_PHY_1365_DATA
+			DDRSS_PHY_1366_DATA
+			DDRSS_PHY_1367_DATA
+			DDRSS_PHY_1368_DATA
+			DDRSS_PHY_1369_DATA
+			DDRSS_PHY_1370_DATA
+			DDRSS_PHY_1371_DATA
+			DDRSS_PHY_1372_DATA
+			DDRSS_PHY_1373_DATA
+			DDRSS_PHY_1374_DATA
+			DDRSS_PHY_1375_DATA
+			DDRSS_PHY_1376_DATA
+			DDRSS_PHY_1377_DATA
+			DDRSS_PHY_1378_DATA
+			DDRSS_PHY_1379_DATA
+			DDRSS_PHY_1380_DATA
+			DDRSS_PHY_1381_DATA
+			DDRSS_PHY_1382_DATA
+			DDRSS_PHY_1383_DATA
+			DDRSS_PHY_1384_DATA
+			DDRSS_PHY_1385_DATA
+			DDRSS_PHY_1386_DATA
+			DDRSS_PHY_1387_DATA
+			DDRSS_PHY_1388_DATA
+			DDRSS_PHY_1389_DATA
+			DDRSS_PHY_1390_DATA
+			DDRSS_PHY_1391_DATA
+			DDRSS_PHY_1392_DATA
+			DDRSS_PHY_1393_DATA
+			DDRSS_PHY_1394_DATA
+			DDRSS_PHY_1395_DATA
+			DDRSS_PHY_1396_DATA
+			DDRSS_PHY_1397_DATA
+			DDRSS_PHY_1398_DATA
+			DDRSS_PHY_1399_DATA
+			DDRSS_PHY_1400_DATA
+			DDRSS_PHY_1401_DATA
+			DDRSS_PHY_1402_DATA
+			DDRSS_PHY_1403_DATA
+			DDRSS_PHY_1404_DATA
+			DDRSS_PHY_1405_DATA
+			DDRSS_PHY_1406_DATA
+			DDRSS_PHY_1407_DATA
+			DDRSS_PHY_1408_DATA
+			DDRSS_PHY_1409_DATA
+			DDRSS_PHY_1410_DATA
+			DDRSS_PHY_1411_DATA
+			DDRSS_PHY_1412_DATA
+			DDRSS_PHY_1413_DATA
+			DDRSS_PHY_1414_DATA
+			DDRSS_PHY_1415_DATA
+			DDRSS_PHY_1416_DATA
+			DDRSS_PHY_1417_DATA
+			DDRSS_PHY_1418_DATA
+			DDRSS_PHY_1419_DATA
+			DDRSS_PHY_1420_DATA
+			DDRSS_PHY_1421_DATA
+			DDRSS_PHY_1422_DATA
+			DDRSS_PHY_1423_DATA
+			DDRSS_PHY_1424_DATA
+			DDRSS_PHY_1425_DATA
+			DDRSS_PHY_1426_DATA
+			DDRSS_PHY_1427_DATA
+			DDRSS_PHY_1428_DATA
+			DDRSS_PHY_1429_DATA
+			DDRSS_PHY_1430_DATA
+			DDRSS_PHY_1431_DATA
+			DDRSS_PHY_1432_DATA
+			DDRSS_PHY_1433_DATA
+			DDRSS_PHY_1434_DATA
+			DDRSS_PHY_1435_DATA
+			DDRSS_PHY_1436_DATA
+			DDRSS_PHY_1437_DATA
+			DDRSS_PHY_1438_DATA
+			DDRSS_PHY_1439_DATA
+			DDRSS_PHY_1440_DATA
+			DDRSS_PHY_1441_DATA
+			DDRSS_PHY_1442_DATA
+			DDRSS_PHY_1443_DATA
+			DDRSS_PHY_1444_DATA
+			DDRSS_PHY_1445_DATA
+			DDRSS_PHY_1446_DATA
+			DDRSS_PHY_1447_DATA
+			DDRSS_PHY_1448_DATA
+			DDRSS_PHY_1449_DATA
+			DDRSS_PHY_1450_DATA
+			DDRSS_PHY_1451_DATA
+			DDRSS_PHY_1452_DATA
+			DDRSS_PHY_1453_DATA
+			DDRSS_PHY_1454_DATA
+			DDRSS_PHY_1455_DATA
+			DDRSS_PHY_1456_DATA
+			DDRSS_PHY_1457_DATA
+			DDRSS_PHY_1458_DATA
+			DDRSS_PHY_1459_DATA
+			DDRSS_PHY_1460_DATA
+			DDRSS_PHY_1461_DATA
+			DDRSS_PHY_1462_DATA
+			DDRSS_PHY_1463_DATA
+			DDRSS_PHY_1464_DATA
+			DDRSS_PHY_1465_DATA
+			DDRSS_PHY_1466_DATA
+			DDRSS_PHY_1467_DATA
+			DDRSS_PHY_1468_DATA
+			DDRSS_PHY_1469_DATA
+			DDRSS_PHY_1470_DATA
+			DDRSS_PHY_1471_DATA
+			DDRSS_PHY_1472_DATA
+			DDRSS_PHY_1473_DATA
+			DDRSS_PHY_1474_DATA
+			DDRSS_PHY_1475_DATA
+			DDRSS_PHY_1476_DATA
+			DDRSS_PHY_1477_DATA
+			DDRSS_PHY_1478_DATA
+			DDRSS_PHY_1479_DATA
+			DDRSS_PHY_1480_DATA
+			DDRSS_PHY_1481_DATA
+			DDRSS_PHY_1482_DATA
+			DDRSS_PHY_1483_DATA
+			DDRSS_PHY_1484_DATA
+			DDRSS_PHY_1485_DATA
+			DDRSS_PHY_1486_DATA
+			DDRSS_PHY_1487_DATA
+			DDRSS_PHY_1488_DATA
+			DDRSS_PHY_1489_DATA
+			DDRSS_PHY_1490_DATA
+			DDRSS_PHY_1491_DATA
+			DDRSS_PHY_1492_DATA
+			DDRSS_PHY_1493_DATA
+			DDRSS_PHY_1494_DATA
+			DDRSS_PHY_1495_DATA
+			DDRSS_PHY_1496_DATA
+			DDRSS_PHY_1497_DATA
+			DDRSS_PHY_1498_DATA
+			DDRSS_PHY_1499_DATA
+			DDRSS_PHY_1500_DATA
+			DDRSS_PHY_1501_DATA
+			DDRSS_PHY_1502_DATA
+			DDRSS_PHY_1503_DATA
+			DDRSS_PHY_1504_DATA
+			DDRSS_PHY_1505_DATA
+			DDRSS_PHY_1506_DATA
+			DDRSS_PHY_1507_DATA
+			DDRSS_PHY_1508_DATA
+			DDRSS_PHY_1509_DATA
+			DDRSS_PHY_1510_DATA
+			DDRSS_PHY_1511_DATA
+			DDRSS_PHY_1512_DATA
+			DDRSS_PHY_1513_DATA
+			DDRSS_PHY_1514_DATA
+			DDRSS_PHY_1515_DATA
+			DDRSS_PHY_1516_DATA
+			DDRSS_PHY_1517_DATA
+			DDRSS_PHY_1518_DATA
+			DDRSS_PHY_1519_DATA
+			DDRSS_PHY_1520_DATA
+			DDRSS_PHY_1521_DATA
+			DDRSS_PHY_1522_DATA
+			DDRSS_PHY_1523_DATA
+			DDRSS_PHY_1524_DATA
+			DDRSS_PHY_1525_DATA
+			DDRSS_PHY_1526_DATA
+			DDRSS_PHY_1527_DATA
+			DDRSS_PHY_1528_DATA
+			DDRSS_PHY_1529_DATA
+			DDRSS_PHY_1530_DATA
+			DDRSS_PHY_1531_DATA
+			DDRSS_PHY_1532_DATA
+			DDRSS_PHY_1533_DATA
+			DDRSS_PHY_1534_DATA
+			DDRSS_PHY_1535_DATA
+			DDRSS_PHY_1536_DATA
+			DDRSS_PHY_1537_DATA
+			DDRSS_PHY_1538_DATA
+			DDRSS_PHY_1539_DATA
+			DDRSS_PHY_1540_DATA
+			DDRSS_PHY_1541_DATA
+			DDRSS_PHY_1542_DATA
+			DDRSS_PHY_1543_DATA
+			DDRSS_PHY_1544_DATA
+			DDRSS_PHY_1545_DATA
+			DDRSS_PHY_1546_DATA
+			DDRSS_PHY_1547_DATA
+			DDRSS_PHY_1548_DATA
+			DDRSS_PHY_1549_DATA
+			DDRSS_PHY_1550_DATA
+			DDRSS_PHY_1551_DATA
+			DDRSS_PHY_1552_DATA
+			DDRSS_PHY_1553_DATA
+			DDRSS_PHY_1554_DATA
+			DDRSS_PHY_1555_DATA
+			DDRSS_PHY_1556_DATA
+			DDRSS_PHY_1557_DATA
+			DDRSS_PHY_1558_DATA
+			DDRSS_PHY_1559_DATA
+			DDRSS_PHY_1560_DATA
+			DDRSS_PHY_1561_DATA
+			DDRSS_PHY_1562_DATA
+			DDRSS_PHY_1563_DATA
+			DDRSS_PHY_1564_DATA
+			DDRSS_PHY_1565_DATA
+			DDRSS_PHY_1566_DATA
+			DDRSS_PHY_1567_DATA
+			DDRSS_PHY_1568_DATA
+			DDRSS_PHY_1569_DATA
+			DDRSS_PHY_1570_DATA
+			DDRSS_PHY_1571_DATA
+			DDRSS_PHY_1572_DATA
+			DDRSS_PHY_1573_DATA
+			DDRSS_PHY_1574_DATA
+			DDRSS_PHY_1575_DATA
+			DDRSS_PHY_1576_DATA
+			DDRSS_PHY_1577_DATA
+			DDRSS_PHY_1578_DATA
+			DDRSS_PHY_1579_DATA
+			DDRSS_PHY_1580_DATA
+			DDRSS_PHY_1581_DATA
+			DDRSS_PHY_1582_DATA
+			DDRSS_PHY_1583_DATA
+			DDRSS_PHY_1584_DATA
+			DDRSS_PHY_1585_DATA
+			DDRSS_PHY_1586_DATA
+			DDRSS_PHY_1587_DATA
+			DDRSS_PHY_1588_DATA
+			DDRSS_PHY_1589_DATA
+			DDRSS_PHY_1590_DATA
+			DDRSS_PHY_1591_DATA
+			DDRSS_PHY_1592_DATA
+			DDRSS_PHY_1593_DATA
+			DDRSS_PHY_1594_DATA
+			DDRSS_PHY_1595_DATA
+			DDRSS_PHY_1596_DATA
+			DDRSS_PHY_1597_DATA
+			DDRSS_PHY_1598_DATA
+			DDRSS_PHY_1599_DATA
+			DDRSS_PHY_1600_DATA
+			DDRSS_PHY_1601_DATA
+			DDRSS_PHY_1602_DATA
+			DDRSS_PHY_1603_DATA
+			DDRSS_PHY_1604_DATA
+			DDRSS_PHY_1605_DATA
+			DDRSS_PHY_1606_DATA
+			DDRSS_PHY_1607_DATA
+			DDRSS_PHY_1608_DATA
+			DDRSS_PHY_1609_DATA
+			DDRSS_PHY_1610_DATA
+			DDRSS_PHY_1611_DATA
+			DDRSS_PHY_1612_DATA
+			DDRSS_PHY_1613_DATA
+			DDRSS_PHY_1614_DATA
+			DDRSS_PHY_1615_DATA
+			DDRSS_PHY_1616_DATA
+			DDRSS_PHY_1617_DATA
+			DDRSS_PHY_1618_DATA
+			DDRSS_PHY_1619_DATA
+			DDRSS_PHY_1620_DATA
+			DDRSS_PHY_1621_DATA
+			DDRSS_PHY_1622_DATA
+			DDRSS_PHY_1623_DATA
+			DDRSS_PHY_1624_DATA
+			DDRSS_PHY_1625_DATA
+			DDRSS_PHY_1626_DATA
+			DDRSS_PHY_1627_DATA
+			DDRSS_PHY_1628_DATA
+			DDRSS_PHY_1629_DATA
+			DDRSS_PHY_1630_DATA
+			DDRSS_PHY_1631_DATA
+			DDRSS_PHY_1632_DATA
+			DDRSS_PHY_1633_DATA
+			DDRSS_PHY_1634_DATA
+			DDRSS_PHY_1635_DATA
+			DDRSS_PHY_1636_DATA
+			DDRSS_PHY_1637_DATA
+			DDRSS_PHY_1638_DATA
+			DDRSS_PHY_1639_DATA
+			DDRSS_PHY_1640_DATA
+			DDRSS_PHY_1641_DATA
+			DDRSS_PHY_1642_DATA
+			DDRSS_PHY_1643_DATA
+			DDRSS_PHY_1644_DATA
+			DDRSS_PHY_1645_DATA
+			DDRSS_PHY_1646_DATA
+			DDRSS_PHY_1647_DATA
+			DDRSS_PHY_1648_DATA
+			DDRSS_PHY_1649_DATA
+			DDRSS_PHY_1650_DATA
+			DDRSS_PHY_1651_DATA
+			DDRSS_PHY_1652_DATA
+			DDRSS_PHY_1653_DATA
+			DDRSS_PHY_1654_DATA
+			DDRSS_PHY_1655_DATA
+			DDRSS_PHY_1656_DATA
+			DDRSS_PHY_1657_DATA
+			DDRSS_PHY_1658_DATA
+			DDRSS_PHY_1659_DATA
+			DDRSS_PHY_1660_DATA
+			DDRSS_PHY_1661_DATA
+			DDRSS_PHY_1662_DATA
+			DDRSS_PHY_1663_DATA
+			DDRSS_PHY_1664_DATA
+			DDRSS_PHY_1665_DATA
+			DDRSS_PHY_1666_DATA
+			DDRSS_PHY_1667_DATA
+			DDRSS_PHY_1668_DATA
+			DDRSS_PHY_1669_DATA
+			DDRSS_PHY_1670_DATA
+			DDRSS_PHY_1671_DATA
+			DDRSS_PHY_1672_DATA
+			DDRSS_PHY_1673_DATA
+			DDRSS_PHY_1674_DATA
+			DDRSS_PHY_1675_DATA
+			DDRSS_PHY_1676_DATA
+			DDRSS_PHY_1677_DATA
+			DDRSS_PHY_1678_DATA
+			DDRSS_PHY_1679_DATA
+			DDRSS_PHY_1680_DATA
+			DDRSS_PHY_1681_DATA
+			DDRSS_PHY_1682_DATA
+			DDRSS_PHY_1683_DATA
+			DDRSS_PHY_1684_DATA
+			DDRSS_PHY_1685_DATA
+			DDRSS_PHY_1686_DATA
+			DDRSS_PHY_1687_DATA
+			DDRSS_PHY_1688_DATA
+			DDRSS_PHY_1689_DATA
+			DDRSS_PHY_1690_DATA
+			DDRSS_PHY_1691_DATA
+			DDRSS_PHY_1692_DATA
+			DDRSS_PHY_1693_DATA
+			DDRSS_PHY_1694_DATA
+			DDRSS_PHY_1695_DATA
+			DDRSS_PHY_1696_DATA
+			DDRSS_PHY_1697_DATA
+			DDRSS_PHY_1698_DATA
+			DDRSS_PHY_1699_DATA
+			DDRSS_PHY_1700_DATA
+			DDRSS_PHY_1701_DATA
+			DDRSS_PHY_1702_DATA
+			DDRSS_PHY_1703_DATA
+			DDRSS_PHY_1704_DATA
+			DDRSS_PHY_1705_DATA
+			DDRSS_PHY_1706_DATA
+			DDRSS_PHY_1707_DATA
+			DDRSS_PHY_1708_DATA
+			DDRSS_PHY_1709_DATA
+			DDRSS_PHY_1710_DATA
+			DDRSS_PHY_1711_DATA
+			DDRSS_PHY_1712_DATA
+			DDRSS_PHY_1713_DATA
+			DDRSS_PHY_1714_DATA
+			DDRSS_PHY_1715_DATA
+			DDRSS_PHY_1716_DATA
+			DDRSS_PHY_1717_DATA
+			DDRSS_PHY_1718_DATA
+			DDRSS_PHY_1719_DATA
+			DDRSS_PHY_1720_DATA
+			DDRSS_PHY_1721_DATA
+			DDRSS_PHY_1722_DATA
+			DDRSS_PHY_1723_DATA
+			DDRSS_PHY_1724_DATA
+			DDRSS_PHY_1725_DATA
+			DDRSS_PHY_1726_DATA
+			DDRSS_PHY_1727_DATA
+			DDRSS_PHY_1728_DATA
+			DDRSS_PHY_1729_DATA
+			DDRSS_PHY_1730_DATA
+			DDRSS_PHY_1731_DATA
+			DDRSS_PHY_1732_DATA
+			DDRSS_PHY_1733_DATA
+			DDRSS_PHY_1734_DATA
+			DDRSS_PHY_1735_DATA
+			DDRSS_PHY_1736_DATA
+			DDRSS_PHY_1737_DATA
+			DDRSS_PHY_1738_DATA
+			DDRSS_PHY_1739_DATA
+			DDRSS_PHY_1740_DATA
+			DDRSS_PHY_1741_DATA
+			DDRSS_PHY_1742_DATA
+			DDRSS_PHY_1743_DATA
+			DDRSS_PHY_1744_DATA
+			DDRSS_PHY_1745_DATA
+			DDRSS_PHY_1746_DATA
+			DDRSS_PHY_1747_DATA
+			DDRSS_PHY_1748_DATA
+			DDRSS_PHY_1749_DATA
+			DDRSS_PHY_1750_DATA
+			DDRSS_PHY_1751_DATA
+			DDRSS_PHY_1752_DATA
+			DDRSS_PHY_1753_DATA
+			DDRSS_PHY_1754_DATA
+			DDRSS_PHY_1755_DATA
+			DDRSS_PHY_1756_DATA
+			DDRSS_PHY_1757_DATA
+			DDRSS_PHY_1758_DATA
+			DDRSS_PHY_1759_DATA
+			DDRSS_PHY_1760_DATA
+			DDRSS_PHY_1761_DATA
+			DDRSS_PHY_1762_DATA
+			DDRSS_PHY_1763_DATA
+			DDRSS_PHY_1764_DATA
+			DDRSS_PHY_1765_DATA
+			DDRSS_PHY_1766_DATA
+			DDRSS_PHY_1767_DATA
+			DDRSS_PHY_1768_DATA
+			DDRSS_PHY_1769_DATA
+			DDRSS_PHY_1770_DATA
+			DDRSS_PHY_1771_DATA
+			DDRSS_PHY_1772_DATA
+			DDRSS_PHY_1773_DATA
+			DDRSS_PHY_1774_DATA
+			DDRSS_PHY_1775_DATA
+			DDRSS_PHY_1776_DATA
+			DDRSS_PHY_1777_DATA
+			DDRSS_PHY_1778_DATA
+			DDRSS_PHY_1779_DATA
+			DDRSS_PHY_1780_DATA
+			DDRSS_PHY_1781_DATA
+			DDRSS_PHY_1782_DATA
+			DDRSS_PHY_1783_DATA
+			DDRSS_PHY_1784_DATA
+			DDRSS_PHY_1785_DATA
+			DDRSS_PHY_1786_DATA
+			DDRSS_PHY_1787_DATA
+			DDRSS_PHY_1788_DATA
+			DDRSS_PHY_1789_DATA
+			DDRSS_PHY_1790_DATA
+			DDRSS_PHY_1791_DATA
+			DDRSS_PHY_1792_DATA
+			DDRSS_PHY_1793_DATA
+			DDRSS_PHY_1794_DATA
+			DDRSS_PHY_1795_DATA
+			DDRSS_PHY_1796_DATA
+			DDRSS_PHY_1797_DATA
+			DDRSS_PHY_1798_DATA
+			DDRSS_PHY_1799_DATA
+			DDRSS_PHY_1800_DATA
+			DDRSS_PHY_1801_DATA
+			DDRSS_PHY_1802_DATA
+			DDRSS_PHY_1803_DATA
+			DDRSS_PHY_1804_DATA
+			DDRSS_PHY_1805_DATA
+			DDRSS_PHY_1806_DATA
+			DDRSS_PHY_1807_DATA
+			DDRSS_PHY_1808_DATA
+			DDRSS_PHY_1809_DATA
+			DDRSS_PHY_1810_DATA
+			DDRSS_PHY_1811_DATA
+			DDRSS_PHY_1812_DATA
+			DDRSS_PHY_1813_DATA
+			DDRSS_PHY_1814_DATA
+			DDRSS_PHY_1815_DATA
+			DDRSS_PHY_1816_DATA
+			DDRSS_PHY_1817_DATA
+			DDRSS_PHY_1818_DATA
+			DDRSS_PHY_1819_DATA
+			DDRSS_PHY_1820_DATA
+			DDRSS_PHY_1821_DATA
+			DDRSS_PHY_1822_DATA
+			DDRSS_PHY_1823_DATA
+			DDRSS_PHY_1824_DATA
+			DDRSS_PHY_1825_DATA
+			DDRSS_PHY_1826_DATA
+			DDRSS_PHY_1827_DATA
+			DDRSS_PHY_1828_DATA
+			DDRSS_PHY_1829_DATA
+			DDRSS_PHY_1830_DATA
+			DDRSS_PHY_1831_DATA
+			DDRSS_PHY_1832_DATA
+			DDRSS_PHY_1833_DATA
+			DDRSS_PHY_1834_DATA
+			DDRSS_PHY_1835_DATA
+			DDRSS_PHY_1836_DATA
+			DDRSS_PHY_1837_DATA
+			DDRSS_PHY_1838_DATA
+			DDRSS_PHY_1839_DATA
+			DDRSS_PHY_1840_DATA
+			DDRSS_PHY_1841_DATA
+			DDRSS_PHY_1842_DATA
+			DDRSS_PHY_1843_DATA
+			DDRSS_PHY_1844_DATA
+			DDRSS_PHY_1845_DATA
+			DDRSS_PHY_1846_DATA
+			DDRSS_PHY_1847_DATA
+			DDRSS_PHY_1848_DATA
+			DDRSS_PHY_1849_DATA
+			DDRSS_PHY_1850_DATA
+			DDRSS_PHY_1851_DATA
+			DDRSS_PHY_1852_DATA
+			DDRSS_PHY_1853_DATA
+			DDRSS_PHY_1854_DATA
+			DDRSS_PHY_1855_DATA
+			DDRSS_PHY_1856_DATA
+			DDRSS_PHY_1857_DATA
+			DDRSS_PHY_1858_DATA
+			DDRSS_PHY_1859_DATA
+			DDRSS_PHY_1860_DATA
+			DDRSS_PHY_1861_DATA
+			DDRSS_PHY_1862_DATA
+			DDRSS_PHY_1863_DATA
+			DDRSS_PHY_1864_DATA
+			DDRSS_PHY_1865_DATA
+			DDRSS_PHY_1866_DATA
+			DDRSS_PHY_1867_DATA
+			DDRSS_PHY_1868_DATA
+			DDRSS_PHY_1869_DATA
+			DDRSS_PHY_1870_DATA
+			DDRSS_PHY_1871_DATA
+			DDRSS_PHY_1872_DATA
+			DDRSS_PHY_1873_DATA
+			DDRSS_PHY_1874_DATA
+			DDRSS_PHY_1875_DATA
+			DDRSS_PHY_1876_DATA
+			DDRSS_PHY_1877_DATA
+			DDRSS_PHY_1878_DATA
+			DDRSS_PHY_1879_DATA
+			DDRSS_PHY_1880_DATA
+			DDRSS_PHY_1881_DATA
+			DDRSS_PHY_1882_DATA
+			DDRSS_PHY_1883_DATA
+			DDRSS_PHY_1884_DATA
+			DDRSS_PHY_1885_DATA
+			DDRSS_PHY_1886_DATA
+			DDRSS_PHY_1887_DATA
+			DDRSS_PHY_1888_DATA
+			DDRSS_PHY_1889_DATA
+			DDRSS_PHY_1890_DATA
+			DDRSS_PHY_1891_DATA
+			DDRSS_PHY_1892_DATA
+			DDRSS_PHY_1893_DATA
+			DDRSS_PHY_1894_DATA
+			DDRSS_PHY_1895_DATA
+			DDRSS_PHY_1896_DATA
+			DDRSS_PHY_1897_DATA
+			DDRSS_PHY_1898_DATA
+			DDRSS_PHY_1899_DATA
+			DDRSS_PHY_1900_DATA
+			DDRSS_PHY_1901_DATA
+			DDRSS_PHY_1902_DATA
+			DDRSS_PHY_1903_DATA
+			DDRSS_PHY_1904_DATA
+			DDRSS_PHY_1905_DATA
+			DDRSS_PHY_1906_DATA
+			DDRSS_PHY_1907_DATA
+			DDRSS_PHY_1908_DATA
+			DDRSS_PHY_1909_DATA
+			DDRSS_PHY_1910_DATA
+			DDRSS_PHY_1911_DATA
+			DDRSS_PHY_1912_DATA
+			DDRSS_PHY_1913_DATA
+			DDRSS_PHY_1914_DATA
+			DDRSS_PHY_1915_DATA
+			DDRSS_PHY_1916_DATA
+			DDRSS_PHY_1917_DATA
+			DDRSS_PHY_1918_DATA
+			DDRSS_PHY_1919_DATA
+			DDRSS_PHY_1920_DATA
+			DDRSS_PHY_1921_DATA
+			DDRSS_PHY_1922_DATA
+			DDRSS_PHY_1923_DATA
+		>;
+	};
+};

+ 298 - 0
arch/arm/dts/k3-am62a-main.dtsi

@@ -0,0 +1,298 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM62A SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+	oc_sram: sram@70000000 {
+		compatible = "mmio-sram";
+		reg = <0x00 0x70000000 0x00 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x00 0x70000000 0x10000>;
+	};
+
+	gic500: interrupt-controller@1800000 {
+		compatible = "arm,gic-v3";
+		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
+		      <0x00 0x01880000 0x00 0xc0000>,	/* GICR */
+		      <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
+		      <0x01 0x00000000 0x00 0x2000>,    /* GICC */
+		      <0x01 0x00010000 0x00 0x1000>,    /* GICH */
+		      <0x01 0x00020000 0x00 0x2000>;    /* GICV */
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		/*
+		 * vcpumntirq:
+		 * virtual CPU interface maintenance interrupt
+		 */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+		gic_its: msi-controller@1820000 {
+			compatible = "arm,gic-v3-its";
+			reg = <0x00 0x01820000 0x00 0x10000>;
+			socionext,synquacer-pre-its = <0x1000000 0x400000>;
+			msi-controller;
+			#msi-cells = <1>;
+		};
+	};
+
+	main_conf: syscon@100000 {
+		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+		reg = <0x00 0x00100000 0x00 0x20000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x00 0x00 0x00100000 0x20000>;
+	};
+
+	dmss: bus@48000000 {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-ranges;
+		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
+
+		ti,sci-dev-id = <25>;
+
+		secure_proxy_main: mailbox@4d000000 {
+			compatible = "ti,am654-secure-proxy";
+			reg = <0x00 0x4d000000 0x00 0x80000>,
+			      <0x00 0x4a600000 0x00 0x80000>,
+			      <0x00 0x4a400000 0x00 0x80000>;
+			reg-names = "target_data", "rt", "scfg";
+			#mbox-cells = <1>;
+			interrupt-names = "rx_012";
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
+	dmsc: system-controller@44043000 {
+		compatible = "ti,k2g-sci";
+		reg = <0x00 0x44043000 0x00 0xfe0>;
+		reg-names = "debug_messages";
+		ti,host-id = <12>;
+		mbox-names = "rx", "tx";
+		mboxes= <&secure_proxy_main 12>,
+			<&secure_proxy_main 13>;
+
+		k3_pds: power-controller {
+			compatible = "ti,sci-pm-domain";
+			#power-domain-cells = <2>;
+		};
+
+		k3_clks: clock-controller {
+			compatible = "ti,k2g-sci-clk";
+			#clock-cells = <2>;
+		};
+
+		k3_reset: reset-controller {
+			compatible = "ti,sci-reset";
+			#reset-cells = <2>;
+		};
+	};
+
+	main_pmx0: pinctrl@f4000 {
+		compatible = "pinctrl-single";
+		reg = <0x00 0xf4000 0x00 0x2ac>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0xffffffff>;
+	};
+
+	main_uart0: serial@2800000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02800000 0x00 0x100>;
+		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 146 0>;
+		clock-names = "fclk";
+		status = "disabled";
+	};
+
+	main_uart1: serial@2810000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02810000 0x00 0x100>;
+		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 152 0>;
+		clock-names = "fclk";
+		status = "disabled";
+	};
+
+	main_uart2: serial@2820000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02820000 0x00 0x100>;
+		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 153 0>;
+		clock-names = "fclk";
+		status = "disabled";
+	};
+
+	main_uart3: serial@2830000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02830000 0x00 0x100>;
+		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 154 0>;
+		clock-names = "fclk";
+		status = "disabled";
+	};
+
+	main_uart4: serial@2840000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02840000 0x00 0x100>;
+		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 155 0>;
+		clock-names = "fclk";
+		status = "disabled";
+	};
+
+	main_uart5: serial@2850000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02850000 0x00 0x100>;
+		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 156 0>;
+		clock-names = "fclk";
+		status = "disabled";
+	};
+
+	main_uart6: serial@2860000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02860000 0x00 0x100>;
+		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 158 0>;
+		clock-names = "fclk";
+		status = "disabled";
+	};
+
+	main_i2c0: i2c@20000000 {
+		compatible = "ti,am64-i2c", "ti,omap4-i2c";
+		reg = <0x00 0x20000000 0x00 0x100>;
+		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 102 2>;
+		clock-names = "fck";
+		status = "disabled";
+	};
+
+	main_i2c1: i2c@20010000 {
+		compatible = "ti,am64-i2c", "ti,omap4-i2c";
+		reg = <0x00 0x20010000 0x00 0x100>;
+		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 103 2>;
+		clock-names = "fck";
+		status = "disabled";
+	};
+
+	main_i2c2: i2c@20020000 {
+		compatible = "ti,am64-i2c", "ti,omap4-i2c";
+		reg = <0x00 0x20020000 0x00 0x100>;
+		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 104 2>;
+		clock-names = "fck";
+		status = "disabled";
+	};
+
+	main_i2c3: i2c@20030000 {
+		compatible = "ti,am64-i2c", "ti,omap4-i2c";
+		reg = <0x00 0x20030000 0x00 0x100>;
+		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 105 2>;
+		clock-names = "fck";
+		status = "disabled";
+	};
+
+	main_gpio_intr: interrupt-controller@a00000 {
+		compatible = "ti,sci-intr";
+		reg = <0x00 0x00a00000 0x00 0x800>;
+		ti,intr-trigger-type = <1>;
+		interrupt-controller;
+		interrupt-parent = <&gic500>;
+		#interrupt-cells = <1>;
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <3>;
+		ti,interrupt-ranges = <0 32 16>;
+		status = "disabled";
+	};
+
+	main_gpio0: gpio@600000 {
+		compatible = "ti,am64-gpio", "ti,keystone-gpio";
+		reg = <0x00 0x00600000 0x0 0x100>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&main_gpio_intr>;
+		interrupts = <190>, <191>, <192>,
+			     <193>, <194>, <195>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		ti,ngpio = <87>;
+		ti,davinci-gpio-unbanked = <0>;
+		power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 77 0>;
+		clock-names = "gpio";
+		status = "disabled";
+	};
+
+	main_gpio1: gpio@601000 {
+		compatible = "ti,am64-gpio", "ti,keystone-gpio";
+		reg = <0x00 0x00601000 0x0 0x100>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&main_gpio_intr>;
+		interrupts = <180>, <181>, <182>,
+			     <183>, <184>, <185>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		ti,ngpio = <88>;
+		ti,davinci-gpio-unbanked = <0>;
+		power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 78 0>;
+		clock-names = "gpio";
+		status = "disabled";
+	};
+
+	sdhci1: mmc@fa00000 {
+		compatible = "ti,am62-sdhci";
+		reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
+		clock-names = "clk_ahb", "clk_xin";
+		ti,trm-icp = <0x2>;
+		ti,otap-del-sel-legacy = <0x0>;
+		ti,otap-del-sel-sd-hs = <0x0>;
+		ti,otap-del-sel-sdr12 = <0xf>;
+		ti,otap-del-sel-sdr25 = <0xf>;
+		ti,otap-del-sel-sdr50 = <0xc>;
+		ti,otap-del-sel-sdr104 = <0x6>;
+		ti,otap-del-sel-ddr50 = <0x9>;
+		ti,itap-del-sel-legacy = <0x0>;
+		ti,itap-del-sel-sd-hs = <0x0>;
+		ti,itap-del-sel-sdr12 = <0x0>;
+		ti,itap-del-sel-sdr25 = <0x0>;
+		ti,clkbuf-sel = <0x7>;
+		bus-width = <4>;
+		no-1-8-v;
+		status = "disabled";
+	};
+};

+ 39 - 0
arch/arm/dts/k3-am62a-mcu.dtsi

@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM625 SoC Family MCU Domain peripherals
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_mcu {
+	mcu_pmx0: pinctrl@4084000 {
+		compatible = "pinctrl-single";
+		reg = <0x00 0x04084000 0x00 0x88>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0xffffffff>;
+		status = "disabled";
+	};
+
+	mcu_uart0: serial@4a00000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x04a00000 0x00 0x100>;
+		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 149 0>;
+		clock-names = "fclk";
+		status = "disabled";
+	};
+
+	mcu_i2c0: i2c@4900000 {
+		compatible = "ti,am64-i2c", "ti,omap4-i2c";
+		reg = <0x00 0x04900000 0x00 0x100>;
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 106 2>;
+		clock-names = "fck";
+		status = "disabled";
+	};
+};

+ 54 - 0
arch/arm/dts/k3-am62a-wakeup.dtsi

@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_wakeup {
+	wkup_conf: syscon@43000000 {
+		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+		reg = <0x00 0x43000000 0x00 0x20000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x00 0x00 0x43000000 0x20000>;
+
+		chipid: chipid@14 {
+			compatible = "ti,am654-chipid";
+			reg = <0x14 0x4>;
+		};
+	};
+
+	wkup_uart0: serial@2b300000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x2b300000 0x00 0x100>;
+		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 114 0>;
+		clock-names = "fclk";
+		status = "disabled";
+	};
+
+	wkup_i2c0: i2c@2b200000 {
+		compatible = "ti,am64-i2c", "ti,omap4-i2c";
+		reg = <0x00 0x02b200000 0x00 0x100>;
+		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 107 4>;
+		clock-names = "fck";
+		status = "disabled";
+	};
+
+	wkup_rtc0: rtc@2b1f0000 {
+		compatible = "ti,am62-rtc";
+		reg = <0x00 0x2b1f0000 0x00 0x100>;
+		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
+		clock-names = "vbus", "osc32k";
+		power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
+		wakeup-source;
+		status = "disabled";
+	};
+};

+ 122 - 0
arch/arm/dts/k3-am62a.dtsi

@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM62A SoC Family
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+/ {
+	model = "Texas Instruments K3 AM62A SoC";
+	compatible = "ti,am62a7";
+	interrupt-parent = <&gic500>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+
+		psci: psci {
+			compatible = "arm,psci-1.0";
+			method = "smc";
+		};
+	};
+
+	a53_timer0: timer-cl0-cpu0 {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	cbass_main: bus@f0000 {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
+			 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
+			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+			 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
+			 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
+			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+			 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
+			 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
+			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
+			 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
+			 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
+			 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
+			 <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
+			 <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
+			 <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
+			 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
+			 <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
+			 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
+			 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
+			 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
+			 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
+			 <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
+			 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
+			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
+			 <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00100000>, /* C7x_0 */
+			 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
+			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
+
+			 /* MCU Domain Range */
+			 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
+			 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
+			 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
+			 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU R5 IRAM0 */
+			 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, /* MCU R5 IRAM1 */
+
+			 /* Wakeup Domain Range */
+			 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
+			 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
+			 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
+			 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM */
+			 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM */
+
+		cbass_mcu: bus@4000000 {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
+				 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
+				 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
+				 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
+				 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
+		};
+
+		cbass_wakeup: bus@b00000 {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
+				 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
+				 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
+				 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
+				 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
+		};
+	};
+};
+
+/* Now include the peripherals for each bus segments */
+#include "k3-am62a-main.dtsi"
+#include "k3-am62a-mcu.dtsi"
+#include "k3-am62a-wakeup.dtsi"

+ 143 - 0
arch/arm/dts/k3-am62a7-r5-sk.dts

@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM62A7 SK dts file for R5 SPL
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-am62a7-sk.dts"
+#include "k3-am62a-ddr-1866mhz-32bit.dtsi"
+#include "k3-am62a-ddr.dtsi"
+
+#include "k3-am62a7-sk-u-boot.dtsi"
+
+/ {
+	aliases {
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+		serial0 = &wkup_uart0;
+		serial3 = &main_uart1;
+	};
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+		tick-timer = &timer1;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>; /* 2G RAM */
+		u-boot,dm-spl;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+			alignment = <0x1000>;
+			no-map;
+		};
+	};
+
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x00 0x00a90000 0x00 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 135 0>;
+		clocks = <&k3_clks 61 0>;
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		assigned-clock-parents = <&k3_clks 61 2>;
+		assigned-clock-rates = <200000000>, <1200000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		u-boot,dm-spl;
+	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <36>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&secure_proxy_main 22>,
+			<&secure_proxy_main 23>;
+		u-boot,dm-spl;
+	};
+};
+
+&dmsc {
+	mboxes= <&secure_proxy_main 0>,
+		<&secure_proxy_main 1>,
+		<&secure_proxy_main 0>;
+	mbox-names = "rx", "tx", "notify";
+	ti,host-id = <35>;
+	ti,secure-host;
+};
+
+&cbass_main {
+	sa3_secproxy: secproxy@44880000 {
+		compatible = "ti,am654-secure-proxy";
+		#mbox-cells = <1>;
+		reg = <0x00 0x44880000 0x00 0x20000>,
+		      <0x0 0x44860000 0x0 0x20000>,
+		      <0x0 0x43600000 0x0 0x10000>;
+		reg-names = "rt", "scfg", "target_data";
+		u-boot,dm-spl;
+	};
+
+	sysctrler: sysctrler {
+		compatible = "ti,am654-system-controller";
+		mboxes= <&secure_proxy_main 1>,
+			<&secure_proxy_main 0>,
+			<&sa3_secproxy 0>;
+		mbox-names = "tx", "rx", "boot_notify";
+		u-boot,dm-spl;
+	};
+};
+
+&mcu_pmx0 {
+	status = "okay";
+	u-boot,dm-spl;
+
+	wkup_uart0_pins_default: wkup-uart0-pins-default {
+		pinctrl-single,pins = <
+			AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0)	/* (C6) WKUP_UART0_CTSn */
+			AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0)	/* (A4) WKUP_UART0_RTSn */
+			AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0)	/* (B4) WKUP_UART0_RXD */
+			AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0)	/* (C5) WKUP_UART0_TXD */
+		>;
+		u-boot,dm-spl;
+	};
+};
+
+&main_pmx0 {
+	u-boot,dm-spl;
+	main_uart1_pins_default: main-uart1-pins-default {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x194, PIN_INPUT, 2)	/* (B19) MCASP0_AXR3.UART1_CTSn */
+			AM62X_IOPAD(0x198, PIN_OUTPUT, 2)	/* (A19) MCASP0_AXR2.UART1_RTSn */
+			AM62X_IOPAD(0x1ac, PIN_INPUT, 2)	/* (E19) MCASP0_AFSR.UART1_RXD */
+			AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2)	/* (A20) MCASP0_ACLKR.UART1_TXD */
+		>;
+		u-boot,dm-spl;
+	};
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&wkup_uart0_pins_default>;
+	status = "okay";
+	u-boot,dm-spl;
+};
+
+/* Main UART1 is used for TIFS firmware logs */
+&main_uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart1_pins_default>;
+	status = "okay";
+	u-boot,dm-spl;
+};

+ 140 - 0
arch/arm/dts/k3-am62a7-sk-u-boot.dtsi

@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common AM62A EVM dts file for SPLs
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+	chosen {
+		stdout-path = "serial2:115200n8";
+		tick-timer = &timer1;
+	};
+
+	memory@80000000 {
+		u-boot,dm-spl;
+	};
+};
+
+&cbass_main{
+	u-boot,dm-spl;
+
+	timer1: timer@2400000 {
+		compatible = "ti,omap5430-timer";
+		reg = <0x00 0x2400000 0x00 0x80>;
+		ti,timer-alwon;
+		clock-frequency = <25000000>;
+		u-boot,dm-spl;
+	};
+};
+
+&dmss {
+	u-boot,dm-spl;
+};
+
+&secure_proxy_main {
+	u-boot,dm-spl;
+};
+
+&dmsc {
+	u-boot,dm-spl;
+};
+
+&k3_pds {
+	u-boot,dm-spl;
+};
+
+&k3_clks {
+	u-boot,dm-spl;
+};
+
+&k3_reset {
+	u-boot,dm-spl;
+};
+
+&wkup_conf {
+	u-boot,dm-spl;
+};
+
+&chipid {
+	u-boot,dm-spl;
+};
+
+&main_pmx0 {
+	u-boot,dm-spl;
+};
+
+&main_uart0 {
+	u-boot,dm-spl;
+};
+
+&main_uart0_pins_default {
+	u-boot,dm-spl;
+};
+
+&main_uart1 {
+	u-boot,dm-spl;
+};
+
+&cbass_mcu {
+	u-boot,dm-spl;
+};
+
+&cbass_wakeup {
+	u-boot,dm-spl;
+};
+
+&mcu_pmx0 {
+	u-boot,dm-spl;
+};
+
+&wkup_uart0 {
+	u-boot,dm-spl;
+};
+
+&main_gpio0 {
+	u-boot,dm-spl;
+};
+
+&main_i2c0 {
+	u-boot,dm-spl;
+};
+
+&main_i2c0_pins_default {
+	u-boot,dm-spl;
+};
+
+&main_i2c1 {
+	u-boot,dm-spl;
+};
+
+&main_i2c1_pins_default {
+	u-boot,dm-spl;
+};
+
+&exp1 {
+	u-boot,dm-spl;
+};
+
+&sdhci1 {
+	u-boot,dm-spl;
+};
+
+&main_mmc1_pins_default {
+	u-boot,dm-spl;
+};
+
+&k3_reset {
+	u-boot,dm-spl;
+};
+
+&dmsc {
+	u-boot,dm-spl;
+	k3_sysreset: sysreset-controller {
+		compatible = "ti,sci-sysreset";
+		u-boot,dm-spl;
+	};
+};
+
+&vdd_mmc1 {
+	u-boot,dm-spl;
+};

+ 223 - 0
arch/arm/dts/k3-am62a7-sk.dts

@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM62A SK: https://www.ti.com/lit/zip/sprr459
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "k3-am62a7.dtsi"
+
+/ {
+	compatible =  "ti,am62a7-sk", "ti,am62a7";
+	model = "Texas Instruments AM62A7 SK";
+
+	aliases {
+		serial2 = &main_uart0;
+		mmc1 = &sdhci1;
+	};
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 2G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secure_tfa_ddr: tfa@9e780000 {
+			reg = <0x00 0x9e780000 0x00 0x80000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9c900000 0x00 0x01e00000>;
+			no-map;
+		};
+	};
+
+	vmain_pd: regulator-0 {
+		/* TPS25750 PD CONTROLLER OUTPUT */
+		compatible = "regulator-fixed";
+		regulator-name = "vmain_pd";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_5v0: regulator-1 {
+		/* Output of TPS63070 */
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vmain_pd>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_3v3_sys: regulator-2 {
+		/* output of LM5141-Q1 */
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_sys";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vmain_pd>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_mmc1: regulator-3 {
+		/* TPS22918DBVR */
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_mmc1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		enable-active-high;
+		gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&usr_led_pins_default>;
+
+		led-0 {
+			label = "am62a-sk:green:heartbeat";
+			gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			function = LED_FUNCTION_HEARTBEAT;
+			default-state = "off";
+		};
+	};
+};
+
+&main_pmx0 {
+	main_uart0_pins_default: main-uart0-pins-default {
+		pinctrl-single,pins = <
+			AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
+			AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
+		>;
+	};
+
+	main_i2c0_pins_default: main-i2c0-pins-default {
+		pinctrl-single,pins = <
+			AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
+			AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
+		>;
+	};
+
+	main_i2c1_pins_default: main-i2c1-pins-default {
+		pinctrl-single,pins = <
+			AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
+			AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
+		>;
+	};
+
+	main_i2c2_pins_default: main-i2c2-pins-default {
+		pinctrl-single,pins = <
+			AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
+			AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
+		>;
+	};
+
+	main_mmc1_pins_default: main-mmc1-pins-default {
+		pinctrl-single,pins = <
+			AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
+			AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
+			AM62AX_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
+			AM62AX_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
+			AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
+			AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
+			AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
+		>;
+	};
+
+	usr_led_pins_default: usr-led-pins-default {
+		pinctrl-single,pins = <
+			AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */
+		>;
+	};
+};
+
+&main_i2c0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c0_pins_default>;
+	clock-frequency = <400000>;
+};
+
+&main_i2c1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c1_pins_default>;
+	clock-frequency = <400000>;
+
+	exp1: gpio@22 {
+		compatible = "ti,tca6424";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
+				   "BT_EN_SOC", "MMC1_SD_EN",
+				   "VPP_EN", "EXP_PS_3V3_En",
+				   "EXP_PS_5V0_En", "EXP_HAT_DETECT",
+				   "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
+				   "UART1_FET_BUF_EN", "BT_UART_WAKE_SOC",
+				   "GPIO_HDMI_RSTn", "CSI_GPIO0",
+				   "CSI_GPIO1", "WLAN_ALERTn",
+				   "HDMI_INTn", "TEST_GPIO2",
+				   "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
+				   "MCASP1_FET_SEL", "UART1_FET_SEL",
+				   "PD_I2C_IRQ", "IO_EXP_TEST_LED";
+	};
+};
+
+&sdhci1 {
+	/* SD/MMC */
+	status = "okay";
+	vmmc-supply = <&vdd_mmc1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_mmc1_pins_default>;
+	ti,driver-strength-ohm = <50>;
+	disable-wp;
+};
+
+&main_gpio0 {
+	status = "okay";
+};
+
+&main_gpio1 {
+	status = "okay";
+};
+
+&main_gpio_intr {
+	status = "okay";
+};
+
+&main_uart0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart0_pins_default>;
+};

+ 103 - 0
arch/arm/dts/k3-am62a7.dtsi

@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM62A7 SoC family in Quad core configuration
+ *
+ * TRM: https://www.ti.com/lit/zip/spruj16
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am62a.dtsi"
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0: cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53";
+			reg = <0x000>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53";
+			reg = <0x001>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu2: cpu@2 {
+			compatible = "arm,cortex-a53";
+			reg = <0x002>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu3: cpu@3 {
+			compatible = "arm,cortex-a53";
+			reg = <0x003>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&L2_0>;
+		};
+	};
+
+	L2_0: l2-cache0 {
+		compatible = "cache";
+		cache-level = <2>;
+		cache-size = <0x40000>;
+		cache-line-size = <64>;
+		cache-sets = <512>;
+	};
+};

+ 8 - 0
arch/arm/dts/k3-am64-mcu.dtsi

@@ -97,4 +97,12 @@
 		clocks = <&k3_clks 79 0>;
 		clock-names = "gpio";
 	};
+
+	mcu_pmx0: pinctrl@4084000 {
+		compatible = "pinctrl-single";
+		reg = <0x00 0x4084000 0x00 0x84>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0xffffffff>;
+	};
 };

+ 92 - 0
arch/arm/dts/nuvoton-common-npcm8xx.dtsi

@@ -4,6 +4,7 @@
 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	#address-cells = <2>;
@@ -60,6 +61,70 @@
 			reg = <0x0 0xf0801000 0x0 0x1000>;
 		};
 
+		sdhci0: sdhci@f0842000 {
+			compatible = "nuvoton,npcm845-sdhci";
+			reg = <0x0 0xf0842000 0x0 0x100>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			clocks =  <&clk NPCM8XX_CLK_AHB>;
+			clock-names = "clk_mmc";
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc8_pins
+				     &mmc_pins>;
+			status = "disabled";
+		};
+
+		fiu0: spi@fb000000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xfb000000 0x0 0x1000>,
+			<0x0 0x80000000 0x0 0x10000000>;
+			reg-names = "control", "memory";
+			clocks = <&clk NPCM8XX_CLK_SPI0>;
+			clock-names = "clk_ahb";
+			status = "disabled";
+		};
+
+		fiu1: spi@fb002000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xfb002000 0x0 0x1000>,
+			<0x0 0x90000000 0x0 0x4000000>;
+			reg-names = "control", "memory";
+			clocks = <&clk NPCM8XX_CLK_SPI1>;
+			clock-names = "clk_spi1";
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi1_pins>;
+			status = "disabled";
+		};
+
+		fiu3: spi@c0000000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xc0000000 0x0 0x1000>,
+			<0x0 0xA0000000 0x0 0x20000000>;
+			reg-names = "control", "memory";
+			clocks = <&clk NPCM8XX_CLK_SPI3>;
+			clock-names = "clk_spi3";
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi3_pins>;
+			status = "disabled";
+		};
+
+		fiux: spi@fb001000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xfb001000 0x0 0x1000>,
+			<0x0 0xf8000000 0x0 0x2000000>;
+			reg-names = "control", "memory";
+			clocks = <&clk NPCM8XX_CLK_SPIX>;
+			clock-names = "clk_ahb";
+			status = "disabled";
+		};
+
 		apb {
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -68,6 +133,19 @@
 			ranges = <0x0 0x0 0xf0000000 0x00300000>,
 				<0xfff00000 0x0 0xfff00000 0x00016000>;
 
+			spi1: spi@201000 {
+				compatible = "nuvoton,npcm845-pspi";
+				reg = <0x201000 0x1000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pspi_pins>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk NPCM8XX_CLK_APB5>;
+				clock-names = "clk_apb5";
+				status = "disabled";
+			};
+
 			timer0: timer@8000 {
 				compatible = "nuvoton,npcm845-timer";
 				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
@@ -165,6 +243,20 @@
 				clocks = <&clk NPCM8XX_CLK_REFCLK>;
 				syscon = <&gcr>;
 			};
+
+			i2c0: i2c@80000 {
+				compatible = "nuvoton,npcm845-i2c";
+				reg = <0x80000 0x1000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb0_pins>;
+				syscon = <&gcr>;
+				status = "disabled";
+			};
 		};
 	};
 };

+ 8 - 8
arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi

@@ -220,7 +220,7 @@
 				clocks = <&clk NPCM7XX_CLK_APB1>;
 			};
 			gpio_0: gpio0@10000 {
-                                compatible = "nuvoton,npcm-gpio";
+                                compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio";
                                 reg = <0x10000 0xB0>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
@@ -228,7 +228,7 @@
                         };
 
                         gpio_1: gpio1@11000 {
-                                compatible = "nuvoton,npcm-gpio";
+                                compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio";
                                 reg = <0x11000 0xB0>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
@@ -236,14 +236,14 @@
                         };
 
                         gpio_2: gpio2@12000 {
-                                compatible = "nuvoton,npcm-gpio";
+                                compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio";
                                 reg = <0x12000 0xB0>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 gpio-bank-name = "gpio2";
                         };
 			gpio_3: gpio3@13000 {
-                                compatible = "nuvoton,npcm-gpio";
+                                compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio";
                                 reg = <0x13000 0xB0>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
@@ -251,7 +251,7 @@
                         };
 
                         gpio_4: gpio4@14000 {
-                                compatible = "nuvoton,npcm-gpio";
+                                compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio";
                                 reg = <0x14000 0xB0>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
@@ -259,7 +259,7 @@
                         };
 
                         gpio_5: gpio5@15000 {
-                                compatible = "nuvoton,npcm-gpio";
+                                compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio";
                                 reg = <0x15000 0xB0>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
@@ -267,14 +267,14 @@
                         };
 
                         gpio_6: gpio6@16000 {
-                                compatible = "nuvoton,npcm-gpio";
+                                compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio";
                                 reg = <0x16000 0xB0>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 gpio-bank-name = "gpio6";
                         };
 			gpio_7: gpio7@17000 {
-                                compatible = "nuvoton,npcm-gpio";
+                                compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio";
                                 reg = <0x17000 0xB0>;
                                 #gpio-cells = <2>;
                                 gpio-controller;

+ 129 - 0
arch/arm/dts/nuvoton-npcm845-evb.dts

@@ -3,6 +3,7 @@
 
 /dts-v1/;
 #include "nuvoton-npcm845.dtsi"
+#include "nuvoton-npcm845-pincfg.dtsi"
 
 / {
 	model = "Nuvoton npcm845 Development Board (Device Tree)";
@@ -10,6 +11,15 @@
 
 	aliases {
 		serial0 = &serial0;
+		i2c0 = &i2c0;
+		spi0 = &fiu0;
+		spi1 = &fiu1;
+		spi3 = &fiu3;
+		spi4 = &fiux;
+		spi5 = &spi1;
+		usb0 = &udc0;
+		usb1 = &ehci1;
+		usb2 = &ehci2;
 	};
 
 	chosen {
@@ -19,6 +29,31 @@
 	memory {
 		reg = <0x0 0x0 0x0 0x40000000>;
 	};
+
+	vsbr2: vsbr2 {
+		compatible = "regulator-npcm845";
+		regulator-name = "vr2";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	vsbv8: vsbv8 {
+		compatible = "regulator-npcm845";
+		regulator-name = "v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	vsbv5: vsbv5 {
+		compatible = "regulator-npcm845";
+		regulator-name = "v5";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
 };
 
 &serial0 {
@@ -28,3 +63,97 @@
 &watchdog1 {
 	status = "okay";
 };
+
+&fiu0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0cs1_pins>;
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+	};
+	spi_flash@1 {
+		compatible = "jedec,spi-nor";
+		reg = <1>;
+		spi-max-frequency = <25000000>;
+	};
+};
+
+&fiu1 {
+	status = "okay";
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+	};
+};
+
+&fiu3 {
+	pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
+	status = "okay";
+	vqspi-supply = <&vsbv5>;
+	vqspi-microvolt = <3300000>;
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+	};
+};
+
+&fiux {
+	nuvoton,spix-mode;
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+};
+
+&usbphy1 {
+	status = "okay";
+};
+
+&usbphy2 {
+	status = "okay";
+};
+
+&usbphy3 {
+	status = "okay";
+};
+
+&udc0 {
+	status = "okay";
+	phys = <&usbphy1 0>;
+};
+
+&sdhci0 {
+	bus-width = <0x8>;
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+	phys = <&usbphy2 3>;
+};
+
+&ehci2 {
+	status = "okay";
+	phys = <&usbphy3 4>;
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&pinctrl {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+		&gspi_pins
+		&vgadig_pins
+		&spix_pins
+		&r1_pins
+		&r1en_pins
+		&r1oen_pins
+	>;
+};

+ 2007 - 0
arch/arm/dts/nuvoton-npcm845-pincfg.dtsi

@@ -0,0 +1,2007 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
+
+/ {
+	pinctrl: pinctrl@f0800000 {
+		gpio0o_pins: gpio0o-pins {
+			pins = "GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA";
+			bias-disable;
+			output-high;
+		};
+		gpio1_pins: gpio1-pins {
+			pins = "GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio2_pins: gpio2-pins {
+			pins = "GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio2o_pins: gpio2o-pins {
+			pins = "GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA";
+			bias-disable;
+			output_high;
+		};
+		gpio3_pins: gpio3-pins {
+			pins = "GPIO3/IOX1_DO/SMB6B_SCL/SMB17_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio3o_pins: gpio3o-pins {
+			pins = "GPIO3/IOX1_DO/SMB6B_SCL/SMB17_SCL";
+			bias-disable;
+			output-high;
+		};
+		gpio4_pins: gpio4-pins {
+			pins = "GPIO4/IOX2_DI/SMB1D_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio5_pins: gpio5-pins {
+			pins = "GPIO5/IOX2_LD/SMB1D_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio6_pins: gpio6-pins {
+			pins = "GPIO6/IOX2_CK/SMB2D_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio6o_pins: gpio6o-pins {
+			pins = "GPIO6/IOX2_CK/SMB2D_SDA";
+			bias-disable;
+			output-high;
+		};
+		gpio6ol_pins: gpio6ol-pins {
+			pins = "GPIO6/IOX2_CK/SMB2D_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio7_pins: gpio7-pins {
+			pins = "GPIO7/IOX2_D0/SMB2D_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio7o_pins: gpio7o-pins {
+			pins = "GPIO7/IOX2_D0/SMB2D_SCL";
+			bias-disable;
+			output-high;
+		};
+		gpio7ol_pins: gpio7ol-pins {
+			pins = "GPIO7/IOX2_D0/SMB2D_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio8_pins: gpio8-pins {
+			pins = "GPIO8/LKGPO1/TP_GPIO0";
+			bias-disable;
+			input-enable;
+		};
+		gpio8ol_pins: gpio8ol-pins {
+			pins = "GPIO8/LKGPO1/TP_GPIO0";
+			bias-disable;
+			output-low;
+		};
+		gpio9_pins: gpio9-pins {
+			pins = "GPIO9/LKGPO2/TP_GPIO1";
+			bias-disable;
+			input-enable;
+		};
+		gpio9o_pins: gpio9o-pins {
+			pins = "GPIO9/LKGPO2/TP_GPIO1";
+			bias-disable;
+			output-high;
+		};
+		gpio9ol_pins: gpio9ol-pins {
+			pins = "GPIO9/LKGPO2/TP_GPIO1";
+			bias-disable;
+			output-low;
+		};
+		gpio10_pins: gpio10-pins {
+			pins = "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio10ol_pins: gpio10ol-pins {
+			pins = "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio11_pins: gpio11-pins {
+			pins = "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio11o_pins: gpio11o-pins {
+			pins = "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA";
+			bias-disable;
+			output-high;
+		};
+		gpio11ol_pins: gpio11ol-pins {
+			pins = "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio12_pins: gpio12-pins {
+			pins = "GPIO12/GSPI_CK/SMB5B_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio12o_pins: gpio12o-pins {
+			pins = "GPIO12/GSPI_CK/SMB5B_SCL";
+			bias-disable;
+			output-high;
+		};
+		gpio12ol_pins: gpio12ol-pins {
+			pins = "GPIO12/GSPI_CK/SMB5B_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio13_pins: gpio13-pins {
+			pins = "GPIO13/GSPI_DO/SMB5B_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio13ol_pins: gpio13ol-pins {
+			pins = "GPIO13/GSPI_DO/SMB5B_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio14_pins: gpio14-pins {
+			pins = "GPIO14/GSPI_DI/SMB5C_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio14ol_pins: gpio14ol-pins {
+			pins = "GPIO14/GSPI_DI/SMB5C_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio15_pins: gpio15-pins {
+			pins = "GPIO15/GSPI_CS/SMB5C_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio15o_pins: gpio15o-pins {
+			pins = "GPIO15/GSPI_CS/SMB5C_SDA";
+			bias-disable;
+			output-high;
+		};
+		gpio16_pins: gpio16-pins {
+			pins = "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2";
+			bias-disable;
+			input-enable;
+		};
+		gpio16o_pins: gpio16o-pins {
+			pins = "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2";
+			bias-disable;
+			output-high;
+		};
+		gpio16ol_pins: gpio16ol-pins {
+			pins = "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2";
+			bias-disable;
+			output-low;
+		};
+		gpio17_pins: gpio17-pins {
+			pins = "GPIO17/PSPI_DI/CP1_GPIO5";
+			bias-disable;
+			input-enable;
+		};
+		gpio17o_pins: gpio17o-pins {
+			pins = "GPIO17/PSPI_DI/CP1_GPIO5";
+			bias-disable;
+			output-high;
+		};
+		gpio17ol_pins: gpio17ol-pins {
+			pins = "GPIO17/PSPI_DI/CP1_GPIO5";
+			bias-disable;
+			output-low;
+		};
+		gpio18_pins: gpio18-pins {
+			pins = "GPIO18/PSPI_D0/SMB4B_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio18ol_pins: gpio18ol-pins {
+			pins = "GPIO18/PSPI_D0/SMB4B_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio19_pins: gpio19-pins {
+			pins = "GPIO19/PSPI_CK/SMB4B_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio19ol_pins: gpio19ol-pins {
+			pins = "GPIO19/PSPI_CK/SMB4B_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio20_pins: gpio20-pins {
+			pins = "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio20o_pins: gpio20o-pins {
+			pins = "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA";
+			bias-disable;
+			output-high;
+		};
+		gpio20ol_pins: gpio20ol-pins {
+			pins = "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio21_pins: gpio21-pins {
+			pins = "GPIO21/H_GPIO1/SMB4C_SCL/SMB15_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio21ol_pins: gpio21ol-pins {
+			pins = "GPIO21/H_GPIO1/SMB4C_SCL/SMB15_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio22_pins: gpio22-pins {
+			pins = "GPIO22/H_GPIO2/SMB4D_SDA/SMB14_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio22ol_pins: gpio22ol-pins {
+			pins = "GPIO22/H_GPIO2/SMB4D_SDA/SMB14_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio23_pins: gpio23-pins {
+			pins = "GPIO23/H_GPIO3/SMB4D_SCL/SMB14_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio23ol_pins: gpio23ol-pins {
+			pins = "GPIO23/H_GPIO3/SMB4D_SCL/SMB14_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio24_pins: gpio24-pins {
+			pins = "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio24o_pins: gpio24o-pins {
+			pins = "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL";
+			bias-disable;
+			output-high;
+		};
+		gpio24ol_pins: gpio24ol-pins {
+			pins = "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio25_pins: gpio25-pins {
+			pins = "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio25o_pins: gpio25o-pins {
+			pins = "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA";
+			bias-disable;
+			output-high;
+		};
+		gpio25ol_pins: gpio25ol-pins {
+			pins = "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio26_pins: gpio26-pins {
+			pins = "GPIO26/SMB5_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio27_pins: gpio27-pins {
+			pins = "GPIO27/SMB5_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio32_pins: gpio32-pins {
+			pins = "GPIO32/SMB14_SCL/SPI0_nCS1";
+			bias-disable;
+			input-enable;
+		};
+		gpio32o_pins: gpio32o-pins {
+			pins = "GPIO32/SMB14_SCL/SPI0_nCS1";
+			bias-disable;
+			output-high;
+		};
+		gpio32ol_pins: gpio32ol-pins {
+			pins = "GPIO32/SMB14_SCL/SPI0_nCS1";
+			bias-disable;
+			output-low;
+		};
+		gpio37_pins: gpio37-pins {
+			pins = "GPIO37/SMB3C_SDA/SMB23_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio37o_pins: gpio37o-pins {
+			pins = "GPIO37/SMB3C_SDA/SMB23_SDA";
+			bias-disable;
+			output-high;
+		};
+		gpio37ol_pins: gpio37ol-pins {
+			pins = "GPIO37/SMB3C_SDA/SMB23_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio38_pins: gpio38-pins {
+			pins = "GPIO38/SMB3C_SCL/SMB23_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio38o_pins: gpio38o-pins {
+			pins = "GPIO38/SMB3C_SCL/SMB23_SCL";
+			bias-disable;
+			output-high;
+		};
+		gpio38ol_pins: gpio38ol-pins {
+			pins = "GPIO38/SMB3C_SCL/SMB23_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio39_pins: gpio39-pins {
+			pins = "GPIO39/SMB3B_SDA/SMB22_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio39o_pins: gpio39o-pins {
+			pins = "GPIO39/SMB3B_SDA/SMB22_SDA";
+			bias-disable;
+			output-high;
+		};
+		gpio39ol_pins: gpio39ol-pins {
+			pins = "GPIO39/SMB3B_SDA/SMB22_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio40_pins: gpio40-pins {
+			pins = "GPIO40/SMB3B_SCL/SMB22_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio40o_pins: gpio40o-pins {
+			pins = "GPIO40/SMB3B_SCL/SMB22_SCL";
+			bias-disable;
+			output-high;
+		};
+		gpio40ol_pins: gpio40ol-pins {
+			pins = "GPIO40/SMB3B_SCL/SMB22_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio41_pins: gpio41-pins {
+			pins = "GPIO41/BU0_RXD/CP1U_RXD";
+			input-enable;
+		};
+		gpio42_pins: gpio42-pins {
+			pins = "GPIO42/BU0_TXD/CP1U_TXD";
+			bias-disable;
+			input-enable;
+		};
+		gpio43_pins: gpio43-pins {
+			pins = "GPIO43/SI1_RXD/BU1_RXD";
+			bias-disable;
+			input-enable;
+		};
+		gpio44_pins: gpio44-pins {
+			pins = "GPIO44/SI1_nCTS/BU1_nCTS/CP_TDI/TP_TDI/CP_TP_TDI";
+			bias-disable;
+			input-enable;
+		};
+		gpio45_pins: gpio45-pins {
+			pins = "GPIO45/SI1_nDCD/CP_TMS_SWIO/TP_TMS_SWIO/CP_TP_TMS_SWIO";
+			bias-disable;
+			input-enable;
+		};
+		gpio46_pins: gpio46-pins {
+			pins = "GPIO46/SI1_nDSR/CP_TCK_SWCLK/TP_TCK_SWCLK/CP_TP_TCK_SWCLK";
+			bias-disable;
+			input-enable;
+		};
+		gpio47_pins: gpio47-pins {
+			pins = "GPIO47/SI1n_RI1";
+			bias-disable;
+			input-enable;
+		};
+		gpio48_pins: gpio48-pins {
+			pins = "GPIO48/SI2_TXD/BU0_TXD/STRAP5";
+			bias-disable;
+			input-enable;
+		};
+		gpio49_pins: gpio49-pins {
+			pins = "GPIO49/SI2_RXD/BU0_RXD";
+			bias-disable;
+			input-enable;
+		};
+		gpio50_pins: gpio50-pins {
+			pins = "GPIO50/SI2_nCTS/BU6_TXD/TPU_TXD";
+			bias-disable;
+			input-enable;
+		};
+		gpio50ol_pins: gpio50ol-pins {
+			pins = "GPIO50/SI2_nCTS/BU6_TXD/TPU_TXD";
+			bias-disable;
+			output-low;
+		};
+		gpio51_pins: gpio51-pins {
+			pins = "GPIO51/SI2_nRTS/BU6_RXD/TPU_RXD";
+			bias-disable;
+			input-enable;
+		};
+		gpio51o_pins: gpio51o-pins {
+			pins = "GPIO51/SI2_nRTS/BU6_RXD/TPU_RXD";
+			bias-disable;
+			output-high;
+		};
+		gpio52_pins: gpio52-pins {
+			pins = "GPIO52/SI2_nDCD/BU5_RXD";
+			bias-disable;
+			input-enable;
+		};
+		gpio52ol_pins: gpio52ol-pins {
+			pins = "GPIO52/SI2_nDCD/BU5_RXD";
+			bias-disable;
+			output-low;
+		};
+		gpio53_pins: gpio53-pins {
+			pins = "GPIO53/SI2_nDTR_BOUT2/BU5_TXD";
+			bias-disable;
+			input-enable;
+		};
+		gpio53o_pins: gpio53o-pins {
+			pins = "GPIO53/SI2_nDTR_BOUT2/BU5_TXD";
+			bias-disable;
+			output-high;
+		};
+		gpio54_pins: gpio54-pins {
+			pins = "GPIO54/SI2_nDSR/BU4_TXD";
+			bias-disable;
+			input-enable;
+		};
+		gpio54ol_pins: gpio54ol-pins {
+			pins = "GPIO54/SI2_nDSR/BU4_TXD";
+			bias-disable;
+			output-low;
+		};
+		gpio55_pins: gpio55-pins {
+			pins = "GPIO55/SI2_RI2/BU4_RXD";
+			bias-disable;
+			input-enable;
+		};
+		gpio55ol_pins: gpio55ol-pins {
+			pins = "GPIO55/SI2_RI2/BU4_RXD";
+			bias-disable;
+			output-low;
+		};
+		gpio56_pins: gpio56-pins {
+			pins = "GPIO56/R1_RXERR/R1_OEN";
+			bias-disable;
+			input-enable;
+		};
+		gpio57_pins: gpio57-pins {
+			pins = "GPIO57/R1_MDC/TP_GPIO4";
+			bias-disable;
+			input-enable;
+		};
+		gpio57ol_pins: gpio57ol-pins {
+			pins = "GPIO57/R1_MDC/TP_GPIO4";
+			bias-disable;
+			output-low;
+		};
+		gpio58_pins: gpio58-pins {
+			pins = "GPIO58/R1_MDIO/TP_GPIO5";
+			bias-disable;
+			input-enable;
+		};
+		gpio58ol_pins: gpio58ol-pins {
+			pins = "GPIO58/R1_MDIO/TP_GPIO5";
+			bias-disable;
+			output-low;
+		};
+		gpio59_pins: gpio59-pins {
+			pins = "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio59o_pins: gpio59o-pins {
+			pins = "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA";
+			bias-disable;
+			output-high;
+		};
+		gpio59ol_pins: gpio59ol-pins {
+			pins = "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio60_pins: gpio60-pins {
+			pins = "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio60o_pins: gpio60o-pins {
+			pins = "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL";
+			bias-disable;
+			output-high;
+		};
+		gpio60ol_pins: gpio60ol-pins {
+			pins = "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio61_pins: gpio61-pins {
+			pins = "GPIO61/SI1_nDTR_BOUT";
+			bias-disable;
+			input-enable;
+		};
+		gpio61o_pins: gpio61o-pins {
+			pins = "GPIO61/SI1_nDTR_BOUT";
+			bias-disable;
+			output-high;
+		};
+		gpio62_pins: gpio62-pins {
+			pins = "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO";
+			bias-disable;
+			input-enable;
+		};
+		gpio62o_pins: gpio62o-pins {
+			pins = "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO";
+			bias-disable;
+			output-high;
+		};
+		gpio63_pins: gpio63-pins {
+			pins = "GPIO63/BU1_TXD1/SI1_TXD";
+			bias-disable;
+			input-enable;
+		};
+		gpio63o_pins: gpio63o-pins {
+			pins = "GPIO63/BU1_TXD1/SI1_TXD";
+			bias-disable;
+			output-high;
+		};
+		gpio64_pins: gpio64-pins {
+			pins = "GPIO64/FANIN0";
+			bias-disable;
+			input-enable;
+		};
+		gpio64o_pins: gpio64o-pins {
+			pins = "GPIO64/FANIN0";
+			bias-disable;
+			output-high;
+		};
+		gpio65_pins: gpio65-pins {
+			pins = "GPIO65/FANIN1";
+			bias-disable;
+			input-enable;
+		};
+		gpio66_pins: gpio66-pins {
+			pins = "GPIO66/FANIN2";
+			bias-disable;
+			input-enable;
+		};
+		gpio67_pins: gpio67-pins {
+			pins = "GPIO67/FANIN3";
+			bias-disable;
+			input-enable;
+		};
+		gpio68_pins: gpio68-pins {
+			pins = "GPIO68/FANIN4";
+			bias-disable;
+			input-enable;
+		};
+		gpio68o_pins: gpio68o-pins {
+			pins = "GPIO68/FANIN4";
+			bias-disable;
+			output-high;
+		};
+		gpio69_pins: gpio69-pins {
+			pins = "GPIO69/FANIN5";
+			bias-disable;
+			input-enable;
+		};
+		gpio69o_pins: gpio69o-pins {
+			pins = "GPIO69/FANIN5";
+			bias-disable;
+			output-high;
+		};
+		gpio69ol_pins: gpio69ol-pins {
+			pins = "GPIO69/FANIN5";
+			bias-disable;
+			output-low;
+		};
+		gpio70_pins: gpio70-pins {
+			pins = "GPIO70/FANIN6";
+			bias-disable;
+			input-enable;
+		};
+		gpio70o_pins: gpio70o-pins {
+			pins = "GPIO70/FANIN6";
+			bias-disable;
+			output-high;
+		};
+		gpio71_pins: gpio71-pins {
+			pins = "GPIO71/FANIN7";
+			bias-disable;
+			input-enable;
+		};
+		gpio72_pins: gpio72-pins {
+			pins = "GPIO72/FANIN8";
+			bias-disable;
+			input-enable;
+		};
+		gpio72ol_pins: gpio72ol-pins {
+			pins = "GPIO72/FANIN8";
+			bias-disable;
+			output-low;
+		};
+		gpio73_pins: gpio73-pins {
+			pins = "GPIO73/FANIN9";
+			bias-disable;
+			input-enable;
+		};
+		gpio73ol_pins: gpio73ol-pins {
+			pins = "GPIO73/FANIN9";
+			bias-disable;
+			output-low;
+		};
+		gpio74_pins: gpio74-pins {
+			pins = "GPIO74/FANIN10";
+			bias-disable;
+			input-enable;
+		};
+		gpio74ol_pins: gpio74ol-pins {
+			pins = "GPIO74/FANIN10";
+			bias-disable;
+			output-low;
+		};
+		gpio75_pins: gpio75-pins {
+			pins = "GPIO75/FANIN11";
+			bias-disable;
+			input-enable;
+		};
+		gpio75ol_pins: gpio75ol-pins {
+			pins = "GPIO75/FANIN11";
+			bias-disable;
+			output-low;
+		};
+		gpio76_pins: gpio76-pins {
+			pins = "GPIO76/FANIN12";
+			bias-disable;
+			input-enable;
+		};
+		gpio76ol_pins: gpio76ol-pins {
+			pins = "GPIO76/FANIN12";
+			bias-disable;
+			output-low;
+		};
+		gpio77_pins: gpio77-pins {
+			pins = "GPIO77/FANIN13";
+			bias-disable;
+			input-enable;
+		};
+		gpio77ol_pins: gpio77ol-pins {
+			pins = "GPIO77/FANIN13";
+			bias-disable;
+			output-low;
+		};
+		gpio78_pins: gpio78-pins {
+			pins = "GPIO78/FANIN14";
+			bias-disable;
+			input-enable;
+		};
+		gpio78ol_pins: gpio78ol-pins {
+			pins = "GPIO78/FANIN14";
+			bias-disable;
+			output-low;
+		};
+		gpio79_pins: gpio79-pins {
+			pins = "GPIO79/FANIN15";
+			bias-disable;
+			input-enable;
+		};
+		gpio79ol_pins: gpio79ol-pins {
+			pins = "GPIO79/FANIN15";
+			bias-disable;
+			output-low;
+		};
+		gpio80_pins: gpio80-pins {
+			pins = "GPIO80/PWM0";
+			bias-disable;
+			input-enable;
+		};
+		gpio81_pins: gpio81-pins {
+			pins = "GPIO81/PWM1";
+			bias-disable;
+			input-enable;
+		};
+		gpio82_pins: gpio82-pins {
+			pins = "GPIO82/PWM2";
+			bias-disable;
+			input-enable;
+		};
+		gpio83_pins: gpio83-pins {
+			pins = "GPIO83/PWM3";
+			bias-disable;
+			input-enable;
+		};
+		gpio84_pins: gpio84-pins {
+			pins = "GPIO84/R2_TXD0";
+			bias-disable;
+			input-enable;
+		};
+		gpio84o_pins: gpio84ol-pins {
+			pins = "GPIO84/R2_TXD0";
+			bias-disable;
+			output-high;
+		};
+		gpio85_pins: gpio85-pins {
+			pins = "GPIO85/R2_TXD1";
+			bias-disable;
+			input-enable;
+		};
+		gpio85o_pins: gpio85o-pins {
+			pins = "GPIO85/R2_TXD1";
+			bias-disable;
+			output-high;
+		};
+		gpio86_pins: gpio86-pins {
+			pins = "GPIO86/R2_TXEN";
+			bias-disable;
+			input-enable;
+		};
+		gpio86o_pins: gpio86o-pins {
+			pins = "GPIO86/R2_TXEN";
+			bias-disable;
+			output-high;
+		};
+		gpio87_pins: gpio87-pins {
+			pins = "GPIO87/R2_RXD0";
+			bias-disable;
+			input-enable;
+		};
+		gpio87o_pins: gpio87o-pins {
+			pins = "GPIO87/R2_RXD0";
+			bias-disable;
+			output-high;
+		};
+		gpio88_pins: gpio88-pins {
+			pins = "GPIO88/R2_RXD1";
+			bias-disable;
+			input-enable;
+		};
+		gpio88ol_pins: gpio88ol-pins {
+			pins = "GPIO88/R2_RXD1";
+			bias-disable;
+			output-low;
+		};
+		gpio89_pins: gpio89-pins {
+			pins = "GPIO89/R2_CRSDV";
+			bias-disable;
+			input-enable;
+		};
+		gpio89ol_pins: gpio89ol-pins {
+			pins = "GPIO89/R2_CRSDV";
+			bias-disable;
+			output-low;
+		};
+		gpio90_pins: gpio90-pins {
+			pins = "GPIO90/R2_RXERR/R2_OEN";
+			bias-disable;
+			input-enable;
+		};
+		gpio90o_pins: gpio90o0-pins {
+			pins = "GPIO90/R2_RXERR/R2_OEN";
+			bias-disable;
+			output-high;
+		};
+		gpio90ol_pins: gpio90ol-pins {
+			pins = "GPIO90/R2_RXERR/R2_OEN";
+			bias-disable;
+			output-low;
+		};
+		gpio91_pins: gpio91-pins {
+			pins = "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0";
+			bias-disable;
+			input-enable;
+		};
+		gpio91o_pins: gpio91o-pins {
+			pins = "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0";
+			bias-disable;
+			output-high;
+		};
+		gpio91ol_pins: gpio91ol-pins {
+			pins = "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0";
+			bias-disable;
+			output-low;
+		};
+		gpio92_pins: gpio92-pins {
+			pins = "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1";
+			bias-disable;
+			input-enable;
+		};
+		gpio92o_pins: gpio92o-pins {
+			pins = "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1";
+			bias-disable;
+			output-high;
+		};
+		gpio92ol_pins: gpio92ol-pins {
+			pins = "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1";
+			bias-disable;
+			output-low;
+		};
+		gpio93_pins: gpio93-pins {
+			pins = "GPIO93/GA20/SMB5D_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio93o_pins: gpio93o-pins {
+			pins = "GPIO93/GA20/SMB5D_SCL";
+			bias-disable;
+			output-high;
+		};
+		gpio93ol_pins: gpio93ol-pins {
+			pins = "GPIO93/GA20/SMB5D_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio94_pins: gpio94-pins {
+			pins = "GPIO94/nKBRST/SMB5D_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio94o_pins: gpio94o-pins {
+			pins = "GPIO94/nKBRST/SMB5D_SDA";
+			bias-disable;
+			output-high;
+		};
+		gpio95_pins: gpio95-pins {
+			pins = "GPIO95/nESPIRST/LPC_nLRESET";
+			bias-disable;
+			input-enable;
+		};
+		gpio96_pins: gpio96-pins {
+			pins = "GPIO96/CP1_GPIO7/BU2_TXD/TP_GPIO7";
+			bias-disable;
+			input-enable;
+		};
+		gpio96ol_pins: gpio96ol-pins {
+			pins = "GPIO96/CP1_GPIO7/BU2_TXD/TP_GPIO7";
+			bias-disable;
+			output-low;
+		};
+		gpio97_pins: gpio97-pins {
+			pins = "GPIO97/CP1_GPIO6/BU2_RXD/TP_GPIO6";
+			bias-disable;
+			input-enable;
+		};
+		gpio97ol_pins: gpio97ol-pins {
+			pins = "GPIO97/CP1_GPIO6/BU2_RXD/TP_GPIO6";
+			bias-disable;
+			output-low;
+		};
+		gpio98_pins: gpio98-pins {
+			pins = "GPIO98/CP1_GPIO5/BU4_TXD/TP_GPIO5";
+			bias-disable;
+			input-enable;
+		};
+		gpio98o_pins: gpio98o-pins {
+			pins = "GPIO98/RG1TXD2";
+			bias-disable;
+			output-high;
+		};
+		gpio98ol_pins: gpio98ol-pins {
+			pins = "GPIO98/CP1_GPIO5/BU4_TXD/TP_GPIO5";
+			bias-disable;
+			output-low;
+		};
+		gpio99_pins: gpio99-pins {
+			pins = "GPIO99/CP1_GPIO4/BU4_RXD/TP_GPIO4";
+			bias-disable;
+			input-enable;
+		};
+		gpio99o_pins: gpio99o-pins {
+			pins = "GPIO99/RG1TXD3";
+			bias-disable;
+			output-high;
+		};
+		gpio99ol_pins: gpio99ol-pins {
+			pins = "GPIO99/CP1_GPIO4/BU4_RXD/TP_GPIO4";
+			bias-disable;
+			output-low;
+		};
+		gpio100_pins: gpio100-pins {
+			pins = "GPIO100/CP1_GPIO3/BU5_TXD/TP_GPIO3";
+			bias-disable;
+			input-enable;
+		};
+		gpio100ol_pins: gpio100ol-pins {
+			pins = "GPIO100/CP1_GPIO3/BU5_TXD/TP_GPIO3";
+			bias-disable;
+			output-low;
+		};
+		gpio101_pins: gpio101-pins {
+			pins = "GPIO101/CP1_GPIO2/BU5_RXD/TP_GPIO2";
+			bias-disable;
+			input-enable;
+		};
+		gpio101ol_pins: gpio101ol-pins {
+			pins = "GPIO101/CP1_GPIO2/BU5_RXD/TP_GPIO2";
+			bias-disable;
+			output-low;
+		};
+		gpio102_pins: gpio102-pins {
+			pins = "GPIO102/HSYNC";
+			bias-disable;
+			input-enable;
+		};
+		gpio102ol_pins: gpio102ol-pins {
+			pins = "GPIO102/HSYNC";
+			bias-disable;
+			output-low;
+		};
+		gpio103_pins: gpio103-pins {
+			pins = "GPIO103/VSYNC";
+			bias-disable;
+			input-enable;
+		};
+		gpio103ol_pins: gpio103ol-pins {
+			pins = "GPIO103/VSYNC";
+			bias-disable;
+			output-low;
+		};
+		gpio104_pins: gpio104-pins {
+			pins = "GPIO104/DDC_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio104ol_pins: gpio104ol-pins {
+			pins = "GPIO104/DDC_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio105_pins: gpio105-pins {
+			pins = "GPIO105/DDC_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio105ol_pins: gpio105ol-pins {
+			pins = "GPIO105/DDC_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio106_pins: gpio106-pins {
+			pins = "GPIO106/I3C5_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio106ol_pins: gpio106ol-pins {
+			pins = "GPIO106/I3C5_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio107_pins: gpio107-pins {
+			pins = "GPIO107/I3C5_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio107ol_pins: gpio107ol-pins {
+			pins = "GPIO107/I3C5_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio108_pins: gpio108-pins {
+			pins = "GPIO108/SG1_MDC";
+			bias-disable;
+			input-enable;
+		};
+		gpio108ol_pins: gpio108ol-pins {
+			pins = "GPIO108/SG1_MDC";
+			bias-disable;
+			output-low;
+		};
+		gpio109_pins: gpio109-pins {
+			pins = "GPIO109/SG1_MDIO";
+			bias-disable;
+			input-enable;
+		};
+		gpio109ol_pins: gpio109ol-pins {
+			pins = "GPIO109/SG1_MDIO";
+			bias-disable;
+			output-low;
+		};
+		gpio110_pins: gpio110-pins {
+			pins = "GPIO110/RG2_TXD0/DDRV0/R3_TXD0";
+			bias-disable;
+			input-enable;
+		};
+		gpio110ol_pins: gpio110ol-pins {
+			pins = "GPIO110/RG2_TXD0/DDRV0/R3_TXD0";
+			bias-disable;
+			output-low;
+		};
+		gpio111_pins: gpio111-pins {
+			pins = "GPIO111/RG2_TXD1/DDRV1/R3_TXD1";
+			bias-disable;
+			input-enable;
+		};
+		gpio111ol_pins: gpio111ol-pins {
+			pins = "GPIO111/RG2_TXD1/DDRV1/R3_TXD1";
+			bias-disable;
+			output-low;
+		};
+		gpio112_pins: gpio112-pins {
+			pins = "GPIO112/RG2_TXD2/DDRV2";
+			bias-disable;
+			input-enable;
+		};
+		gpio112ol_pins: gpio112ol-pins {
+			pins = "GPIO112/RG2_TXD2/DDRV2";
+			bias-disable;
+			output-low;
+		};
+		gpio113_pins: gpio113-pins {
+			pins = "GPIO113/RG2_TXD3/DDRV3";
+			bias-disable;
+			input-enable;
+		};
+		gpio113ol_pins: gpio113ol-pins {
+			pins = "GPIO113/RG2_TXD3/DDRV3";
+			bias-disable;
+			output-low;
+		};
+		gpio118_pins: gpio118-pins {
+			pins = "GPIO118/SMB2_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio119_pins: gpio119-pins {
+			pins = "GPIO119/SMB2_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio120_pins: gpio120-pins {
+			pins = "GPIO120/SMB2C_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio120ol_pins: gpio120ol-pins {
+			pins = "GPIO120/SMB2C_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio121_pins: gpio121-pins {
+			pins = "GPIO121/SMB2C_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio122_pins: gpio122-pins {
+			pins = "GPIO122/SMB2B_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio123_pins: gpio123-pins {
+			pins = "GPIO123/SMB2B_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio123_pins: gpio123-pins {
+			pins = "GPIO123/SMB2B_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio124_pins: gpio124-pins {
+			pins = "GPIO124/SMB1C_SDA/CP1_GPIO3";
+			bias-disable;
+			input-enable;
+		};
+		gpio125_pins: gpio125-pins {
+			pins = "GPIO125/SMB1C_SCL/CP1_GPIO2";
+			bias-disable;
+			input-enable;
+		};
+		gpio126_pins: gpio126-pins {
+			pins = "GPIO126/SMB1B_SDA/CP1_GPIO1";
+			bias-disable;
+			input-enable;
+		};
+		gpio127_pins: gpio127-pins {
+			pins = "GPIO127/SMB1B_SCL/CP1_GPIO0";
+			bias-disable;
+			input-enable;
+		};
+		gpio128o_pins: gpio128o-pins {
+			pins = "GPIO128/SMB824_SCL";
+			bias-disable;
+			output-high;
+		};
+		gpio130_pins: gpio130-pins {
+			pins = "GPIO130/SMB925_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio131_pins: gpio131-pins {
+			pins = "GPIO131/SMB925_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio132_pins: gpio132-pins {
+			pins = "GPIO132/SMB1026_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio133_pins: gpio133-pins {
+			pins = "GPIO133/SMB1026_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio134_pins: gpio134-pins {
+			pins = "GPIO134/SMB11_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio135_pins: gpio135-pins {
+			pins = "GPIO135/SMB11_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio136_pins: gpio136-pins {
+			pins = "GPIO136/JM1_TCK";
+			bias-disable;
+			input-enable;
+		};
+		gpio136o_pins: gpio136o-pins {
+			pins = "GPIO136/JM1_TCK";
+			bias-disable;
+			output-high;
+		};
+		gpio137_pins: gpio137-pins {
+			pins = "GPIO137/JM1_TDO";
+			bias-disable;
+			input-enable;
+		};
+		gpio137o_pins: gpio137o-pins {
+			pins = "GPIO137/JM1_TDO";
+			bias-disable;
+			output-high;
+		};
+		gpio138_pins: gpio138-pins {
+			pins = "GPIO138/JM1_TMS";
+			bias-disable;
+			input-enable;
+		};
+		gpio138o_pins: gpio138o-pins {
+			pins = "GPIO138/JM1_TMS";
+			bias-disable;
+			output-high;
+		};
+		gpio139_pins: gpio139-pins {
+			pins = "GPIO139/JM1_TDI";
+			bias-disable;
+			input-enable;
+		};
+		gpio139o_pins: gpio139o-pins {
+			pins = "GPIO139/JM1_TDI";
+			bias-disable;
+			output-high;
+		};
+		gpio140_pins: gpio140-pins {
+			pins = "GPIO140/JM1_nTRST";
+			bias-disable;
+			input-enable;
+		};
+		gpio140o_pins: gpio140o-pins {
+			pins = "GPIO140/JM1_nTRST";
+			bias-disable;
+			output-high;
+		};
+		gpio141_pins: gpio141-pins {
+			pins = "GPIO141/SMB7B_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio141o_pins: gpio141o-pins {
+			pins = "GPIO141/SMB7B_SCL";
+			bias-disable;
+			output-high;
+		};
+		gpio141ol_pins: gpio141ol-pins {
+			pins = "GPIO141/SMB7B_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio142_pins: gpio142-pins {
+			pins = "GPIO142/SMB7D_SCL/TPSMB1_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio142o_pins: gpio142o-pins {
+			pins = "GPIO142/SMB7D_SCL/TPSMB1_SCL";
+			bias-disable;
+			output-high;
+		};
+		gpio143_pins: gpio143-pins {
+			pins = "GPIO143/SMB7D_SDA/TPSMB1_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio143o_pins: gpio143o-pins {
+			pins = "GPIO143/SMB7D_SDA/TPSMB1_SDA";
+			bias-disable;
+			output-high;
+		};
+		gpio143ol_pins: gpio143ol-pins {
+			pins = "GPIO143/SMB7D_SDA/TPSMB1_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio144_pins: gpio144-pins {
+			pins = "GPIO144/PWM4";
+			bias-disable;
+			input-enable;
+		};
+		gpio145_pins: gpio145-pins {
+			pins = "GPIO145/PWM5";
+			bias-disable;
+			input-enable;
+		};
+		gpio146_pins: gpio146-pins {
+			pins = "GPIO146/PWM6";
+			bias-disable;
+			input-enable;
+		};
+		gpio147_pins: gpio147-pins {
+			pins = "GPIO147/PWM7";
+			bias-disable;
+			input-enable;
+		};
+		gpio148_pins: gpio148-pins {
+			pins = "GPIO148/MMC_DT4";
+			bias-disable;
+			input-enable;
+		};
+		gpio148o_pins: gpio148o-pins {
+			pins = "GPIO148/MMC_DT4";
+			bias-disable;
+			output-high;
+		};
+		gpio148ol_pins: gpio148ol_pins {
+			pins = "GPIO148/MMC_DT4";
+			bias-disable;
+			output-low;
+		};
+		gpio149_pins: gpio149-pins {
+			pins = "GPIO149/MMC_DT5";
+			bias-disable;
+			input-enable;
+		};
+		gpio149o_pins: gpio149o-pins {
+			pins = "GPIO149/MMC_DT5";
+			bias-disable;
+			output-high;
+		};
+		gpio149ol_pins: gpio149ol-pins {
+			pins = "GPIO149/MMC_DT5";
+			bias-disable;
+			output-low;
+		};
+		gpio150_pins: gpio150-pins {
+			pins = "GPIO150/MMC_DT6";
+			bias-disable;
+			input-enable;
+		};
+		gpio150o_pins: gpio150o-pins {
+			pins = "GPIO150/MMC_DT6";
+			bias-disable;
+			output-high;
+		};
+		gpio150ol_pins: gpio150ol-pins {
+			pins = "GPIO150/MMC_DT6";
+			bias-disable;
+			output-low;
+		};
+		gpio151_pins: gpio151-pins {
+			pins = "GPIO151/MMC_DT7";
+			bias-disable;
+			input-enable;
+		};
+		gpio151o_pins: gpio151o-pins {
+			pins = "GPIO151/MMC_DT7";
+			bias-disable;
+			output-high;
+		};
+		gpio151ol_pins: gpio151ol-pins {
+			pins = "GPIO151/MMC_DT7";
+			bias-disable;
+			output-low;
+		};
+		gpio152_pins: gpio152-pins {
+			pins = "GPIO152/MMC_CLK";
+			bias-disable;
+			input-enable;
+		};
+		gpio152o_pins: gpio152o-pins {
+			pins = "GPIO152/MMC_CLK";
+			bias-disable;
+			output-high;
+		};
+		gpio152ol_pins: gpio152ol-pins {
+			pins = "GPIO152/MMC_CLK";
+			bias-disable;
+			output-low;
+		};
+		gpio153_pins: gpio153-pins {
+			pins = "GPIO153/MMC_WP";
+			bias-disable;
+			input-enable;
+		};
+		gpio153ol_pins: gpio153ol-pins {
+			pins = "GPIO153/MMC_WP";
+			bias-disable;
+			output-low;
+		};
+		gpio154_pins: gpio154-pins {
+			pins = "GPIO154/MMC_CMD";
+			bias-disable;
+			input-enable;
+		};
+		gpio154ol_pins: gpio154ol-pins {
+			pins = "GPIO154/MMC_CMD";
+			bias-disable;
+			output-low;
+		};
+		gpio155_pins: gpio155-pins {
+			pins = "GPIO155/MMC_nCD/MMC_nRSTLK";
+			bias-disable;
+			input-enable;
+		};
+		gpio155ol_pins: gpio155ol-pins {
+			pins = "GPIO155/MMC_nCD/MMC_nRSTLK";
+			bias-disable;
+			output-low;
+		};
+		gpio156_pins: gpio156-pins {
+			pins = "GPIO156/MMC_DT0";
+			bias-disable;
+			input-enable;
+		};
+		gpio156ol_pins: gpio156ol-pins {
+			pins = "GPIO156/MMC_DT0";
+			bias-disable;
+			output-low;
+		};
+		gpio157_pins: gpio157-pins {
+			pins = "GPIO157/MMC_DT1";
+			bias-disable;
+			input-enable;
+		};
+		gpio157o_pins: gpio157o-pins {
+			pins = "GPIO157/MMC_DT1";
+			bias-disable;
+			output-high;
+		};
+		gpio157ol_pins: gpio157ol-pins {
+			pins = "GPIO157/MMC_DT1";
+			bias-disable;
+			output-low;
+		};
+		gpio158_pins: gpio158-pins {
+			pins = "GPIO158/MMC_DT2";
+			bias-disable;
+			input-enable;
+		};
+		gpio158o_pins: gpio158o-pins {
+			pins = "GPIO158/MMC_DT2";
+			bias-disable;
+			output-high;
+		};
+		gpio158ol_pins: gpio158ol-pins {
+			pins = "GPIO158/MMC_DT2";
+			bias-disable;
+			output-low;
+		};
+		gpio159_pins: gpio159-pins {
+			pins = "GPIO159/MMC_DT3";
+			bias-disable;
+			input-enable;
+		};
+		gpio159o_pins: gpio159o-pins {
+			pins = "GPIO159/MMC_DT3";
+			bias-disable;
+			output-high;
+		};
+		gpio159ol_pins: gpio159ol-pins {
+			pins = "GPIO159/MMC_DT3";
+			bias-disable;
+			output-low;
+		};
+		gpio160_pins: gpio160-pins {
+			pins = "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK";
+			bias-disable;
+			input-enable;
+		};
+		gpio160o_pins: gpio160o-pins {
+			pins = "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK";
+			bias-disable;
+			output-high;
+		};
+		gpio160ol_pins: gpio160ol-pins {
+			pins = "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK";
+			bias-disable;
+			output-low;
+		};
+		gpio161_pins: gpio161-pins {
+			pins = "GPIO161/ESPI_nCS/LPC_nLFRAME";
+			bias-disable;
+			input-enable;
+		};
+		gpio162_pins: gpio162-pins {
+			pins = "GPIO162/LPC_nCLKRUN";
+			bias-disable;
+			input-enable;
+		};
+		gpio162o_pins: gpio162o-pins {
+			pins = "GPIO162/LPC_nCLKRUN";
+			bias-disable;
+			output-high;
+		};
+		gpio163_pins: gpio163-pins {
+			pins = "GPIO163/ESPI_CK/LPC_LCLK";
+			bias-disable;
+			input-enable;
+		};
+		gpio164_pins: gpio164-pins {
+			pins = "GPIO164/ESPI_IO0/LPC_LAD0";
+			bias-disable;
+			input-enable;
+		};
+		gpio165_pins: gpio165-pins {
+			pins = "GPIO165/ESPI_IO1/LPC_LAD1";
+			bias-disable;
+			input-enable;
+		};
+		gpio166_pins: gpio166-pins {
+			pins = "GPIO166/ESPI_IO2/LPC_LAD2";
+			bias-disable;
+			input-enable;
+		};
+		gpio167_pins: gpio167-pins {
+			pins = "GPIO167/ESPI_IO3/LPC_LAD3";
+			bias-disable;
+			input-enable;
+		};
+		gpio168_pins: gpio168-pins {
+			pins = "GPIO168/ESPI_nALERT/SERIRQ";
+			bias-disable;
+			input-enable;
+			drive-open-drain;
+		};
+		gpio168ol_pins: gpio168ol-pins {
+			pins = "GPIO168/ESPI_nALERT/SERIRQ";
+			bias-disable;
+			output-low;
+		};
+		gpio169_pins: gpio169-pins {
+			pins = "GPIO169/nSCIPME/SMB21_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio169o_pins: gpio169o-pins {
+			pins = "GPIO169/nSCIPME/SMB21_SCL";
+			bias-disable;
+			output-high;
+		};
+		gpio169ol_pins: gpio169ol-pins {
+			pins = "GPIO169/nSCIPME/SMB21_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio170_pins: gpio170-pins {
+			pins = "GPIO170/nSMI/SMB21_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio170ol_pins: gpio170ol-pins {
+			pins = "GPIO170/nSMI/SMB21_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio173o_pins: gpio173o-pins {
+			pins = "GPIO173/SMB7_SCL";
+			bias-disable;
+			output-high;
+		};
+		gpio173ol_pins: gpio173ol-pins {
+			pins = "GPIO173/SMB7_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio174_pins: gpio174-pins {
+			pins = "GPIO174/SMB7_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio175_pins: gpio175-pins {
+			pins = "GPIO175/SPI1_CK/FANIN19/FM1_CK";
+			bias-disable;
+			input-enable;
+		};
+		gpio175o_pins: gpio175o-pins {
+			pins = "GPIO175/SPI1_CK/FANIN19/FM1_CK";
+			bias-disable;
+			output-high;
+		};
+		gpio175ol_pins: gpio175ol-pins {
+			pins = "GPIO175/SPI1_CK/FANIN19/FM1_CK";
+			bias-disable;
+			output-low;
+		};
+		gpio176_pins: gpio176-pins {
+			pins = "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9";
+			bias-disable;
+			input-enable;
+		};
+		gpio176o_pins: gpio176o-pins {
+			pins = "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9";
+			bias-disable;
+			output-high;
+		};
+		gpio176ol_pins: gpio176ol-pins {
+			pins = "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9";
+			bias-disable;
+			output-low;
+		};
+		gpio177_pins: gpio177-pins {
+			pins = "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10";
+			bias-disable;
+			input-enable;
+		};
+		gpio177o_pins: gpio177o-pins {
+			pins = "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10";
+			bias-disable;
+			output-high;
+		};
+		gpio177ol_pins: gpio177ol-pins {
+			pins = "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10";
+			bias-disable;
+			output-low;
+		};
+		gpio187_pins: gpio187-pins {
+			pins = "GPIO187/SPI3_nCS1_SMB14_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio187o_pins: gpio187o-pins {
+			pins = "GPIO187/SPI3_nCS1_SMB14_SDA";
+			bias-disable;
+			output-high;
+		};
+		gpio187ol_pins: gpio187ol-pins {
+			pins = "GPIO187/SPI3_nCS1_SMB14_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio188_pins: gpio188-pins {
+			pins = "GPIO188/SPI3_D2/SPI3_nCS2";
+			bias-disable;
+			input-enable;
+		};
+		gpio188o_pins: gpio188o-pins {
+			pins = "GPIO188/SPI3_D2/SPI3_nCS2";
+			bias-disable;
+			output-high;
+		};
+		gpio189o_pins: gpio189o-pins {
+			pins = "GPIO189/SPI3_D3/SPI3_nCS3";
+			bias-disable;
+			output-high;
+		};
+		gpio190_pins: gpio190-pins {
+			pins = "GPIO190/nPRD_SMI";
+			bias-disable;
+			input-enable;
+		};
+		gpio190o_pins: gpio190o-pins {
+			pins = "GPIO190/nPRD_SMI";
+			bias-disable;
+			output-high;
+		};
+		gpio190ol_pins: gpio190ol-pins {
+			pins = "GPIO190/nPRD_SMI";
+			bias-disable;
+			output-low;
+		};
+		gpio191o_pins: gpio191o-pins {
+			pins = "GPIO191/SPI1_D1/FANIN17/FM1_D1/STRAP10";
+			bias-disable;
+			output-high;
+		};
+		gpio191ol_pins: gpio191ol-pins {
+			pins = "GPIO191/SPI1_D1/FANIN17/FM1_D1/STRAP10";
+			bias-disable;
+			output-low;
+		};
+		gpio192_pins: gpio192-pins {
+			pins = "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio192o_pins: gpio192o-pins {
+			pins = "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL";
+			bias-disable;
+			output-high;
+		};
+		gpio192ol_pins: gpio192ol-pins {
+			pins = "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio194_pins: gpio194-pins {
+			pins = "GPIO194/SMB0B_SCL/FM0_CK";
+			bias-disable;
+			input-enable;
+		};
+		gpio194o_pins: gpio194o-pins {
+			pins = "GPIO194/SMB0B_SCL/FM0_CK";
+			bias-disable;
+			output-high;
+		};
+		gpio195_pins: gpio195-pins {
+			pins = "GPIO195/SMB0B_SDA/FM0_D0";
+			bias-disable;
+			input-enable;
+		};
+		gpio196_pins: gpio196-pins {
+			pins = "GPIO196/SMB0C_SCL/FM0_D1";
+			bias-disable;
+			input-enable;
+		};
+		gpio196o_pins: gpio196o-pins {
+			pins = "GPIO196/SMB0C_SCL/FM0_D1";
+			bias-disable;
+			output-high;
+		};
+		gpio197_pins: gpio197-pins {
+			pins = "GPIO197/SMB0DEN/FM0_D3";
+			bias-disable;
+			input-enable;
+		};
+		gpio197o_pins: gpio197o-pins {
+			pins = "GPIO197/SMB0DEN/FM0_D3";
+			bias-disable;
+			output-high;
+		};
+		gpio197ol_pins: gpio197ol-pins {
+			pins = "GPIO197/SMB0DEN/FM0_D3";
+			bias-disable;
+			output-low;
+		};
+		gpio198o_pins: gpio198o-pins {
+			pins = "GPIO198/SMB0D_SDA/FM0_D2";
+			bias-disable;
+			output-high;
+		};
+		gpio198ol_pins: gpio198ol-pins {
+			pins = "GPIO198/SMB0D_SDA/FM0_D2";
+			bias-disable;
+			output-low;
+		};
+		gpio199_pins: gpio199-pins {
+			pins = "GPIO199/SMB0D_SCL/FM0_CSO";
+			bias-disable;
+			input-enable;
+		};
+		gpio200_pins: gpio200-pins {
+			pins = "GPIO200/R2_CK";
+			input-enable;
+			bias-disable;
+		};
+		gpio200ol_pins: gpio200ol-pins {
+			pins = "GPIO200/R2_CK";
+			bias-disable;
+			output-low;
+		};
+		gpio201ol_pins: gpio201ol-pins {
+			pins = "GPIO201/R1_CK";
+			bias-disable;
+			output-low;
+		};
+		gpio202_pins: gpio202-pins {
+			pins = "GPIO202/SMB0C_SDA/FM0_CSI";
+			bias-disable;
+			input-enable;
+		};
+		gpio203_pins: gpio203-pins {
+			pins = "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI";
+			bias-disable;
+			input-enable;
+		};
+		gpio203o_pins: gpio203o-pins {
+			pins = "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI";
+			bias-disable;
+			output-high;
+		};
+		gpio203ol_pins: gpio203ol-pins {
+			pins = "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI";
+			bias-disable;
+			output-low;
+		};
+		gpio208_pins: gpio208-pins {
+			pins = "GPIO208/RG2_TXC/DVCK";
+			bias-disable;
+			input-enable;
+		};
+		gpio208o_pins: gpio208o-pins {
+			pins = "GPIO208/RG2_TXC/DVCK";
+			bias-disable;
+			output-high;
+		};
+		gpio208ol_pins: gpio208ol-pins {
+			pins = "GPIO208/RG2_TXC/DVCK";
+			bias-disable;
+			output-low;
+		};
+		gpio209_pins: gpio209-pins {
+			pins = "GPIO209/RG2_TXCTL/DDRV4/R3_TXEN";
+			bias-disable;
+			input-enable;
+		};
+		gpio209ol_pins: gpio209ol-pins {
+			pins = "GPIO209/RG2_TXCTL/DDRV4/R3_TXEN";
+			bias-disable;
+			output-low;
+		};
+		gpio210_pins: gpio210-pins {
+			pins = "GPIO210/RG2_RXD0/DDRV5/R3_RXD0";
+			bias-disable;
+			input-enable;
+		};
+		gpio210o_pins: gpio210o-pins {
+			pins = "GPIO210/RG2_RXD0/DDRV5/R3_RXD0";
+			bias-disable;
+			output-high;
+		};
+		gpio210ol_pins: gpio210ol-pins {
+			pins = "GPIO210/RG2_RXD0/DDRV5/R3_RXD0";
+			bias-disable;
+			output-low;
+		};
+		gpio211_pins: gpio211-pins {
+			pins = "GPIO211/RG2_RXD1/DDRV6/R3_RXD1";
+			bias-disable;
+			input-enable;
+		};
+		gpio211o_pins: gpio211o-pins {
+			pins = "GPIO211/RG2_RXD1/DDRV6/R3_RXD1";
+			bias-disable;
+			output-high;
+		};
+		gpio211ol_pins: gpio211ol-pins {
+			pins = "GPIO211/RG2_RXD1/DDRV6/R3_RXD1";
+			bias-disable;
+			output-low;
+		};
+		gpio212_pins: gpio212-pins {
+			pins = "GPIO212/RG2_RXD2/DDRV7/R3_RXD2";
+			bias-disable;
+			input-enable;
+		};
+		gpio212o_pins: gpio212o-pins {
+			pins = "GPIO212/RG2_RXD2/DDRV7/R3_RXD2";
+			bias-disable;
+			output-high;
+		};
+		gpio212ol_pins: gpio212ol-pins {
+			pins = "GPIO212/RG2_RXD2/DDRV7/R3_RXD2";
+			bias-disable;
+			output-low;
+		};
+		gpio213_pins: gpio213-pins {
+			pins = "GPIO213/RG2_RXD3/DDRV8/R3_OEN";
+			bias-disable;
+			input-enable;
+		};
+		gpio213o_pins: gpio213o-pins {
+			pins = "GPIO213/RG2_RXD3/DDRV8/R3_OEN";
+			bias-disable;
+			output-high;
+		};
+		gpio213ol_pins: gpio213ol-pins {
+			pins = "GPIO213/RG2_RXD3/DDRV8/R3_OEN";
+			bias-disable;
+			output-low;
+		};
+		gpio214_pins: gpio214-pins {
+			pins = "GPIO214/RG2_RXC/DDRV9/R3_CK";
+			bias-disable;
+			input-enable;
+		};
+		gpio214ol_pins: gpio214ol-pins {
+			pins = "GPIO214/RG2_RXC/DDRV9/R3_CK";
+			bias-disable;
+			output-low;
+		};
+		gpio215_pins: gpio215-pins {
+			pins = "GPIO215/RG2_RXCTL/DDRV10/R3_CRSDV";
+			bias-disable;
+			input-enable;
+		};
+		gpio215ol_pins: gpio215ol-pins {
+			pins = "GPIO215/RG2_RXCTL/DDRV10/R3_CRSDV";
+			bias-disable;
+			output-low;
+		};
+		gpio216_pins: gpio216-pins {
+			pins = "GPIO216/RG2_MDC/DDRV11";
+			bias-disable;
+			input-enable;
+		};
+		gpio216ol_pins: gpio216ol-pins {
+			pins = "GPIO216/RG2_MDC/DDRV11";
+			bias-disable;
+			output-low;
+		};
+		gpio217_pins: gpio217-pins {
+			pins = "GPIO217/RG2_MDIO/DVHSYNC";
+			bias-disable;
+			input-enable;
+		};
+		gpio217ol_pins: gpio217ol-pins {
+			pins = "GPIO217/RG2_MDIO/DVHSYNC";
+			bias-disable;
+			output-low;
+		};
+		gpio218_pins: gpio218-pins {
+			pins = "GPIO218/nWDO1/SMB16_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio218ol_pins: gpio218ol-pins {
+			pins = "GPIO218/nWDO1/SMB16_SCL";
+			bias-disable;
+			output-low;
+		};
+		gpio219_pins: gpio219-pins {
+			pins = "GPIO219/nWDO2/SMB16_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio219ol_pins: gpio219ol-pins {
+			pins = "GPIO219/nWDO2/SMB16_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio220ol_pins: gpio220ol-pins {
+			pins = "GPIO220/SMB12_SCL/PWM8";
+			bias-disable;
+			output-low;
+		};
+		gpio221o_pins: gpio221o-pins {
+			pins = "GPIO221/SMB12_SDA/PWM9";
+			bias-disable;
+			output-high;
+		};
+		gpio222_pins: gpio222-pins {
+			pins = "GPIO222/SMB13_SCL";
+			bias-disable;
+			input-enable;
+		};
+		gpio222o_pins: gpio222o-pins {
+			pins = "GPIO222/SMB13_SCL";
+			bias-disable;
+			output-high;
+		};
+		gpio223_pins: gpio223-pins {
+			pins = "GPIO223/SMB13_SDA";
+			bias-disable;
+			input-enable;
+		};
+		gpio223ol_pins: gpio223ol-pins {
+			pins = "GPIO223/SMB13_SDA";
+			bias-disable;
+			output-low;
+		};
+		gpio224_pins: gpio224-pins {
+			pins = "GPIO224/SPIX_CK/FM2_CK";
+			bias-disable;
+			input-enable;
+		};
+		gpio224o_pins: gpio224o-pins {
+			pins = "GPIO224/SPIX_CK/FM2_CK";
+			bias-disable;
+			output-high;
+		};
+		gpio224ol_pins: gpio224ol-pins {
+			pins = "GPIO224/SPIX_CK/FM2_CK";
+			bias-disable;
+			output-low;
+		};
+		gpio225_pins: gpio225-pins {
+			pins = "GPO225/SPIX_D0/FM2_D0/STRAP1";
+			bias-disable;
+			input-enable;
+		};
+		gpio225o_pins: gpio225o-pins {
+			pins = "GPO225/SPIX_D0/FM2_D0/STRAP1";
+			bias-disable;
+			output-high;
+		};
+		gpio226_pins: gpio226-pins {
+			pins = "GPO226/SPIX_D1/FM2_D1/STRAP2";
+			bias-disable;
+			input-enable;
+		};
+		gpio226o_pins: gpio226o-pins {
+			pins = "GPO226/SPIX_D1/FM2_D1/STRAP2";
+			bias-disable;
+			output-high;
+		};
+		gpio227_pins: gpio227-pins {
+			pins = "GPIO227/SPIX_nCS0/FM2_CSI";
+			bias-disable;
+			input-enable;
+		};
+		gpio227o_pins: gpio227o-pins {
+			pins = "GPIO227/SPIX_nCS0/FM2_CSI";
+			bias-disable;
+			output-high;
+		};
+		gpio227ol_pins: gpio227ol-pins {
+			pins = "GPIO227/SPIX_nCS0/FM2_CSI";
+			bias-disable;
+			output-low;
+		};
+		gpio228_pins: gpio228-pins {
+			pins = "GPIO228/SPIX_nCS1/FM2_CSO";
+			bias-disable;
+			input-enable;
+		};
+		gpio228ol_pins: gpio228ol-pins {
+			pins = "GPIO228/SPIX_nCS1/FM2_CSO";
+			bias-disable;
+			output-low;
+		};
+		gpio229_pins: gpio229-pins {
+			pins = "GPO229/SPIX_D2/FM2_D2/STRAP3";
+			bias-disable;
+			input-enable;
+		};
+		gpio229o_pins: gpio229o-pins {
+			pins = "GPO229/SPIX_D2/FM2_D2/STRAP3";
+			bias-disable;
+			output-high;
+		};
+		gpio230_pins: gpio230-pins {
+			pins = "GPO230/SPIX_D3/FM2_D3/STRAP6";
+			bias-disable;
+			input-enable;
+		};
+		gpio230o_pins: gpio230o-pins {
+			pins = "GPO230/SPIX_D3/FM2_D3/STRAP6";
+			bias-disable;
+			output-high;
+		};
+		gpio230ol_pins: gpio230ol-pins {
+			pins = "GPO230/SPIX_D3/FM2_D3/STRAP6";
+			bias-disable;
+			output-low;
+		};
+		gpio231_pins: gpio231-pins {
+			pins = "GPIO231/EP_nCLKREQ";
+			bias-disable;
+			input-enable;
+		};
+		gpio231o_pins: gpio231o-pins {
+			pins = "GPIO231/EP_nCLKREQ";
+			bias-disable;
+			output-high;
+		};
+	};
+};

+ 824 - 8
arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi

@@ -59,6 +59,174 @@
 			clocks = <&clk_refclk>;
 		};
 
+		ehci1: usb@f0828100 {
+			compatible = "nuvoton,npcm845-ehci";
+			reg = <0x0 0xf0828100 0x0 0x1000>;
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&rstc2 NPCM8XX_RESET_USBH1>;
+			status = "disabled";
+		};
+
+		ehci2: usb@f082a100 {
+			compatible = "nuvoton,npcm845-ehci";
+			reg = <0x0 0xf082a100 0x0 0x1000>;
+			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&rstc4 NPCM8XX_RESET_USBH2>;
+			status = "disabled";
+		};
+
+		ohci1: usb@f0829000 {
+			compatible = "nuvoton,npcm845-ohci";
+			reg = <0x0 0xF0829000 0x0 0x1000>;
+			resets = <&rstc2 NPCM8XX_RESET_USBH1>;
+			status = "disabled";
+		};
+
+		ohci2: usb@f082b000 {
+			compatible = "nuvoton,npcm845-ohci";
+			reg = <0x0 0xF082B000 0x0 0x1000>;
+			resets = <&rstc4 NPCM8XX_RESET_USBH2>;
+			status = "disabled";
+		};
+
+		usbphy {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			syscon = <&gcr>;
+			usbphy1: usbphy@1 {
+				compatible = "nuvoton,npcm845-usb-phy";
+				#phy-cells = <1>;
+				reg = <1>;
+				resets = <&rstc3 NPCM8XX_RESET_USBPHY1>;
+				status = "disabled";
+			};
+			usbphy2: usbphy@2 {
+				compatible = "nuvoton,npcm845-usb-phy";
+				#phy-cells = <1>;
+				reg = <2>;
+				resets = <&rstc3 NPCM8XX_RESET_USBPHY2>;
+				status = "disabled";
+			};
+			usbphy3: usbphy@3 {
+				compatible = "nuvoton,npcm845-usb-phy";
+				#phy-cells = <1>;
+				reg = <3>;
+				resets = <&rstc3 NPCM8XX_RESET_USBPHY3>;
+				status = "disabled";
+			};
+		};
+
+		udc0:udc@f0830100 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0830100 0x0 0x100
+			       0x0 0xfffb0000 0x0 0x800>;
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+			resets = <&rstc3 NPCM8XX_RESET_UDC0>;
+			status = "disable";
+		};
+
+		udc1:udc@f0831100 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0831100 0x0 0x100
+			       0x0 0xfffb0800 0x0 0x800>;
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+			resets = <&rstc1 NPCM8XX_RESET_UDC1>;
+			status = "disable";
+		};
+
+		udc2:udc@f0832100 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0832100 0x0 0x100
+			       0x0 0xfffb1000 0x0 0x800>;
+			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+			resets = <&rstc1 NPCM8XX_RESET_UDC2>;
+			status = "disable";
+		};
+
+		udc3:udc@f0833100 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0833100 0x0 0x100
+			       0x0 0xfffb1800 0x0 0x800>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+			resets = <&rstc1 NPCM8XX_RESET_UDC3>;
+			status = "disable";
+		};
+
+		udc4:udc@f0834100 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0834100 0x0 0x100
+			       0x0 0xfffb2000 0x0 0x800>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+			resets = <&rstc1 NPCM8XX_RESET_UDC4>;
+			status = "disable";
+		};
+
+		udc5:udc@f0835100 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0835100 0x0 0x100
+			       0x0 0xfffb2800 0x0 0x800>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+			resets = <&rstc1 NPCM8XX_RESET_UDC5>;
+			status = "disable";
+		};
+
+		udc6:udc@f0836100 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0836100 0x0 0x100
+			       0x0 0xfffb3000 0x0 0x800>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+			resets = <&rstc1 NPCM8XX_RESET_UDC6>;
+			status = "disable";
+		};
+
+		udc7:udc@f0837100 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0837100 0x0 0x100
+			       0x0 0xfffb3800 0x0 0x800>;
+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+			resets = <&rstc3 NPCM8XX_RESET_UDC7>;
+			status = "disable";
+		};
+
+		udc8:udc@f0838100 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0838100 0x0 0x100
+			       0x0 0xfffb4000 0x0 0x800>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+			resets = <&rstc3 NPCM8XX_RESET_UDC8>;
+			status = "disable";
+		};
+
+		udc9:udc@f0839100 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0839100 0x0 0x100
+			       0x0 0xfffb4800 0x0 0x800>;
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+			resets = <&rstc3 NPCM8XX_RESET_UDC9>;
+			status = "disable";
+		};
+
 		apb {
 			serial0: serial@0 {
 				compatible = "nuvoton,npcm845-uart";
@@ -69,7 +237,7 @@
 			};
 
 			gpio0: gpio0@10000 {
-				compatible = "nuvoton,npcm-gpio";
+				compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
 				reg = <0x10000 0xB0>;
 				#gpio-cells = <2>;
 				gpio-controller;
@@ -77,7 +245,7 @@
 			};
 
 			gpio1: gpio1@11000 {
-				compatible = "nuvoton,npcm-gpio";
+				compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
 				reg = <0x11000 0xB0>;
 				#gpio-cells = <2>;
 				gpio-controller;
@@ -85,7 +253,7 @@
 			};
 
 			gpio2: gpio2@12000 {
-				compatible = "nuvoton,npcm-gpio";
+				compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
 				reg = <0x12000 0xB0>;
 				#gpio-cells = <2>;
 				gpio-controller;
@@ -93,7 +261,7 @@
 			};
 
 			gpio3: gpio3@13000 {
-				compatible = "nuvoton,npcm-gpio";
+				compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
 				reg = <0x13000 0xB0>;
 				#gpio-cells = <2>;
 				gpio-controller;
@@ -101,7 +269,7 @@
 			};
 
 			gpio4: gpio4@14000 {
-				compatible = "nuvoton,npcm-gpio";
+				compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
 				reg = <0x14000 0xB0>;
 				#gpio-cells = <2>;
 				gpio-controller;
@@ -109,7 +277,7 @@
 			};
 
 			gpio5: gpio5@15000 {
-				compatible = "nuvoton,npcm-gpio";
+				compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
 				reg = <0x15000 0xB0>;
 				#gpio-cells = <2>;
 				gpio-controller;
@@ -117,7 +285,7 @@
 			};
 
 			gpio6: gpio6@16000 {
-				compatible = "nuvoton,npcm-gpio";
+				compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
 				reg = <0x16000 0xB0>;
 				#gpio-cells = <2>;
 				gpio-controller;
@@ -125,7 +293,7 @@
 			};
 
 			gpio7: gpio7@17000 {
-				compatible = "nuvoton,npcm-gpio";
+				compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
 				reg = <0x17000 0xB0>;
 				#gpio-cells = <2>;
 				gpio-controller;
@@ -133,4 +301,652 @@
 			};
 		};
 	};
+	pinctrl: pinctrl@f0800000 {
+		compatible = "nuvoton,npcm845-pinctrl", "syscon", "simple-mfd";
+		reg = <0x0 0xf0010000 0x0 0x8000>;
+		syscon-gcr = <&gcr>;
+		syscon-rst = <&rstc>;
+		status = "okay";
+
+		iox1_pins: iox1-pins {
+			groups = "iox1";
+			function = "iox1";
+		};
+		iox2_pins: iox2-pins {
+			groups = "iox2";
+			function = "iox2";
+		};
+		smb1d_pins: smb1d-pins {
+			groups = "smb1d";
+			function = "smb1d";
+		};
+		smb2d_pins: smb2d-pins {
+			groups = "smb2d";
+			function = "smb2d";
+		};
+		lkgpo1_pins: lkgpo1-pins {
+			groups = "lkgpo1";
+			function = "lkgpo1";
+		};
+		lkgpo2_pins: lkgpo2-pins {
+			groups = "lkgpo2";
+			function = "lkgpo2";
+		};
+		ioxh_pins: ioxh-pins {
+			groups = "ioxh";
+			function = "ioxh";
+		};
+		gspi_pins: gspi-pins {
+			groups = "gspi";
+			function = "gspi";
+		};
+		smb5b_pins: smb5b-pins {
+			groups = "smb5b";
+			function = "smb5b";
+		};
+		smb5c_pins: smb5c-pins {
+			groups = "smb5c";
+			function = "smb5c";
+		};
+		lkgpo0_pins: lkgpo0-pins {
+			groups = "lkgpo0";
+			function = "lkgpo0";
+		};
+		pspi_pins: pspi-pins {
+			groups = "pspi";
+			function = "pspi";
+		};
+		vgadig_pins: vgadig-pins {
+			groups = "vgadig";
+			function = "vgadig";
+		};
+		jm1_pins: jm1-pins {
+			groups = "jm1";
+			function = "jm1";
+		};
+		jm2_pins: jm2-pins {
+			groups = "jm2";
+			function = "jm2";
+		};
+		smb4b_pins: smb4b-pins {
+			groups = "smb4b";
+			function = "smb4b";
+		};
+		smb4c_pins: smb4c-pins {
+			groups = "smb4c";
+			function = "smb4c";
+		};
+		smb15_pins: smb15-pins {
+			groups = "smb15";
+			function = "smb15";
+		};
+		smb16_pins: smb16-pins {
+			groups = "smb16";
+			function = "smb16";
+		};
+		smb17_pins: smb17-pins {
+			groups = "smb17";
+			function = "smb17";
+		};
+		smb18_pins: smb18-pins {
+			groups = "smb18";
+			function = "smb18";
+		};
+		smb19_pins: smb19-pins {
+			groups = "smb19";
+			function = "smb19";
+		};
+		smb20_pins: smb20-pins {
+			groups = "smb20";
+			function = "smb20";
+		};
+		smb21_pins: smb21-pins {
+			groups = "smb21";
+			function = "smb21";
+		};
+		smb22_pins: smb22-pins {
+			groups = "smb22";
+			function = "smb22";
+		};
+		smb23_pins: smb23-pins {
+			groups = "smb23";
+			function = "smb23";
+		};
+		smb4d_pins: smb4d-pins {
+			groups = "smb4d";
+			function = "smb4d";
+		};
+		smb14_pins: smb14-pins {
+			groups = "smb14";
+			function = "smb14";
+		};
+		smb5_pins: smb5-pins {
+			groups = "smb5";
+			function = "smb5";
+		};
+		smb4_pins: smb4-pins {
+			groups = "smb4";
+			function = "smb4";
+		};
+		smb3_pins: smb3-pins {
+			groups = "smb3";
+			function = "smb3";
+		};
+		spi0cs1_pins: spi0cs1-pins {
+			groups = "spi0cs1";
+			function = "spi0cs1";
+		};
+		spi0cs2_pins: spi0cs2-pins {
+			groups = "spi0cs2";
+			function = "spi0cs2";
+		};
+		spi0cs3_pins: spi0cs3-pins {
+			groups = "spi0cs3";
+			function = "spi0cs3";
+		};
+		smb3c_pins: smb3c-pins {
+			groups = "smb3c";
+			function = "smb3c";
+		};
+		smb3b_pins: smb3b-pins {
+			groups = "smb3b";
+			function = "smb3b";
+		};
+		hsi1a_pins: hsi1a-pins {
+			groups = "hsi1a";
+			function = "hsi1a";
+		};
+		hsi1b_pins: hsi1b-pins {
+			groups = "hsi1b";
+			function = "hsi1b";
+		};
+		hsi1c_pins: hsi1c-pins {
+			groups = "hsi1c";
+			function = "hsi1c";
+		};
+		hsi2a_pins: hsi2a-pins {
+			groups = "hsi2a";
+			function = "hsi2a";
+		};
+		hsi2b_pins: hsi2b-pins {
+			groups = "hsi2b";
+			function = "hsi2b";
+		};
+		hsi2c_pins: hsi2c-pins {
+			groups = "hsi2c";
+			function = "hsi2c";
+		};
+		bmcuart0a_pins: bmcuart0a-pins {
+			groups = "bmcuart0a";
+			function = "bmcuart0a";
+		};
+		bmcuart0b_pins: bmcuart0b-pins {
+			groups = "bmcuart0b";
+			function = "bmcuart0b";
+		};
+		bmcuart1_pins: bmcuart1-pins {
+			groups = "bmcuart1";
+			function = "bmcuart1";
+		};
+		bu4_pins: bu4-pins {
+			groups = "bu4";
+			function = "bu4";
+		};
+		bu5_pins: bu5-pins {
+			groups = "bu5";
+			function = "bu5";
+		};
+		bu6_pins: bu6-pins {
+			groups = "bu6";
+			function = "bu6";
+		};
+		r1err_pins: r1err-pins {
+			groups = "r1err";
+			function = "r1err";
+		};
+		r1md_pins: r1md-pins {
+			groups = "r1md";
+			function = "r1md";
+		};
+		r1oen_pins: r1oen-pins {
+			groups = "r1oen";
+			function = "r1oen";
+		};
+		r1en_pins: r1en-pins {
+			groups = "r1en";
+			function = "r1en";
+		};
+		r2oen_pins: r2oen-pins {
+			groups = "r2oen";
+			function = "r2oen";
+		};
+		r2en_pins: r2en-pins {
+			groups = "r2en";
+			function = "r2en";
+		};
+		rmii3_pins: rmii3_pins {
+			groups = "rmii3";
+			function = "rmii3";
+		};
+		r3oen_pins: r3oen-pins {
+			groups = "r3oen";
+			function = "r3oen";
+		};
+		r3en_pins: r3en-pins {
+			groups = "r3en";
+			function = "r3en";
+		};
+		smb3d_pins: smb3d-pins {
+			groups = "smb3d";
+			function = "smb3d";
+		};
+		fanin0_pins: fanin0-pins {
+			groups = "fanin0";
+			function = "fanin0";
+		};
+		fanin1_pins: fanin1-pins {
+			groups = "fanin1";
+			function = "fanin1";
+		};
+		fanin2_pins: fanin2-pins {
+			groups = "fanin2";
+			function = "fanin2";
+		};
+		fanin3_pins: fanin3-pins {
+			groups = "fanin3";
+			function = "fanin3";
+		};
+		fanin4_pins: fanin4-pins {
+			groups = "fanin4";
+			function = "fanin4";
+		};
+		fanin5_pins: fanin5-pins {
+			groups = "fanin5";
+			function = "fanin5";
+		};
+		fanin6_pins: fanin6-pins {
+			groups = "fanin6";
+			function = "fanin6";
+		};
+		fanin7_pins: fanin7-pins {
+			groups = "fanin7";
+			function = "fanin7";
+		};
+		fanin8_pins: fanin8-pins {
+			groups = "fanin8";
+			function = "fanin8";
+		};
+		fanin9_pins: fanin9-pins {
+			groups = "fanin9";
+			function = "fanin9";
+		};
+		fanin10_pins: fanin10-pins {
+			groups = "fanin10";
+			function = "fanin10";
+		};
+		fanin11_pins: fanin11-pins {
+			groups = "fanin11";
+			function = "fanin11";
+		};
+		fanin12_pins: fanin12-pins {
+			groups = "fanin12";
+			function = "fanin12";
+		};
+		fanin13_pins: fanin13-pins {
+			groups = "fanin13";
+			function = "fanin13";
+		};
+		fanin14_pins: fanin14-pins {
+			groups = "fanin14";
+			function = "fanin14";
+		};
+		fanin15_pins: fanin15-pins {
+			groups = "fanin15";
+			function = "fanin15";
+		};
+		pwm0_pins: pwm0-pins {
+			groups = "pwm0";
+			function = "pwm0";
+		};
+		pwm1_pins: pwm1-pins {
+			groups = "pwm1";
+			function = "pwm1";
+		};
+		pwm2_pins: pwm2-pins {
+			groups = "pwm2";
+			function = "pwm2";
+		};
+		pwm3_pins: pwm3-pins {
+			groups = "pwm3";
+			function = "pwm3";
+		};
+		r2_pins: r2-pins {
+			groups = "r2";
+			function = "r2";
+		};
+		r2err_pins: r2err-pins {
+			groups = "r2err";
+			function = "r2err";
+		};
+		r2md_pins: r2md-pins {
+			groups = "r2md";
+			function = "r2md";
+		};
+		r3rxer_pins: r3rxer_pins {
+			groups = "r3rxer";
+			function = "r3rxer";
+		};
+		ga20kbc_pins: ga20kbc-pins {
+			groups = "ga20kbc";
+			function = "ga20kbc";
+		};
+		smb5d_pins: smb5d-pins {
+			groups = "smb5d";
+			function = "smb5d";
+		};
+		lpc_pins: lpc-pins {
+			groups = "lpc";
+			function = "lpc";
+		};
+		espi_pins: espi-pins {
+			groups = "espi";
+			function = "espi";
+		};
+		rg1_pins: rg1-pins {
+			groups = "rg1";
+			function = "rg1";
+		};
+		rg1mdio_pins: rg1mdio-pins {
+			groups = "rg1mdio";
+			function = "rg1mdio";
+		};
+		rg2_pins: rg2-pins {
+			groups = "rg2";
+			function = "rg2";
+		};
+		ddr_pins: ddr-pins {
+			groups = "ddr";
+			function = "ddr";
+		};
+		i3c0_pins: i3c0-pins {
+			groups = "i3c0";
+			function = "i3c0";
+		};
+		i3c1_pins: i3c1-pins {
+			groups = "i3c1";
+			function = "i3c1";
+		};
+		i3c2_pins: i3c2-pins {
+			groups = "i3c2";
+			function = "i3c2";
+		};
+		i3c3_pins: i3c3-pins {
+			groups = "i3c3";
+			function = "i3c3";
+		};
+		i3c4_pins: i3c4-pins {
+			groups = "i3c4";
+			function = "i3c4";
+		};
+		i3c5_pins: i3c5-pins {
+			groups = "i3c5";
+			function = "i3c5";
+		};
+		smb0_pins: smb0-pins {
+			groups = "smb0";
+			function = "smb0";
+		};
+		smb1_pins: smb1-pins {
+			groups = "smb1";
+			function = "smb1";
+		};
+		smb2_pins: smb2-pins {
+			groups = "smb2";
+			function = "smb2";
+		};
+		smb2c_pins: smb2c-pins {
+			groups = "smb2c";
+			function = "smb2c";
+		};
+		smb2b_pins: smb2b-pins {
+			groups = "smb2b";
+			function = "smb2b";
+		};
+		smb1c_pins: smb1c-pins {
+			groups = "smb1c";
+			function = "smb1c";
+		};
+		smb1b_pins: smb1b-pins {
+			groups = "smb1b";
+			function = "smb1b";
+		};
+		smb8_pins: smb8-pins {
+			groups = "smb8";
+			function = "smb8";
+		};
+		smb9_pins: smb9-pins {
+			groups = "smb9";
+			function = "smb9";
+		};
+		smb10_pins: smb10-pins {
+			groups = "smb10";
+			function = "smb10";
+		};
+		smb11_pins: smb11-pins {
+			groups = "smb11";
+			function = "smb11";
+		};
+		sd1_pins: sd1-pins {
+			groups = "sd1";
+			function = "sd1";
+		};
+		sd1pwr_pins: sd1pwr-pins {
+			groups = "sd1pwr";
+			function = "sd1pwr";
+		};
+		pwm4_pins: pwm4-pins {
+			groups = "pwm4";
+			function = "pwm4";
+		};
+		pwm5_pins: pwm5-pins {
+			groups = "pwm5";
+			function = "pwm5";
+		};
+		pwm6_pins: pwm6-pins {
+			groups = "pwm6";
+			function = "pwm6";
+		};
+		pwm7_pins: pwm7-pins {
+			groups = "pwm7";
+			function = "pwm7";
+		};
+		pwm8_pins: pwm8-pins {
+			groups = "pwm8";
+			function = "pwm8";
+		};
+		pwm9_pins: pwm9-pins {
+			groups = "pwm9";
+			function = "pwm9";
+		};
+		pwm10_pins: pwm10-pins {
+			groups = "pwm10";
+			function = "pwm10";
+		};
+		pwm11_pins: pwm11-pins {
+			groups = "pwm11";
+			function = "pwm11";
+		};
+		mmc8_pins: mmc8-pins {
+			groups = "mmc8";
+			function = "mmc8";
+		};
+		mmc_pins: mmc-pins {
+			groups = "mmc";
+			function = "mmc";
+		};
+		mmcwp_pins: mmcwp-pins {
+			groups = "mmcwp";
+			function = "mmcwp";
+		};
+		mmccd_pins: mmccd-pins {
+			groups = "mmccd";
+			function = "mmccd";
+		};
+		mmcrst_pins: mmcrst-pins {
+			groups = "mmcrst";
+			function = "mmcrst";
+		};
+		clkout_pins: clkout-pins {
+			groups = "clkout";
+			function = "clkout";
+		};
+		serirq_pins: serirq-pins {
+			groups = "serirq";
+			function = "serirq";
+		};
+		scipme_pins: scipme-pins {
+			groups = "scipme";
+			function = "scipme";
+		};
+		sci_pins: sci-pins {
+			groups = "sci";
+			function = "sci";
+		};
+		smb6_pins: smb6-pins {
+			groups = "smb6";
+			function = "smb6";
+		};
+		smb7_pins: smb7-pins {
+			groups = "smb7";
+			function = "smb7";
+		};
+		spi1_pins: spi1-pins {
+			groups = "spi1";
+			function = "spi1";
+		};
+		spi1d23_pins: spi1d23-pins {
+			groups = "spi1d23";
+			function = "spi1d23";
+		};
+		faninx_pins: faninx-pins {
+			groups = "faninx";
+			function = "faninx";
+		};
+		r1_pins: r1-pins {
+			groups = "r1";
+			function = "r1";
+		};
+		spi3_pins: spi3-pins {
+			groups = "spi3";
+			function = "spi3";
+		};
+		spi3cs1_pins: spi3cs1-pins {
+			groups = "spi3cs1";
+			function = "spi3cs1";
+		};
+		spi3quad_pins: spi3quad-pins {
+			groups = "spi3quad";
+			function = "spi3quad";
+		};
+		spi3cs2_pins: spi3cs2-pins {
+			groups = "spi3cs2";
+			function = "spi3cs2";
+		};
+		spi3cs3_pins: spi3cs3-pins {
+			groups = "spi3cs3";
+			function = "spi3cs3";
+		};
+		nprd_smi_pins: nprd-smi-pins {
+			groups = "nprd_smi";
+			function = "nprd_smi";
+		};
+		smb0b_pins: smb0b-pins {
+			groups = "smb0b";
+			function = "smb0b";
+		};
+		smb0c_pins: smb0c-pins {
+			groups = "smb0c";
+			function = "smb0c";
+		};
+		smb0den_pins: smb0den-pins {
+			groups = "smb0den";
+			function = "smb0den";
+		};
+		smb0d_pins: smb0d-pins {
+			groups = "smb0d";
+			function = "smb0d";
+		};
+		rg2mdio_pins: rg2mdio-pins {
+			groups = "rg2mdio";
+			function = "rg2mdio";
+		};
+		rg2refck_pins: rg2refck-pins {
+			groups = "rg2refck";
+			function = "rg2refck";
+		};
+		wdog1_pins: wdog1-pins {
+			groups = "wdog1";
+			function = "wdog1";
+		};
+		wdog2_pins: wdog2-pins {
+			groups = "wdog2";
+			function = "wdog2";
+		};
+		smb12_pins: smb12-pins {
+			groups = "smb12";
+			function = "smb12";
+		};
+		smb13_pins: smb13-pins {
+			groups = "smb13";
+			function = "smb13";
+		};
+		spix_pins: spix-pins {
+			groups = "spix";
+			function = "spix";
+		};
+		spixcs1_pins: spixcs1-pins {
+			groups = "spixcs1";
+			function = "spixcs1";
+		};
+		clkreq_pins: clkreq-pins {
+			groups = "clkreq";
+			function = "clkreq";
+		};
+		hgpio0_pins: hgpio0-pins {
+			groups = "hgpio0";
+			function = "hgpio0";
+		};
+		hgpio1_pins: hgpio1-pins {
+			groups = "hgpio1";
+			function = "hgpio1";
+		};
+		hgpio2_pins: hgpio2-pins {
+			groups = "hgpio2";
+			function = "hgpio2";
+		};
+		hgpio3_pins: hgpio3-pins {
+			groups = "hgpio3";
+			function = "hgpio3";
+		};
+		hgpio4_pins: hgpio4-pins {
+			groups = "hgpio4";
+			function = "hgpio4";
+		};
+		hgpio5_pins: hgpio5-pins {
+			groups = "hgpio5";
+			function = "hgpio5";
+		};
+		hgpio6_pins: hgpio6-pins {
+			groups = "hgpio6";
+			function = "hgpio6";
+		};
+		hgpio7_pins: hgpio7-pins {
+			groups = "hgpio7";
+			function = "hgpio7";
+		};
+		jtag2_pins: jtag2-pins {
+			groups = "jtag2";
+			function = "jtag2";
+		};
+	};
 };

+ 8 - 0
arch/arm/dts/omap4-u-boot.dtsi

@@ -17,6 +17,14 @@
 			compatible = "simple-bus";
 		};
 	};
+
+	segment@80000 {
+		/* USB OTG */
+		target-module@2b000 {
+			compatible = "simple-bus";
+		};
+	};
+
 };
 
 &l4_per {

+ 2 - 2
arch/arm/dts/rockchip-optee.dtsi

@@ -32,8 +32,8 @@
 					arch = "arm";
 					os = "tee";
 					compression = "none";
-					load = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>;
-					entry = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>;
+					load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
+					entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
 
 					blob-ext {
 						filename = "tee.bin";

+ 6 - 0
arch/arm/dts/s5p4418-nanopi2.dts

@@ -25,6 +25,7 @@
 		i2c0 = "/i2c@c00a4000";
 		i2c1 = "/i2c@c00a5000";
 		i2c2 = "/i2c@c00a6000";
+		serial0 = "/uart@c00a1000";
 	};
 
 	mmc0:mmc@c0062000 {
@@ -107,4 +108,9 @@
 			};
 		};
 	};
+
+	uart0:uart@c00a1000 {
+		skip-init;
+		status = "okay";
+	};
 };

+ 71 - 0
arch/arm/dts/s5p4418-pinctrl.dtsi

@@ -132,4 +132,75 @@ pinctrl@C0010000 {
 		pin-pull = <2>;
 		pin-strength = <0>;
 	};
+
+	/* UART */
+	uart0_rx:uart0-rx {
+		pins = "gpiod-14";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <0>;
+	};
+
+	uart0_tx:uart0-tx {
+		pins = "gpiod-18";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <0>;
+	};
+
+	uart1_rx:uart1-rx {
+		pins = "gpiod-15";
+		pin-function = <2>;
+		pin-pull = <2>;
+		pin-strength = <0>;
+	};
+
+	uart1_tx:uart1-tx {
+		pins = "gpiod-19";
+		pin-function = <2>;
+		pin-pull = <2>;
+		pin-strength = <0>;
+	};
+
+	uart2_rx:uart2-rx {
+		pins = "gpiod-16";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <0>;
+	};
+
+	uart2_tx:uart2-tx {
+		pins = "gpiod-20";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <0>;
+	};
+
+	uart3_rx:uart3-rx {
+		pins = "gpiod-17";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <0>;
+	};
+
+	uart3_tx:uart3-tx {
+		pins = "gpiod-21";
+		pin-function = <1>;
+		pin-pull = <2>;
+		pin-strength = <0>;
+	};
+
+	uart4_rx:uart4-rx {
+		pins = "gpiob-28";
+		pin-function = <3>;
+		pin-pull = <2>;
+		pin-strength = <0>;
+	};
+
+	uart4_tx:uart4-tx {
+		pins = "gpiob-29";
+		pin-function = <3>;
+		pin-pull = <2>;
+		pin-strength = <0>;
+	};
 };

+ 40 - 0
arch/arm/dts/s5p4418.dtsi

@@ -167,4 +167,44 @@
 		reg = <0xc0010000 0xf000>;
 		u-boot,dm-pre-reloc;
 	};
+
+	uart0:uart@c00a1000 {
+		compatible = "nexell,s5p4418-pl011", "arm,primecell";
+		reg = <0xc00a1000 0x1000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart0_rx>, <&uart0_tx>;
+		status = "disabled";
+	};
+
+	uart1:uart@c00a0000 {
+		compatible = "nexell,s5p4418-pl011", "arm,primecell";
+		reg = <0xc00a0000 0x1000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart1_rx>, <&uart1_tx>;
+		status = "disabled";
+	};
+
+	uart2:uart@c00a2000 {
+		compatible = "nexell,s5p4418-pl011", "arm,primecell";
+		reg = <0xc00a2000 0x1000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart2_rx>, <&uart2_tx>;
+		status = "disabled";
+	};
+
+	uart3:uart@c00a3000 {
+		compatible = "nexell,s5p4418-pl011", "arm,primecell";
+		reg = <0xc00a3000 0x1000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart3_rx>, <&uart3_tx>;
+		status = "disabled";
+	};
+
+	uart4:uart@c006d000 {
+		compatible = "nexell,s5p4418-pl011", "arm,primecell";
+		reg = <0xc006d000 0x1000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart4_rx>, <&uart4_tx>;
+		status = "disabled";
+	};
 };

+ 85 - 0
arch/arm/dts/sam9x60.dtsi

@@ -69,6 +69,50 @@
 		#size-cells = <1>;
 		ranges;
 
+		usb1: usb@600000 {
+			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+			reg = <0x00600000 0x100000>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 21>;
+			clock-names = "ohci_clk", "hclk", "uhpck";
+			status = "disabled";
+		};
+
+		usb2: usb@700000 {
+			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+			reg = <0x00700000 0x100000>;
+			clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_PERIPHERAL 22>;
+			clock-names = "usb_clk", "ehci_clk";
+			assigned-clocks = <&pmc PMC_TYPE_CORE 8>;
+			assigned-clock-rates = <480000000>;
+			status = "disabled";
+		};
+
+		ebi: ebi@10000000 {
+			compatible = "microchip,sam9x60-ebi";
+			#address-cells = <2>;
+			#size-cells = <1>;
+			atmel,smc = <&smc>;
+			microchip,sfr = <&sfr>;
+			reg = <0x10000000 0x60000000>;
+			ranges = <0x0 0x0 0x10000000 0x10000000
+				  0x1 0x0 0x20000000 0x10000000
+				  0x2 0x0 0x30000000 0x10000000
+				  0x3 0x0 0x40000000 0x10000000
+				  0x4 0x0 0x50000000 0x10000000
+				  0x5 0x0 0x60000000 0x10000000>;
+			clocks = <&pmc PMC_TYPE_CORE 11>;
+			status = "disabled";
+
+			nand_controller: nand-controller {
+				compatible = "microchip,sam9x60-nand-controller";
+				ecc-engine = <&pmecc>;
+				#address-cells = <2>;
+				#size-cells = <1>;
+				ranges;
+				status = "disabled";
+			};
+		};
+
 		sdhci0: sdhci-host@80000000 {
 			compatible = "microchip,sam9x60-sdhci";
 			reg = <0x80000000 0x300>;
@@ -82,6 +126,19 @@
 			pinctrl-0 = <&pinctrl_sdhci0>;
 		};
 
+		sdhci1: sdhci-host@90000000 {
+			compatible = "microchip,sam9x60-sdhci";
+			reg = <0x90000000 0x300>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
+			assigned-clock-rates = <100000000>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
+			bus-width = <4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_sdhci1>;
+		};
+
 		apb {
 			compatible = "simple-bus";
 			#address-cells = <1>;
@@ -119,6 +176,11 @@
 				status = "disabled";
 			};
 
+			sfr: sfr@f8050000 {
+				compatible = "microchip,sam9x60-sfr", "syscon";
+				reg = <0xf8050000 0x100>;
+			};
+
 			dbgu: serial@fffff200 {
 				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
 				reg = <0xfffff200 0x200>;
@@ -180,6 +242,29 @@
 							 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>;	/* PA20 DAT3 periph A with pullup */
 					};
 				};
+
+				sdhci1 {
+					pinctrl_sdhci1: sdhci1 {
+						atmel,pins =
+							<AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI)				/* PA13 CK periph B */
+							 AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA12 CMD periph B with pullup */
+							 AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA11 DAT0 periph B with pullup */
+							 AT91_PIOA  2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA2 DAT1 periph B with pullup */
+							 AT91_PIOA  3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA3 DAT2 periph B with pullup */
+							 AT91_PIOA  4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>;	/* PA4 DAT3 periph B with pullup */
+					};
+				};
+			};
+
+			pmecc: ecc-engine@ffffe000 {
+				compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
+				reg = <0xffffe000 0x300>,
+				      <0xffffe600 0x100>;
+			};
+
+			smc: smc@ffffea00 {
+				compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
+				reg = <0xffffea00 0x100>;
 			};
 
 			pioA: gpio@fffff400 {

+ 124 - 0
arch/arm/dts/sam9x60ek.dts

@@ -80,6 +80,44 @@
 			};
 
 			pinctrl {
+				nand {
+					pinctrl_nand_oe_we: nand-oe-we-0 {
+						atmel,pins =
+							<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+							 AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+					};
+
+					pinctrl_nand_rb: nand-rb-0 {
+						atmel,pins =
+							<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+					};
+
+					pinctrl_nand_cs: nand-cs-0 {
+						atmel,pins =
+							<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+					};
+				};
+
+				ebi {
+					pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
+						atmel,pins =
+							<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+							 AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+							 AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+							 AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+							 AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+							 AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+							 AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+							 AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+					};
+
+					pinctrl_ebi_addr_nand: ebi-addr-0 {
+						atmel,pins =
+							<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+							 AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+					};
+				};
+
 				pinctrl_qspi: qspi {
 					atmel,pins =
 						<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
@@ -101,6 +139,78 @@
 						<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
 				};
 
+				usb1 {
+					pinctrl_usb_default: usb_default {
+						atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+								AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+					};
+				};
+
+			};
+		};
+	};
+};
+
+&ebi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
+	status = "okay";
+
+	nand_controller: nand-controller {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
+		status = "okay";
+
+		nand@3 {
+			reg = <0x3 0x0 0x800000>;
+			rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+			cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+			nand-bus-width = <8>;
+			nand-ecc-mode = "hw";
+			nand-ecc-strength = <8>;
+			nand-ecc-step-size = <512>;
+			nand-on-flash-bbt;
+			label = "atmel_nand";
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				at91bootstrap@0 {
+					label = "at91bootstrap";
+					reg = <0x0 0x40000>;
+				};
+
+				uboot@40000 {
+					label = "u-boot";
+					reg = <0x40000 0xc0000>;
+				};
+
+				ubootenvred@100000 {
+					label = "U-Boot Env Redundant";
+					reg = <0x100000 0x40000>;
+				};
+
+				ubootenv@140000 {
+					label = "U-Boot Env";
+					reg = <0x140000 0x40000>;
+				};
+
+				dtb@180000 {
+					label = "device tree";
+					reg = <0x180000 0x80000>;
+				};
+
+				kernel@200000 {
+					label = "kernel";
+					reg = <0x200000 0x600000>;
+				};
+
+				rootfs@800000 {
+					label = "rootfs";
+					reg = <0x800000 0x1f800000>;
+				};
 			};
 		};
 	};
@@ -110,3 +220,17 @@
 	phy-mode = "rmii";
 	status = "okay";
 };
+
+&usb1 {
+	num-ports = <3>;
+	atmel,vbus-gpio = <0
+			   &pioD 15 GPIO_ACTIVE_HIGH
+			   &pioD 16 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_default>;
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};

+ 0 - 1
arch/arm/dts/sama5d2.dtsi

@@ -84,7 +84,6 @@
 				reg = <0xf0014000 0x160>;
 				#address-cells = <1>;
 				#size-cells = <0>;
-				#interrupt-cells = <1>;
 				u-boot,dm-pre-reloc;
 
 				main: mainck {

+ 16 - 11
arch/arm/dts/sama7g5.dtsi

@@ -15,6 +15,7 @@
 #include <dt-bindings/clk/at91.h>
 #include <dt-bindings/dma/at91.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/at91-usart.h>
 
 / {
 	model = "Microchip SAMA7G5 family SoC";
@@ -195,11 +196,11 @@
 				<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			gpio-controller;
 			#gpio-cells = <2>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
 		};
 
 		pmc: pmc@e0018000 {
@@ -211,6 +212,13 @@
 			clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
 		};
 
+		reset_controller: reset-controller@e001d000 {
+			compatible = "microchip,sama7g5-rstc";
+			reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
+			#reset-cells = <1>;
+			clocks = <&clk32k 0>;
+		};
+
 		shdwc: shdwc@e001d010 {
 			compatible = "microchip,sama7g5-shdwc", "syscon";
 			reg = <0xe001d010 0x10>;
@@ -229,13 +237,6 @@
 			clocks = <&clk32k 0>;
 		};
 
-		reset_controller: rstc@e001d000 {
-			compatible = "microchip,sama7g5-rstc", "microchip,sam9x60-rstc";
-			reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
-			#reset-cells = <1>;
-			clocks = <&clk32k 0>;
-		};
-
 		clk32k: clock-controller@e001d050 {
 			compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc";
 			reg = <0xe001d050 0x4>;
@@ -620,6 +621,7 @@
 			uart0: serial@200 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0x200 0x200>;
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
 				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
 				clock-names = "usart";
@@ -668,6 +670,7 @@
 			uart3: serial@200 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0x200 0x200>;
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
 				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
 				clock-names = "usart";
@@ -711,6 +714,7 @@
 			uart4: serial@200 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0x200 0x200>;
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
 				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
 				clock-names = "usart";
@@ -736,6 +740,7 @@
 			uart7: serial@200 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0x200 0x200>;
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
 				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
 				clock-names = "usart";
@@ -884,9 +889,9 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 				atmel,fifo-size = <32>;
-				dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>,
-					    <&dma0 AT91_XDMAC_DT_PERID(28)>;
-				dma-names = "rx", "tx";
+				dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>,
+					    <&dma0 AT91_XDMAC_DT_PERID(27)>;
+				dma-names = "tx", "rx";
 				status = "disabled";
 			};
 		};

+ 1 - 3
arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi

@@ -20,10 +20,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "okay";
-		active_clk_edges;
-		chipselect_num = <1>;
 
-		spi-flash@0 {
+		flash@0 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "jedec,spi-nor";

+ 1 - 1
arch/arm/dts/synquacer-sc2a11-developerbox.dts

@@ -18,7 +18,7 @@
         compatible = "gpio-keys";
         interrupt-parent = <&exiu>;
 
-        power {
+        power-button {
             label = "Power Button";
             linux,code = <KEY_POWER>;
             interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_FALLING>;

+ 35 - 36
arch/arm/dts/synquacer-sc2a11.dtsi

@@ -41,168 +41,168 @@
 
         CPU0: cpu@0 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x0>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU1: cpu@1 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x1>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU2: cpu@100 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x100>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU3: cpu@101 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x101>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU4: cpu@200 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x200>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU5: cpu@201 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x201>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU6: cpu@300 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x300>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU7: cpu@301 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x301>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU8: cpu@400 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x400>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU9: cpu@401 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x401>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU10: cpu@500 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x500>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU11: cpu@501 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x501>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU12: cpu@600 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x600>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU13: cpu@601 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x601>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU14: cpu@700 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x700>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU15: cpu@701 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x701>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU16: cpu@800 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x800>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU17: cpu@801 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x801>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU18: cpu@900 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x900>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU19: cpu@901 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0x901>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU20: cpu@a00 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0xa00>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU21: cpu@a01 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0xa01>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU22: cpu@b00 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0xb00>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
         };
         CPU23: cpu@b01 {
             device_type = "cpu";
-            compatible = "arm,cortex-a53","arm,armv8";
+            compatible = "arm,cortex-a53";
             reg = <0xb01>;
             enable-method = "psci";
             cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -309,7 +309,7 @@
     };
 
     idle-states {
-        entry-method = "arm,psci";
+        entry-method = "psci";
 
         CPU_SLEEP_0: cpu-sleep-0 {
             compatible = "arm,idle-state";
@@ -344,7 +344,7 @@
         interrupt-controller;
         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 
-        its: gic-its@30020000 {
+        its: msi-controller@30020000 {
             compatible = "arm,gic-v3-its";
             reg = <0x0 0x30020000 0x0 0x20000>;
             #msi-cells = <1>;
@@ -361,16 +361,16 @@
                      <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;   // HYP
     };
 
-    mmio-timer@2a810000 {
+    timer@2a810000 {
         compatible = "arm,armv7-timer-mem";
         reg = <0x0 0x2a810000 0x0 0x10000>;
-        #address-cells = <2>;
-        #size-cells = <2>;
-        ranges;
-        frame@2a830000 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges = <0x0 0x0 0x2a810000 0x30000>;
+        frame@20000 {
             frame-number = <0>;
             interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-            reg = <0x0 0x2a830000 0x0 0x10000>;
+            reg = <0x20000 0x10000>;
         };
     };
 
@@ -398,7 +398,7 @@
         clock-output-names = "apb_pclk";
     };
 
-    soc_uart0: uart@2a400000 {
+    soc_uart0: serial@2a400000 {
         compatible = "arm,pl011", "arm,primecell";
         reg = <0x0 0x2a400000 0x0 0x1000>;
         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
@@ -406,7 +406,7 @@
         clock-names = "uartclk", "apb_pclk";
     };
 
-    fuart: uart@51040000 {
+    fuart: serial@51040000 {
         compatible = "snps,dw-apb-uart";
         reg = <0x0 0x51040000 0x0 0x1000>;
         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
@@ -497,7 +497,6 @@
         gpio-controller;
         #gpio-cells = <2>;
         clocks = <&clk_apb>;
-        base = <0>;
     };
 
     exiu: interrupt-controller@510c0000 {
@@ -523,7 +522,7 @@
         clock-output-names = "sd_sd4clk";
     };
 
-    sdhci: sdhci@52300000 {
+    sdhci: mmc@52300000 {
         compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0";
         reg = <0 0x52300000 0x0 0x1000>;
         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,

+ 4 - 0
arch/arm/dts/uniphier-v7-u-boot.dtsi

@@ -2,6 +2,10 @@
 	soc {
 		u-boot,dm-pre-reloc;
 
+		timer@60000200 {
+			u-boot,dm-pre-reloc;
+		};
+
 		serial@54006800 {
 			u-boot,dm-pre-reloc;
 		};

+ 1 - 1
arch/arm/include/asm/arch-am33xx/clock.h

@@ -13,7 +13,7 @@
 #include <asm/arch/clocks_am33xx.h>
 #include <asm/arch/hardware.h>
 
-#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X)
+#if defined(CONFIG_TI816X)
 #include <asm/arch/clock_ti81xx.h>
 #endif
 

+ 6 - 30
arch/arm/include/asm/arch-am33xx/clock_ti81xx.h

@@ -44,9 +44,7 @@ struct cm_alwon {
 	unsigned int mmu_clkstctrl;
 	unsigned int mmucfg_clkstctrl;
 	unsigned int ocmc0clkstctrl;
-#if defined(CONFIG_TI814X)
-	unsigned int vcpclkstctrl;
-#elif defined(CONFIG_TI816X)
+#if defined(CONFIG_TI816X)
 	unsigned int ocmc1clkstctrl;
 #endif
 	unsigned int mpuclkstctrl;
@@ -67,16 +65,7 @@ struct cm_alwon {
 	unsigned int gpio1clkctrl;
 	unsigned int i2c0clkctrl;
 	unsigned int i2c1clkctrl;
-#if defined(CONFIG_TI814X)
-	unsigned int mcasp345clkctrl;
-	unsigned int atlclkctrl;
-	unsigned int mlbclkctrl;
-	unsigned int pataclkctrl;
-	unsigned int resv1[1];
-	unsigned int uart3clkctrl;
-	unsigned int uart4clkctrl;
-	unsigned int uart5clkctrl;
-#elif defined(CONFIG_TI816X)
+#if defined(CONFIG_TI816X)
 	unsigned int resv1[1];
 	unsigned int timer1clkctrl;
 	unsigned int timer2clkctrl;
@@ -93,16 +82,12 @@ struct cm_alwon {
 	unsigned int mmudataclkctrl;
 	unsigned int resv2[2];
 	unsigned int mmucfgclkctrl;
-#if defined(CONFIG_TI814X)
-	unsigned int resv3[2];
-#elif defined(CONFIG_TI816X)
+#if defined(CONFIG_TI816X)
 	unsigned int resv3[1];
 	unsigned int sdioclkctrl;
 #endif
 	unsigned int ocmc0clkctrl;
-#if defined(CONFIG_TI814X)
-	unsigned int vcpclkctrl;
-#elif defined(CONFIG_TI816X)
+#if defined(CONFIG_TI816X)
 	unsigned int ocmc1clkctrl;
 #endif
 	unsigned int resv4[2];
@@ -112,9 +97,7 @@ struct cm_alwon {
 	unsigned int ethernet0clkctrl;
 	unsigned int ethernet1clkctrl;
 	unsigned int mpuclkctrl;
-#if defined(CONFIG_TI814X)
-	unsigned int debugssclkctrl;
-#elif defined(CONFIG_TI816X)
+#if defined(CONFIG_TI816X)
 	unsigned int resv6[1];
 #endif
 	unsigned int l3clkctrl;
@@ -126,14 +109,7 @@ struct cm_alwon {
 	unsigned int tptc1clkctrl;
 	unsigned int tptc2clkctrl;
 	unsigned int tptc3clkctrl;
-#if defined(CONFIG_TI814X)
-	unsigned int resv6[4];
-	unsigned int dcan01clkctrl;
-	unsigned int mmchs0clkctrl;
-	unsigned int mmchs1clkctrl;
-	unsigned int mmchs2clkctrl;
-	unsigned int custefuseclkctrl;
-#elif defined(CONFIG_TI816X)
+#if defined(CONFIG_TI816X)
 	unsigned int sr0clkctrl;
 	unsigned int sr1clkctrl;
 #endif

+ 0 - 2
arch/arm/include/asm/arch-am33xx/hardware.h

@@ -16,8 +16,6 @@
 #include <asm/arch/hardware_am33xx.h>
 #elif defined(CONFIG_TI816X)
 #include <asm/arch/hardware_ti816x.h>
-#elif defined(CONFIG_TI814X)
-#include <asm/arch/hardware_ti814x.h>
 #elif defined(CONFIG_AM43XX)
 #include <asm/arch/hardware_am43xx.h>
 #endif

+ 0 - 60
arch/arm/include/asm/arch-am33xx/hardware_ti814x.h

@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * hardware_ti814x.h
- *
- * TI814x hardware specific header
- *
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
- */
-
-#ifndef __AM33XX_HARDWARE_TI814X_H
-#define __AM33XX_HARDWARE_TI814X_H
-
-/* Module base addresses */
-
-/* UART Base Address */
-#define UART0_BASE			0x48020000
-
-/* Watchdog Timer */
-#define WDT_BASE			0x481C7000
-
-/* Control Module Base Address */
-#define CTRL_BASE			0x48140000
-#define CTRL_DEVICE_BASE		0x48140600
-
-/* PRCM Base Address */
-#define PRCM_BASE			0x48180000
-#define CM_PER				0x44E00000
-#define CM_WKUP				0x44E00400
-
-#define PRM_RSTCTRL			(PRCM_BASE + 0x00A0)
-#define PRM_RSTST			(PRM_RSTCTRL + 8)
-
-/* PLL Subsystem Base Address */
-#define PLL_SUBSYS_BASE			0x481C5000
-
-/* VTP Base address */
-#define VTP0_CTRL_ADDR			0x48140E0C
-#define VTP1_CTRL_ADDR			0x48140E10
-
-/* DDR Base address */
-#define DDR_PHY_CMD_ADDR		0x47C0C400
-#define DDR_PHY_DATA_ADDR		0x47C0C4C8
-#define DDR_PHY_CMD_ADDR2		0x47C0C800
-#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
-#define DDR_DATA_REGS_NR		4
-
-#define DDRPHY_0_CONFIG_BASE		(CTRL_BASE + 0x1400)
-#define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
-
-/* CPSW Config space */
-#define CPSW_MDIO_BASE			0x4A100800
-
-/* RTC base address */
-#define RTC_BASE			0x480C0000
-
-/* OTG */
-#define USB0_OTG_BASE			0x47401000
-#define USB1_OTG_BASE			0x47401800
-
-#endif /* __AM33XX_HARDWARE_TI814X_H */

+ 1 - 4
arch/arm/include/asm/arch-am33xx/mmc_host_def.h

@@ -24,10 +24,7 @@
 #define OMAP_HSMMC1_BASE		0x48060000
 #define OMAP_HSMMC2_BASE		0x481D8000
 
-#if defined(CONFIG_TI814X)
-#undef MMC_CLOCK_REFERENCE
-#define MMC_CLOCK_REFERENCE	192 /* MHz */
-#elif defined(CONFIG_TI816X)
+#if defined(CONFIG_TI816X)
 #undef MMC_CLOCK_REFERENCE
 #define MMC_CLOCK_REFERENCE	48 /* MHz */
 #endif

+ 0 - 2
arch/arm/include/asm/arch-am33xx/mux.h

@@ -20,8 +20,6 @@
 
 #ifdef CONFIG_AM33XX
 #include <asm/arch/mux_am33xx.h>
-#elif defined(CONFIG_TI814X)
-#include <asm/arch/mux_ti814x.h>
 #elif defined(CONFIG_TI816X)
 #include <asm/arch/mux_ti816x.h>
 #elif defined(CONFIG_AM43XX)

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