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@@ -31,6 +31,25 @@
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#clock-cells = <0>;
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u-boot,dm-pre-reloc;
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};
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+
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+ mmcclk_ciu: mmcclk-ciu {
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+ compatible = "fixed-clock";
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+ /*
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+ * DW sdio controller has external ciu clock divider
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+ * controlled via register in SDIO IP. It divides
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+ * sdio_ref_clk (which comes from CGU) by 16 for
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+ * default. So default mmcclk clock (which comes
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+ * to sdk_in) is 25000000 Hz.
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+ */
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+ clock-frequency = <25000000>;
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+ #clock-cells = <0>;
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+ };
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+
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+ mmcclk_biu: mmcclk-biu {
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+ compatible = "fixed-clock";
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+ clock-frequency = <50000000>;
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+ #clock-cells = <0>;
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+ };
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};
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ethernet@18000 {
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@@ -53,6 +72,15 @@
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reg = < 0x60000 0x100 >;
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};
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+ mmc: mmc@15000 {
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+ compatible = "snps,dw-mshc";
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+ reg = <0x15000 0x400>;
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+ bus-width = <4>;
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+ clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
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+ clock-names = "biu", "ciu";
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+ max-frequency = <25000000>;
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+ };
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+
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uart0: serial0@22000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x22000 0x100>;
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