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@@ -17,6 +17,7 @@
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#include <malloc.h>
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#include <memalign.h>
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#include <spi.h>
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+#include <spi-mem.h>
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#include <ubi_uboot.h>
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#include <wait_bit.h>
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#include <dm/device_compat.h>
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@@ -172,8 +173,7 @@ struct zynqmp_qspi_priv {
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unsigned int len;
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int bytes_to_transfer;
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int bytes_to_receive;
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- unsigned int is_inst;
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- unsigned int cs_change:1;
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+ const struct spi_mem_op *op;
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};
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static int zynqmp_qspi_of_to_plat(struct udevice *bus)
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@@ -222,6 +222,21 @@ static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
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return gqspi_fifo_reg;
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}
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+static u32 zynqmp_qspi_genfifo_mode(u8 buswidth)
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+{
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+ switch (buswidth) {
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+ case 1:
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+ return GQSPI_SPI_MODE_SPI;
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+ case 2:
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+ return GQSPI_SPI_MODE_DUAL_SPI;
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+ case 4:
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+ return GQSPI_SPI_MODE_QSPI;
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+ default:
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+ debug("Unsupported bus width %u\n", buswidth);
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+ return GQSPI_SPI_MODE_SPI;
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+ }
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+}
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+
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static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
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u32 gqspi_fifo_reg)
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{
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@@ -306,12 +321,9 @@ static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
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if (speed > plat->frequency)
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speed = plat->frequency;
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- /* Set the clock frequency */
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- confr = readl(®s->confr);
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- if (speed == 0) {
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- /* Set baudrate x8, if the freq is 0 */
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- baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
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- } else if (plat->speed_hz != speed) {
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+ if (plat->speed_hz != speed) {
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+ /* Set the clock frequency */
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+ /* If speed == 0, default to lowest speed */
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while ((baud_rate_val < 8) &&
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((plat->frequency /
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(2 << baud_rate_val)) > speed))
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@@ -321,13 +333,15 @@ static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
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baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
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plat->speed_hz = plat->frequency / (2 << baud_rate_val);
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- }
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- confr &= ~GQSPI_BAUD_DIV_MASK;
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- confr |= (baud_rate_val << 3);
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- writel(confr, ®s->confr);
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- zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
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- debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
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+ confr = readl(®s->confr);
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+ confr &= ~GQSPI_BAUD_DIV_MASK;
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+ confr |= (baud_rate_val << 3);
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+ writel(confr, ®s->confr);
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+ zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
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+
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+ debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
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+ }
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return 0;
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}
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@@ -359,7 +373,7 @@ static int zynqmp_qspi_probe(struct udevice *bus)
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debug("%s: CLK %ld\n", __func__, clock);
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ret = clk_enable(&clk);
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- if (ret && ret != -ENOSYS) {
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+ if (ret) {
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dev_err(bus, "failed to enable clock\n");
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return ret;
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}
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@@ -446,21 +460,42 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
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static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
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{
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+ const struct spi_mem_op *op = priv->op;
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u32 gen_fifo_cmd;
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- u32 bytecount = 0;
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+ u8 i, dummy_cycles, addr;
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+
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+ /* Send opcode */
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+ gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
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+ gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth);
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+ gen_fifo_cmd |= GQSPI_GFIFO_TX;
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+ gen_fifo_cmd |= op->cmd.opcode;
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+ zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
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+
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+ /* Send address */
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+ for (i = 0; i < op->addr.nbytes; i++) {
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+ addr = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
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- while (priv->len) {
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gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
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- gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_SPI_MODE_SPI;
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- gen_fifo_cmd |= *(u8 *)priv->tx_buf;
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- bytecount++;
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- priv->len--;
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- priv->tx_buf = (u8 *)priv->tx_buf + 1;
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+ gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->addr.buswidth);
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+ gen_fifo_cmd |= GQSPI_GFIFO_TX;
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+ gen_fifo_cmd |= addr;
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debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
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zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
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}
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+
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+ /* Send dummy */
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+ if (op->dummy.nbytes) {
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+ dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
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+
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+ gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
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+ gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->dummy.buswidth);
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+ gen_fifo_cmd &= ~(GQSPI_GFIFO_TX | GQSPI_GFIFO_RX);
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+ gen_fifo_cmd |= GQSPI_GFIFO_DATA_XFR_MASK;
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+ gen_fifo_cmd |= dummy_cycles;
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+ zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
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+ }
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}
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static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
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@@ -497,11 +532,10 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
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int ret = 0;
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gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
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+ gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
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gen_fifo_cmd |= GQSPI_GFIFO_TX |
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GQSPI_GFIFO_DATA_XFR_MASK;
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- gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
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-
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while (priv->len) {
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len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
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zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
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@@ -575,11 +609,10 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
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u32 actuallen = priv->len;
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gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
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+ gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
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gen_fifo_cmd |= GQSPI_GFIFO_RX |
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GQSPI_GFIFO_DATA_XFR_MASK;
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- gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
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-
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/*
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* Check if receive buffer is aligned to 4 byte and length
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* is multiples of four byte as we are using dma to receive.
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@@ -596,62 +629,6 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
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return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
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}
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-static int zynqmp_qspi_start_transfer(struct zynqmp_qspi_priv *priv)
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-{
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- int ret = 0;
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-
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- if (priv->is_inst) {
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- if (priv->tx_buf)
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- zynqmp_qspi_genfifo_cmd(priv);
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- else
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- return -EINVAL;
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- } else {
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- if (priv->tx_buf)
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- ret = zynqmp_qspi_genfifo_fill_tx(priv);
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- else if (priv->rx_buf)
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- ret = zynqmp_qspi_genfifo_fill_rx(priv);
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- else
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- return -EINVAL;
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- }
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- return ret;
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-}
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-
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-static int zynqmp_qspi_transfer(struct zynqmp_qspi_priv *priv)
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-{
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- static unsigned int cs_change = 1;
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- int status = 0;
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-
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- debug("%s\n", __func__);
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-
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- while (1) {
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- /* Select the chip if required */
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- if (cs_change)
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- zynqmp_qspi_chipselect(priv, 1);
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-
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- cs_change = priv->cs_change;
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-
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- if (!priv->tx_buf && !priv->rx_buf && priv->len) {
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- status = -EINVAL;
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- break;
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- }
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-
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- /* Request the transfer */
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- if (priv->len) {
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- status = zynqmp_qspi_start_transfer(priv);
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- priv->is_inst = 0;
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- if (status < 0)
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- break;
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- }
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-
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- if (cs_change)
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- /* Deselect the chip */
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- zynqmp_qspi_chipselect(priv, 0);
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- break;
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- }
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-
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- return status;
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-}
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-
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static int zynqmp_qspi_claim_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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@@ -674,45 +651,43 @@ static int zynqmp_qspi_release_bus(struct udevice *dev)
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return 0;
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}
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-int zynqmp_qspi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout,
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- void *din, unsigned long flags)
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+static int zynqmp_qspi_exec_op(struct spi_slave *slave,
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+ const struct spi_mem_op *op)
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{
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- struct udevice *bus = dev->parent;
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- struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
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+ struct zynqmp_qspi_priv *priv = dev_get_priv(slave->dev->parent);
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+ int ret = 0;
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- debug("%s: priv: 0x%08lx bitlen: %d dout: 0x%08lx ", __func__,
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- (unsigned long)priv, bitlen, (unsigned long)dout);
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- debug("din: 0x%08lx flags: 0x%lx\n", (unsigned long)din, flags);
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+ priv->op = op;
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+ priv->tx_buf = op->data.buf.out;
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+ priv->rx_buf = op->data.buf.in;
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+ priv->len = op->data.nbytes;
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- priv->tx_buf = dout;
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- priv->rx_buf = din;
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- priv->len = bitlen / 8;
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+ zynqmp_qspi_chipselect(priv, 1);
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- /*
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- * Assume that the beginning of a transfer with bits to
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- * transmit must contain a device command.
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- */
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- if (dout && flags & SPI_XFER_BEGIN)
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- priv->is_inst = 1;
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- else
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- priv->is_inst = 0;
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+ /* Send opcode, addr, dummy */
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+ zynqmp_qspi_genfifo_cmd(priv);
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- if (flags & SPI_XFER_END)
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- priv->cs_change = 1;
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- else
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- priv->cs_change = 0;
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+ /* Request the transfer */
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+ if (op->data.dir == SPI_MEM_DATA_IN)
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+ ret = zynqmp_qspi_genfifo_fill_rx(priv);
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+ else if (op->data.dir == SPI_MEM_DATA_OUT)
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+ ret = zynqmp_qspi_genfifo_fill_tx(priv);
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- zynqmp_qspi_transfer(priv);
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+ zynqmp_qspi_chipselect(priv, 0);
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- return 0;
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+ return ret;
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}
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+static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
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+ .exec_op = zynqmp_qspi_exec_op,
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+};
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+
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static const struct dm_spi_ops zynqmp_qspi_ops = {
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.claim_bus = zynqmp_qspi_claim_bus,
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.release_bus = zynqmp_qspi_release_bus,
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- .xfer = zynqmp_qspi_xfer,
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.set_speed = zynqmp_qspi_set_speed,
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.set_mode = zynqmp_qspi_set_mode,
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+ .mem_ops = &zynqmp_qspi_mem_ops,
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};
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static const struct udevice_id zynqmp_qspi_ids[] = {
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