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@@ -659,7 +659,20 @@
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status = "disabled";
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};
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- i2c5: i2c5@12050000 {
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+ i2c2: i2c@10050000 {
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+ compatible = "snps,designware-i2c";
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+ reg = <0x0 0x10050000 0x0 0x10000>;
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+ clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
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+ <&clkgen JH7110_I2C2_CLK_APB>;
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+ clock-names = "ref", "pclk";
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+ resets = <&rstgen RSTN_U2_DW_I2C_APB>;
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+ interrupts = <37>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c5: i2c@12050000 {
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compatible = "snps,designware-i2c";
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reg = <0x0 0x12050000 0x0 0x10000>;
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clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
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@@ -1270,126 +1283,177 @@
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reg = <0 0x295B0000 0 0x90>;
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};
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- hdmi_output: hdmi-output {
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- compatible = "verisilicon,hdmi-encoder";
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- verisilicon,dss-syscon = <&dssctrl>;
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- verisilicon,mux-mask = <0x70 0x380>;
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- verisilicon,mux-val = <0x40 0x280>;
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- status = "disabled";
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- };
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-
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dc8200: dc8200@29400000 {
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- compatible = "verisilicon,dc8200";
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+ compatible = "starfive,sf-dc8200";
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reg = <0x0 0x29400000 0x0 0x100>,
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- <0x0 0x29400800 0x0 0x2000>,
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- <0x0 0x17030000 0x0 0x1000>;
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- interrupts = <95>;
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- status = "disabled";
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- clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
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- <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
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- <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
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- <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
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- <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
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- <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
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- <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
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- <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
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- <&clkgen JH7110_VOUT_SRC>,
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- <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
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- <&clkgen JH7110_AHB1>,
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- <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
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- <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
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- <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
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- <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
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- <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
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- <&clkvout JH7110_U0_DC8200_CLK_AXI>,
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- <&clkvout JH7110_U0_DC8200_CLK_CORE>,
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- <&clkvout JH7110_U0_DC8200_CLK_AHB>;
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- clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
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- "noc_disp","noc_isp","noc_stg","vout_src",
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- "top_vout_axi","ahb1","top_vout_ahb",
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- "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
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- "axi_clk","core_clk","vout_ahb";
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+ <0x0 0x29400800 0x0 0x2000>;
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+ reg-names = "hi", "low";
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+ status = "okay";
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+ clocks = <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
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+ <&clkgen JH7110_VOUT_SRC>,
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+ <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
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+ <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
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+ <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
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+ <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
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+ <&clkvout JH7110_U0_DC8200_CLK_AXI>,
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+ <&clkvout JH7110_U0_DC8200_CLK_CORE>,
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+ <&clkvout JH7110_U0_DC8200_CLK_AHB>,
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+ <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
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+ <&hdmitx0_pixelclk>,
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+ <&clkvout JH7110_DC8200_PIX0>,
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+ <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
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+ <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
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+ clock-names = "disp_axi","vout_src",
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+ "top_vout_axi","top_vout_ahb",
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+ "dc_pix0","dc_pix1",
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+ "dc_axi","dc_core","dc_ahb",
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+ "top_vout_lcd","hdmitx0_pixelclk","dc8200_pix0",
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+ "dc8200_pix0_out","dc8200_pix1_out";
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resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
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<&rstgen RSTN_U0_DC8200_AXI>,
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<&rstgen RSTN_U0_DC8200_AHB>,
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<&rstgen RSTN_U0_DC8200_CORE>,
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- <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
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- <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
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- <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
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- <&rstgen RSTN_U0_NOC_BUS_GPU_AXI_N>,
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- <&rstgen RSTN_U0_NOC_BUS_VDEC_AXI_N>,
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- <&rstgen RSTN_U0_JTAG2APB_PRESETN>,
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- <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
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- <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>,
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- <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>,
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- <&rstgen RSTN_U0_NOC_BUS_DDRC_N>;
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+ <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>;
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reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
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- "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
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- "rst_noc_gpu","rst_noc_vdec","rst_jtag2apb",
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- "rst_noc_disp","rst_noc_isp","rst_noc_stg","rst_noc_ddrc";
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+ "rst_noc_disp";
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+
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+ vopb_out: port {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ vopb_out_mipi: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&mipi_in_vopb>;
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+ };
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+
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+ vopb_out_hdmi: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&hdmi_in_vopb>;
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+ };
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+
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+ vopb_out_lvds: endpoint@2 {
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+ reg = <2>;
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+ remote-endpoint = <&lvds_in_vopb>;
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+ };
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+
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+ vopb_out_edp: endpoint@3 {
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+ reg = <3>;
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+ remote-endpoint = <&edp_in_vopb>;
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+ };
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+ };
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};
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- mipi_dphy: mipi-dphy@295e0000{
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- compatible = "starfive,jh7100-mipi-dphy-tx";
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- reg = <0x0 0x295e0000 0x0 0x10000>;
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- clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
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- clock-names = "dphy_txesc";
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- resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
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- <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
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- reset-names = "dphy_sys", "dphy_txbytehs";
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- #phy-cells = <0>;
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- status = "disabled";
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+ edp: edp@29600000 {
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+ compatible = "rockchip,rk3288-edp";
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+ reg = <0x0 0x29600000 0x0 0x4000>;
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+ status = "okay";
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+ ports {
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+ edp_in: port {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ edp_in_vopb: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&vopb_out_edp>;
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+ };
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+ };
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+ };
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+ };
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+
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+ hdmi: hdmi@29590000 {
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+ compatible = "rockchip,rk3288-dw-hdmi";
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+ reg = <0x0 0x29590000 0x0 0x4000>;
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+ status = "okay";
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+ ports {
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+ hdmi_in: port {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ hdmi_in_vopb: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&vopb_out_hdmi>;
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+ };
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+ };
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+ };
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};
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- mipi_dsi: mipi@295d0000 {
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- compatible = "cdns,dsi";
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- reg = <0x0 0x295d0000 0x0 0x10000>;
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- reg-names = "dsi";
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+ lvds: lvds@ff96c000 {
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+ compatible = "rockchip,rk3288-lvds";
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+ reg = <0x0 0xff96c000 0x0 0x4000>;
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+ status = "okay";
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ lvds_in: port@0 {
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+ reg = <0>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ lvds_in_vopb: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&vopb_out_lvds>;
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+ };
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+ };
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+ };
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+ };
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+
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+ mipi_dsi0: mipi@295d0000 {
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+ compatible = "starfive,sf_mipi_dsi";
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+ reg = <0x0 0x295d0000 0x0 0x10000>,
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+ <0x0 0x295e0000 0x0 0x10000>,
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+ <0x0 0x17010000 0x0 0x1000>;
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+ reg-names = "dsi", "phy", "syscon";
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clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
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<&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
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<&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
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- <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
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- clock-names = "sys", "apb", "txesc", "dpi";
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+ <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>,
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+ <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
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+ clock-names = "sys", "apb", "txesc", "dpi","dphy_txesc";
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resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
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<&rstgen RSTN_U0_CDNS_DSITX_APB>,
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<&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
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<&rstgen RSTN_U0_CDNS_DSITX_SYS>,
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<&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
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- <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
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+ <&rstgen RSTN_U0_CDNS_DSITX_TXESC>,
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+ <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
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+ <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
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reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
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- "dsi_sys", "dsi_txbytehs", "dsi_txesc";
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- phys = <&mipi_dphy>;
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- phy-names = "dphy";
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- status = "disabled";
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+ "dsi_sys", "dsi_txbytehs", "dsi_txesc",
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+ "dphy_sys", "dphy_txbytehs";
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- port {
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- dsi_out_port: endpoint {
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- /*remote-endpoint = <&panel_dsi_port>;*/
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+ status = "disabled";
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+ ports {
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+ mipi_in: port {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ mipi_in_vopb: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&vopb_out_mipi>;
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+ };
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};
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};
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+ };
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- mipi_panel: panel@0 {
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- /*compatible = "";*/
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- status = "disabled";
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- };
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+ dsi_host: dsi-host {
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+ compatible = "starfive,mipi-dsi";
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+ status = "okay";
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};
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- hdmi: hdmi@29590000 {
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- compatible = "rockchip,rk3036-inno-hdmi";
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- reg = <0x0 0x29590000 0x0 0x4000>;
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- /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
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- /*clocks = <&cru PCLK_HDMI>;*/
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- /*clock-names = "pclk";*/
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- /*pinctrl-names = "default";*/
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- /*pinctrl-0 = <&hdmi_ctl>;*/
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+ hdmi_output: hdmi-output {
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+ compatible = "verisilicon,hdmi-encoder";
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+ verisilicon,dss-syscon = <&dssctrl>;
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+ verisilicon,mux-mask = <0x70 0x380>;
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+ verisilicon,mux-val = <0x40 0x280>;
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+ status = "disabled";
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+ };
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+
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+ mipi_dphy: mipi-dphy@295e0000{
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+ compatible = "starfive,jh7100-mipi-dphy-tx";
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+ reg = <0x0 0x295e0000 0x0 0x10000>;
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+ clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
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+ clock-names = "dphy_txesc";
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+ resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
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+ <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
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+ reset-names = "dphy_sys", "dphy_txbytehs";
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+ #phy-cells = <0>;
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status = "disabled";
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- clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
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- <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
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- <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>;
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- clock-names = "sysclk", "mclk", "bclk";
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- resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
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- reset-names = "hdmi_tx";
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};
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sound: snd-card {
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