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@@ -20,11 +20,11 @@
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struct dram_info {
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#ifdef CONFIG_TPL_BUILD
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- struct rk3328_ddr_pctl_regs *pctl;
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- struct rk3328_ddr_phy_regs *phy;
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+ struct ddr_pctl_regs *pctl;
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+ struct ddr_phy_regs *phy;
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struct clk ddr_clk;
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struct rk3328_cru *cru;
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- struct rk3328_msch_regs *msch;
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+ struct msch_regs *msch;
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struct rk3328_ddr_grf_regs *ddr_grf;
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#endif
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struct ram_info info;
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@@ -71,10 +71,11 @@ static void rkclk_ddr_reset(struct dram_info *dram,
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writel(ddrctrl_asrstn_req(ctl_srstn), &dram->cru->softrst_con[9]);
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}
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-static void rkclk_set_dpll(struct dram_info *dram, unsigned int mhz)
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+static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz)
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{
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unsigned int refdiv, postdiv1, postdiv2, fbdiv;
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int delay = 1000;
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+ u32 mhz = hz / MHZ;
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refdiv = 1;
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if (mhz <= 300) {
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@@ -122,52 +123,7 @@ static void rkclk_configure_ddr(struct dram_info *dram,
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clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7);
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/* for inno ddr phy need 2*freq */
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- rkclk_set_dpll(dram, sdram_params->ddr_freq * 2);
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-}
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-
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-static void phy_soft_reset(struct dram_info *dram)
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-{
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- void __iomem *phy_base = dram->phy;
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-
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- clrbits_le32(PHY_REG(phy_base, 0), 0x3 << 2);
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- udelay(1);
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- setbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET);
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- udelay(5);
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- setbits_le32(PHY_REG(phy_base, 0), DIGITAL_DERESET);
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- udelay(1);
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-}
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-
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-static int pctl_cfg(struct dram_info *dram,
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- struct rk3328_sdram_params *sdram_params)
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-{
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- u32 i;
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- void __iomem *pctl_base = dram->pctl;
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-
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- for (i = 0; sdram_params->pctl_regs.pctl[i][0] != 0xFFFFFFFF; i++) {
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- writel(sdram_params->pctl_regs.pctl[i][1],
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- pctl_base + sdram_params->pctl_regs.pctl[i][0]);
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- }
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- clrsetbits_le32(pctl_base + DDR_PCTL2_PWRTMG,
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- (0xff << 16) | 0x1f,
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- ((SR_IDLE & 0xff) << 16) | (PD_IDLE & 0x1f));
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- /*
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- * dfi_lp_en_pd=1,dfi_lp_wakeup_pd=2
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- * hw_lp_idle_x32=1
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- */
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- if (sdram_params->dramtype == LPDDR3) {
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- setbits_le32(pctl_base + DDR_PCTL2_DFILPCFG0, 1);
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- clrsetbits_le32(pctl_base + DDR_PCTL2_DFILPCFG0,
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- 0xf << 4,
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- 2 << 4);
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- }
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- clrsetbits_le32(pctl_base + DDR_PCTL2_HWLPCTL,
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- 0xfff << 16,
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- 1 << 16);
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- /* disable zqcs */
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- setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1u << 31);
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- setbits_le32(pctl_base + 0x2000 + DDR_PCTL2_ZQCTL0, 1u << 31);
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-
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- return 0;
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+ rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ * 2);
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}
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/* return ddrconfig value
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@@ -175,62 +131,39 @@ static int pctl_cfg(struct dram_info *dram,
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* other, the ddrconfig value
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* only support cs0_row >= cs1_row
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*/
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-static unsigned int calculate_ddrconfig(struct rk3328_sdram_params *sdram_params)
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+static u32 calculate_ddrconfig(struct rk3328_sdram_params *sdram_params)
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{
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- static const u16 ddr_cfg_2_rbc[] = {
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- /***************************
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- * [5:4] row(13+n)
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- * [3] cs(0:0 cs, 1:2 cs)
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- * [2] bank(0:0bank,1:8bank)
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- * [1:0] col(11+n)
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- ****************************/
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- /* row, cs, bank, col */
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- ((3 << 4) | (0 << 3) | (1 << 2) | 0),
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- ((3 << 4) | (0 << 3) | (1 << 2) | 1),
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- ((2 << 4) | (0 << 3) | (1 << 2) | 2),
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- ((3 << 4) | (0 << 3) | (1 << 2) | 2),
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- ((2 << 4) | (0 << 3) | (1 << 2) | 3),
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- ((3 << 4) | (1 << 3) | (1 << 2) | 0),
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- ((3 << 4) | (1 << 3) | (1 << 2) | 1),
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- ((2 << 4) | (1 << 3) | (1 << 2) | 2),
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- ((3 << 4) | (0 << 3) | (0 << 2) | 1),
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- ((2 << 4) | (0 << 3) | (1 << 2) | 1),
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- };
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-
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- static const u16 ddr4_cfg_2_rbc[] = {
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- /***************************
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- * [6] cs 0:0cs 1:2 cs
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- * [5:3] row(13+n)
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- * [2] cs(0:0 cs, 1:2 cs)
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- * [1] bw 0: 16bit 1:32bit
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- * [0] diebw 0:8bit 1:16bit
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- ***************************/
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- /* cs, row, cs, bw, diebw */
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- ((0 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 0),
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- ((1 << 6) | (2 << 3) | (0 << 2) | (1 << 1) | 0),
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- ((0 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 0),
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- ((1 << 6) | (3 << 3) | (0 << 2) | (0 << 1) | 0),
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- ((0 << 6) | (4 << 3) | (0 << 2) | (1 << 1) | 1),
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- ((1 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 1),
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- ((1 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 1),
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- ((0 << 6) | (2 << 3) | (1 << 2) | (1 << 1) | 0),
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- ((0 << 6) | (3 << 3) | (1 << 2) | (0 << 1) | 0),
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- ((0 << 6) | (3 << 3) | (1 << 2) | (1 << 1) | 1),
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- ((0 << 6) | (4 << 3) | (1 << 2) | (0 << 1) | 1),
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- };
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-
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+ struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
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u32 cs, bw, die_bw, col, row, bank;
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+ u32 cs1_row;
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u32 i, tmp;
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u32 ddrconf = -1;
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- cs = sdram_ch.rank;
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- bw = sdram_ch.bw;
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- die_bw = sdram_ch.dbw;
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- col = sdram_ch.col;
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- row = sdram_ch.cs0_row;
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- bank = sdram_ch.bk;
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+ cs = cap_info->rank;
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+ bw = cap_info->bw;
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+ die_bw = cap_info->dbw;
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+ col = cap_info->col;
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+ row = cap_info->cs0_row;
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+ cs1_row = cap_info->cs1_row;
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+ bank = cap_info->bk;
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+
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+ if (sdram_params->base.dramtype == DDR4) {
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+ /* when DDR_TEST, CS always at MSB position for easy test */
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+ if (cs == 2 && row == cs1_row) {
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+ /* include 2cs cap both 2^n or both (2^n - 2^(n-2)) */
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+ tmp = ((row - 13) << 3) | (1 << 2) | (bw & 0x2) |
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+ die_bw;
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+ for (i = 17; i < 21; i++) {
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+ if (((tmp & 0x7) ==
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+ (ddr4_cfg_2_rbc[i - 10] & 0x7)) &&
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+ ((tmp & 0x3c) <=
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+ (ddr4_cfg_2_rbc[i - 10] & 0x3c))) {
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+ ddrconf = i;
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+ goto out;
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+ }
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+ }
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+ }
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- if (sdram_params->dramtype == DDR4) {
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tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw;
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for (i = 10; i < 17; i++) {
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if (((tmp & 0x7) == (ddr4_cfg_2_rbc[i - 10] & 0x7)) &&
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@@ -246,6 +179,18 @@ static unsigned int calculate_ddrconfig(struct rk3328_sdram_params *sdram_params
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goto out;
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}
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+ /* when DDR_TEST, CS always at MSB position for easy test */
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+ if (cs == 2 && row == cs1_row) {
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+ /* include 2cs cap both 2^n or both (2^n - 2^(n-2)) */
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+ for (i = 5; i < 8; i++) {
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+ if ((bw + col - 11) == (ddr_cfg_2_rbc[i] &
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+ 0x3)) {
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+ ddrconf = i;
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+ goto out;
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+ }
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+ }
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+ }
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+
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tmp = ((row - 13) << 4) | (1 << 2) | ((bw + col - 11) << 0);
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for (i = 0; i < 5; i++)
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if (((tmp & 0xf) == (ddr_cfg_2_rbc[i] & 0xf)) &&
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@@ -257,23 +202,11 @@ static unsigned int calculate_ddrconfig(struct rk3328_sdram_params *sdram_params
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out:
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if (ddrconf > 20)
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- printf("calculate_ddrconfig error\n");
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+ printf("calculate ddrconfig error\n");
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return ddrconf;
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}
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-/* n: Unit bytes */
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-static void copy_to_reg(u32 *dest, u32 *src, u32 n)
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-{
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- int i;
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-
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- for (i = 0; i < n / sizeof(u32); i++) {
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- writel(*src, dest);
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- src++;
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- dest++;
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- }
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-}
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-
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/*******
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* calculate controller dram address map, and setting to register.
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* argument sdram_ch.ddrconf must be right value before
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@@ -282,273 +215,42 @@ static void copy_to_reg(u32 *dest, u32 *src, u32 n)
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static void set_ctl_address_map(struct dram_info *dram,
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struct rk3328_sdram_params *sdram_params)
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{
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+ struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
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void __iomem *pctl_base = dram->pctl;
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- copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0),
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- &addrmap[sdram_ch.ddrconfig][0], 9 * 4);
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- if (sdram_params->dramtype == LPDDR3 && sdram_ch.row_3_4)
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+ sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0),
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+ &addrmap[cap_info->ddrconfig][0], 9 * 4);
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+ if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4)
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setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31);
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- if (sdram_params->dramtype == DDR4 && sdram_ch.bw == 0x1)
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+ if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1)
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setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8);
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- if (sdram_ch.rank == 1)
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+ if (cap_info->rank == 1)
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clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f);
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}
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-static void phy_dll_bypass_set(struct dram_info *dram, u32 freq)
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-{
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- u32 tmp;
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- void __iomem *phy_base = dram->phy;
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-
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- setbits_le32(PHY_REG(phy_base, 0x13), 1 << 4);
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- clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3);
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- setbits_le32(PHY_REG(phy_base, 0x26), 1 << 4);
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- clrbits_le32(PHY_REG(phy_base, 0x27), 1 << 3);
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- setbits_le32(PHY_REG(phy_base, 0x36), 1 << 4);
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- clrbits_le32(PHY_REG(phy_base, 0x37), 1 << 3);
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- setbits_le32(PHY_REG(phy_base, 0x46), 1 << 4);
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- clrbits_le32(PHY_REG(phy_base, 0x47), 1 << 3);
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- setbits_le32(PHY_REG(phy_base, 0x56), 1 << 4);
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- clrbits_le32(PHY_REG(phy_base, 0x57), 1 << 3);
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-
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- if (freq <= 400)
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- /* DLL bypass */
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- setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f);
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- else
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- clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f);
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- if (freq <= 680)
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- tmp = 2;
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- else
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- tmp = 1;
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- writel(tmp, PHY_REG(phy_base, 0x28));
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- writel(tmp, PHY_REG(phy_base, 0x38));
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- writel(tmp, PHY_REG(phy_base, 0x48));
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- writel(tmp, PHY_REG(phy_base, 0x58));
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-}
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-
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-static void set_ds_odt(struct dram_info *dram,
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- struct rk3328_sdram_params *sdram_params)
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-{
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- u32 cmd_drv, clk_drv, dqs_drv, dqs_odt;
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- void __iomem *phy_base = dram->phy;
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-
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- if (sdram_params->dramtype == DDR3) {
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- cmd_drv = PHY_DDR3_RON_RTT_34ohm;
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- clk_drv = PHY_DDR3_RON_RTT_45ohm;
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- dqs_drv = PHY_DDR3_RON_RTT_34ohm;
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- dqs_odt = PHY_DDR3_RON_RTT_225ohm;
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- } else {
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- cmd_drv = PHY_DDR4_LPDDR3_RON_RTT_34ohm;
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- clk_drv = PHY_DDR4_LPDDR3_RON_RTT_43ohm;
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- dqs_drv = PHY_DDR4_LPDDR3_RON_RTT_34ohm;
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- dqs_odt = PHY_DDR4_LPDDR3_RON_RTT_240ohm;
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- }
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- /* DS */
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- writel(cmd_drv, PHY_REG(phy_base, 0x11));
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- clrsetbits_le32(PHY_REG(phy_base, 0x12), 0x1f << 3, cmd_drv << 3);
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- writel(clk_drv, PHY_REG(phy_base, 0x16));
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- writel(clk_drv, PHY_REG(phy_base, 0x18));
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- writel(dqs_drv, PHY_REG(phy_base, 0x20));
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- writel(dqs_drv, PHY_REG(phy_base, 0x2f));
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- writel(dqs_drv, PHY_REG(phy_base, 0x30));
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- writel(dqs_drv, PHY_REG(phy_base, 0x3f));
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- writel(dqs_drv, PHY_REG(phy_base, 0x40));
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- writel(dqs_drv, PHY_REG(phy_base, 0x4f));
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- writel(dqs_drv, PHY_REG(phy_base, 0x50));
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- writel(dqs_drv, PHY_REG(phy_base, 0x5f));
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- /* ODT */
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- writel(dqs_odt, PHY_REG(phy_base, 0x21));
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- writel(dqs_odt, PHY_REG(phy_base, 0x2e));
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- writel(dqs_odt, PHY_REG(phy_base, 0x31));
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- writel(dqs_odt, PHY_REG(phy_base, 0x3e));
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- writel(dqs_odt, PHY_REG(phy_base, 0x41));
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- writel(dqs_odt, PHY_REG(phy_base, 0x4e));
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- writel(dqs_odt, PHY_REG(phy_base, 0x51));
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- writel(dqs_odt, PHY_REG(phy_base, 0x5e));
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-}
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-
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-static void phy_cfg(struct dram_info *dram,
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- struct rk3328_sdram_params *sdram_params)
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-{
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- u32 i;
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- void __iomem *phy_base = dram->phy;
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-
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- phy_dll_bypass_set(dram, sdram_params->ddr_freq);
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- for (i = 0; sdram_params->phy_regs.phy[i][0] != 0xFFFFFFFF; i++) {
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- writel(sdram_params->phy_regs.phy[i][1],
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- phy_base + sdram_params->phy_regs.phy[i][0]);
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- }
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- if (sdram_ch.bw == 2) {
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- clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4);
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- } else {
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- clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4);
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- /* disable DQS2,DQS3 tx dll for saving power */
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- clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3);
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- clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3);
|
|
|
- }
|
|
|
- set_ds_odt(dram, sdram_params);
|
|
|
- /* deskew */
|
|
|
- setbits_le32(PHY_REG(phy_base, 2), 8);
|
|
|
- copy_to_reg(PHY_REG(phy_base, 0xb0),
|
|
|
- &sdram_params->skew.a0_a1_skew[0], 15 * 4);
|
|
|
- copy_to_reg(PHY_REG(phy_base, 0x70),
|
|
|
- &sdram_params->skew.cs0_dm0_skew[0], 44 * 4);
|
|
|
- copy_to_reg(PHY_REG(phy_base, 0xc0),
|
|
|
- &sdram_params->skew.cs1_dm0_skew[0], 44 * 4);
|
|
|
-}
|
|
|
-
|
|
|
-static int update_refresh_reg(struct dram_info *dram)
|
|
|
-{
|
|
|
- void __iomem *pctl_base = dram->pctl;
|
|
|
- u32 ret;
|
|
|
-
|
|
|
- ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1);
|
|
|
- writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3);
|
|
|
-
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
static int data_training(struct dram_info *dram, u32 cs, u32 dramtype)
|
|
|
-{
|
|
|
- u32 ret;
|
|
|
- u32 dis_auto_zq = 0;
|
|
|
- void __iomem *pctl_base = dram->pctl;
|
|
|
- void __iomem *phy_base = dram->phy;
|
|
|
-
|
|
|
- /* disable zqcs */
|
|
|
- if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) &
|
|
|
- (1ul << 31))) {
|
|
|
- dis_auto_zq = 1;
|
|
|
- setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
|
|
|
- }
|
|
|
- /* disable auto refresh */
|
|
|
- setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
|
|
|
- update_refresh_reg(dram);
|
|
|
-
|
|
|
- if (dramtype == DDR4) {
|
|
|
- clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0);
|
|
|
- clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0);
|
|
|
- clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0);
|
|
|
- clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0);
|
|
|
- }
|
|
|
- /* choose training cs */
|
|
|
- clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs));
|
|
|
- /* enable gate training */
|
|
|
- clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1);
|
|
|
- udelay(50);
|
|
|
- ret = readl(PHY_REG(phy_base, 0xff));
|
|
|
- /* disable gate training */
|
|
|
- clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 0);
|
|
|
- /* restore zqcs */
|
|
|
- if (dis_auto_zq)
|
|
|
- clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
|
|
|
- /* restore auto refresh */
|
|
|
- clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
|
|
|
- update_refresh_reg(dram);
|
|
|
-
|
|
|
- if (dramtype == DDR4) {
|
|
|
- clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0x2);
|
|
|
- clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0x2);
|
|
|
- clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0x2);
|
|
|
- clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0x2);
|
|
|
- }
|
|
|
-
|
|
|
- if (ret & 0x10) {
|
|
|
- ret = -1;
|
|
|
- } else {
|
|
|
- ret = (ret & 0xf) ^ (readl(PHY_REG(phy_base, 0)) >> 4);
|
|
|
- ret = (ret == 0) ? 0 : -1;
|
|
|
- }
|
|
|
- return ret;
|
|
|
-}
|
|
|
-
|
|
|
-/* rank = 1: cs0
|
|
|
- * rank = 2: cs1
|
|
|
- * rank = 3: cs0 & cs1
|
|
|
- * note: be careful of keep mr original val
|
|
|
- */
|
|
|
-static int write_mr(struct dram_info *dram, u32 rank, u32 mr_num, u32 arg,
|
|
|
- u32 dramtype)
|
|
|
{
|
|
|
void __iomem *pctl_base = dram->pctl;
|
|
|
-
|
|
|
- while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
|
|
|
- continue;
|
|
|
- if (dramtype == DDR3 || dramtype == DDR4) {
|
|
|
- writel((mr_num << 12) | (rank << 4) | (0 << 0),
|
|
|
- pctl_base + DDR_PCTL2_MRCTRL0);
|
|
|
- writel(arg, pctl_base + DDR_PCTL2_MRCTRL1);
|
|
|
- } else {
|
|
|
- writel((rank << 4) | (0 << 0),
|
|
|
- pctl_base + DDR_PCTL2_MRCTRL0);
|
|
|
- writel((mr_num << 8) | (arg & 0xff),
|
|
|
- pctl_base + DDR_PCTL2_MRCTRL1);
|
|
|
- }
|
|
|
-
|
|
|
- setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
|
|
|
- while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
|
|
|
- continue;
|
|
|
- while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
|
|
|
- continue;
|
|
|
-
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-/*
|
|
|
- * rank : 1:cs0, 2:cs1, 3:cs0&cs1
|
|
|
- * vrefrate: 4500: 45%,
|
|
|
- */
|
|
|
-static int write_vrefdq(struct dram_info *dram, u32 rank, u32 vrefrate,
|
|
|
- u32 dramtype)
|
|
|
-{
|
|
|
- u32 tccd_l, value;
|
|
|
u32 dis_auto_zq = 0;
|
|
|
- void __iomem *pctl_base = dram->pctl;
|
|
|
+ u32 pwrctl;
|
|
|
+ u32 ret;
|
|
|
|
|
|
- if (dramtype != DDR4 || vrefrate < 4500 || vrefrate > 9200)
|
|
|
- return -1;
|
|
|
+ /* disable auto low-power */
|
|
|
+ pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL);
|
|
|
+ writel(0, pctl_base + DDR_PCTL2_PWRCTL);
|
|
|
|
|
|
- tccd_l = (readl(pctl_base + DDR_PCTL2_DRAMTMG4) >> 16) & 0xf;
|
|
|
- tccd_l = (tccd_l - 4) << 10;
|
|
|
+ dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl);
|
|
|
|
|
|
- if (vrefrate > 7500) {
|
|
|
- /* range 1 */
|
|
|
- value = ((vrefrate - 6000) / 65) | tccd_l;
|
|
|
- } else {
|
|
|
- /* range 2 */
|
|
|
- value = ((vrefrate - 4500) / 65) | tccd_l | (1 << 6);
|
|
|
- }
|
|
|
+ ret = phy_data_training(dram->phy, cs, dramtype);
|
|
|
|
|
|
- /* disable zqcs */
|
|
|
- if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) &
|
|
|
- (1ul << 31))) {
|
|
|
- dis_auto_zq = 1;
|
|
|
- setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
|
|
|
- }
|
|
|
- /* disable auto refresh */
|
|
|
- setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
|
|
|
- update_refresh_reg(dram);
|
|
|
-
|
|
|
- /* enable vrefdq calibratin */
|
|
|
- write_mr(dram, rank, 6, value | (1 << 7), dramtype);
|
|
|
- udelay(1);/* tvrefdqe */
|
|
|
- /* write vrefdq value */
|
|
|
- write_mr(dram, rank, 6, value | (1 << 7), dramtype);
|
|
|
- udelay(1);/* tvref_time */
|
|
|
- write_mr(dram, rank, 6, value | (0 << 7), dramtype);
|
|
|
- udelay(1);/* tvrefdqx */
|
|
|
-
|
|
|
- /* restore zqcs */
|
|
|
- if (dis_auto_zq)
|
|
|
- clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
|
|
|
- /* restore auto refresh */
|
|
|
- clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
|
|
|
- update_refresh_reg(dram);
|
|
|
+ pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq);
|
|
|
|
|
|
- return 0;
|
|
|
-}
|
|
|
+ /* restore auto low-power */
|
|
|
+ writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL);
|
|
|
|
|
|
-#define _MAX_(x, y) ((x) > (y) ? (x) : (y))
|
|
|
+ return ret;
|
|
|
+}
|
|
|
|
|
|
static void rx_deskew_switch_adjust(struct dram_info *dram)
|
|
|
{
|
|
@@ -557,7 +259,7 @@ static void rx_deskew_switch_adjust(struct dram_info *dram)
|
|
|
void __iomem *phy_base = dram->phy;
|
|
|
|
|
|
for (i = 0; i < 4; i++)
|
|
|
- gate_val = _MAX_(readl(PHY_REG(phy_base, 0xfb + i)), gate_val);
|
|
|
+ gate_val = MAX(readl(PHY_REG(phy_base, 0xfb + i)), gate_val);
|
|
|
|
|
|
deskew_val = (gate_val >> 3) + 1;
|
|
|
deskew_val = (deskew_val > 0x1f) ? 0x1f : deskew_val;
|
|
@@ -566,8 +268,6 @@ static void rx_deskew_switch_adjust(struct dram_info *dram)
|
|
|
(deskew_val & 0x1c) << 2);
|
|
|
}
|
|
|
|
|
|
-#undef _MAX_
|
|
|
-
|
|
|
static void tx_deskew_switch_adjust(struct dram_info *dram)
|
|
|
{
|
|
|
void __iomem *phy_base = dram->phy;
|
|
@@ -580,40 +280,39 @@ static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig)
|
|
|
writel(ddrconfig, &dram->msch->ddrconf);
|
|
|
}
|
|
|
|
|
|
+static void sdram_msch_config(struct msch_regs *msch,
|
|
|
+ struct sdram_msch_timings *noc_timings)
|
|
|
+{
|
|
|
+ writel(noc_timings->ddrtiming.d32, &msch->ddrtiming);
|
|
|
+
|
|
|
+ writel(noc_timings->ddrmode.d32, &msch->ddrmode);
|
|
|
+ writel(noc_timings->readlatency, &msch->readlatency);
|
|
|
+
|
|
|
+ writel(noc_timings->activate.d32, &msch->activate);
|
|
|
+ writel(noc_timings->devtodev.d32, &msch->devtodev);
|
|
|
+ writel(noc_timings->ddr4timing.d32, &msch->ddr4_timing);
|
|
|
+ writel(noc_timings->agingx0, &msch->aging0);
|
|
|
+ writel(noc_timings->agingx0, &msch->aging1);
|
|
|
+ writel(noc_timings->agingx0, &msch->aging2);
|
|
|
+ writel(noc_timings->agingx0, &msch->aging3);
|
|
|
+ writel(noc_timings->agingx0, &msch->aging4);
|
|
|
+ writel(noc_timings->agingx0, &msch->aging5);
|
|
|
+}
|
|
|
+
|
|
|
static void dram_all_config(struct dram_info *dram,
|
|
|
struct rk3328_sdram_params *sdram_params)
|
|
|
{
|
|
|
- u32 sys_reg = 0, tmp = 0;
|
|
|
-
|
|
|
- set_ddrconfig(dram, sdram_ch.ddrconfig);
|
|
|
-
|
|
|
- sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->dramtype);
|
|
|
- sys_reg |= SYS_REG_ENC_ROW_3_4(sdram_ch.row_3_4, 0);
|
|
|
- sys_reg |= SYS_REG_ENC_RANK(sdram_ch.rank, 0);
|
|
|
- sys_reg |= SYS_REG_ENC_COL(sdram_ch.col, 0);
|
|
|
- sys_reg |= SYS_REG_ENC_BK(sdram_ch.bk, 0);
|
|
|
- SYS_REG_ENC_CS0_ROW(sdram_ch.cs0_row, sys_reg, tmp, 0);
|
|
|
- if (sdram_ch.cs1_row)
|
|
|
- SYS_REG_ENC_CS1_ROW(sdram_ch.cs1_row, sys_reg, tmp, 0);
|
|
|
- sys_reg |= SYS_REG_ENC_BW(sdram_ch.bw, 0);
|
|
|
- sys_reg |= SYS_REG_ENC_DBW(sdram_ch.dbw, 0);
|
|
|
-
|
|
|
- writel(sys_reg, &dram->grf->os_reg[2]);
|
|
|
-
|
|
|
- writel(sdram_ch.noc_timings.ddrtiming.d32, &dram->msch->ddrtiming);
|
|
|
-
|
|
|
- writel(sdram_ch.noc_timings.ddrmode.d32, &dram->msch->ddrmode);
|
|
|
- writel(sdram_ch.noc_timings.readlatency, &dram->msch->readlatency);
|
|
|
-
|
|
|
- writel(sdram_ch.noc_timings.activate.d32, &dram->msch->activate);
|
|
|
- writel(sdram_ch.noc_timings.devtodev.d32, &dram->msch->devtodev);
|
|
|
- writel(sdram_ch.noc_timings.ddr4timing.d32, &dram->msch->ddr4_timing);
|
|
|
- writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging0);
|
|
|
- writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging1);
|
|
|
- writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging2);
|
|
|
- writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging3);
|
|
|
- writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging4);
|
|
|
- writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging5);
|
|
|
+ struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
|
|
|
+ u32 sys_reg2 = 0;
|
|
|
+ u32 sys_reg3 = 0;
|
|
|
+
|
|
|
+ set_ddrconfig(dram, cap_info->ddrconfig);
|
|
|
+ sdram_org_config(cap_info, &sdram_params->base, &sys_reg2,
|
|
|
+ &sys_reg3, 0);
|
|
|
+ writel(sys_reg2, &dram->grf->os_reg[2]);
|
|
|
+ writel(sys_reg3, &dram->grf->os_reg[3]);
|
|
|
+
|
|
|
+ sdram_msch_config(dram->msch, &sdram_ch.noc_timings);
|
|
|
}
|
|
|
|
|
|
static void enable_low_power(struct dram_info *dram,
|
|
@@ -641,6 +340,7 @@ static void enable_low_power(struct dram_info *dram,
|
|
|
static int sdram_init(struct dram_info *dram,
|
|
|
struct rk3328_sdram_params *sdram_params, u32 pre_init)
|
|
|
{
|
|
|
+ struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
|
|
|
void __iomem *pctl_base = dram->pctl;
|
|
|
|
|
|
rkclk_ddr_reset(dram, 1, 1, 1, 1);
|
|
@@ -652,30 +352,18 @@ static int sdram_init(struct dram_info *dram,
|
|
|
*/
|
|
|
rkclk_ddr_reset(dram, 1, 1, 1, 0);
|
|
|
rkclk_configure_ddr(dram, sdram_params);
|
|
|
- if (pre_init == 0) {
|
|
|
- switch (sdram_params->dramtype) {
|
|
|
- case DDR3:
|
|
|
- printf("DDR3\n");
|
|
|
- break;
|
|
|
- case DDR4:
|
|
|
- printf("DDR4\n");
|
|
|
- break;
|
|
|
- case LPDDR3:
|
|
|
- default:
|
|
|
- printf("LPDDR3\n");
|
|
|
- break;
|
|
|
- }
|
|
|
- }
|
|
|
+
|
|
|
/* release phy srst to provide clk to ctrl */
|
|
|
rkclk_ddr_reset(dram, 1, 1, 0, 0);
|
|
|
udelay(10);
|
|
|
- phy_soft_reset(dram);
|
|
|
+ phy_soft_reset(dram->phy);
|
|
|
/* release ctrl presetn, and config ctl registers */
|
|
|
rkclk_ddr_reset(dram, 1, 0, 0, 0);
|
|
|
- pctl_cfg(dram, sdram_params);
|
|
|
- sdram_ch.ddrconfig = calculate_ddrconfig(sdram_params);
|
|
|
+ pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE);
|
|
|
+ cap_info->ddrconfig = calculate_ddrconfig(sdram_params);
|
|
|
set_ctl_address_map(dram, sdram_params);
|
|
|
- phy_cfg(dram, sdram_params);
|
|
|
+ phy_cfg(dram->phy, &sdram_params->phy_regs, &sdram_params->skew,
|
|
|
+ &sdram_params->base, cap_info->bw);
|
|
|
|
|
|
/* enable dfi_init_start to init phy after ctl srstn deassert */
|
|
|
setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4));
|
|
@@ -685,13 +373,18 @@ static int sdram_init(struct dram_info *dram,
|
|
|
continue;
|
|
|
|
|
|
/* do ddr gate training */
|
|
|
- if (data_training(dram, 0, sdram_params->dramtype) != 0) {
|
|
|
+ if (data_training(dram, 0, sdram_params->base.dramtype) != 0) {
|
|
|
+ printf("data training error\n");
|
|
|
+ return -1;
|
|
|
+ }
|
|
|
+ if (data_training(dram, 1, sdram_params->base.dramtype) != 0) {
|
|
|
printf("data training error\n");
|
|
|
return -1;
|
|
|
}
|
|
|
|
|
|
- if (sdram_params->dramtype == DDR4)
|
|
|
- write_vrefdq(dram, 0x3, 5670, sdram_params->dramtype);
|
|
|
+ if (sdram_params->base.dramtype == DDR4)
|
|
|
+ pctl_write_vrefdq(dram->pctl, 0x3, 5670,
|
|
|
+ sdram_params->base.dramtype);
|
|
|
|
|
|
if (pre_init == 0) {
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rx_deskew_switch_adjust(dram);
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@@ -708,7 +401,7 @@ static u64 dram_detect_cap(struct dram_info *dram,
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struct rk3328_sdram_params *sdram_params,
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unsigned char channel)
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{
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- void __iomem *pctl_base = dram->pctl;
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+ struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
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/*
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* for ddr3: ddrconf = 3
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@@ -718,14 +411,10 @@ static u64 dram_detect_cap(struct dram_info *dram,
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*/
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u32 bk, bktmp;
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u32 col, coltmp;
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- u32 row, rowtmp, row_3_4;
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- void __iomem *test_addr, *test_addr1;
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- u32 dbw;
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+ u32 rowtmp;
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u32 cs;
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u32 bw = 1;
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- u64 cap = 0;
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- u32 dram_type = sdram_params->dramtype;
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- u32 pwrctl;
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+ u32 dram_type = sdram_params->base.dramtype;
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if (dram_type != DDR4) {
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/* detect col and bk for ddr3/lpddr3 */
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@@ -733,33 +422,10 @@ static u64 dram_detect_cap(struct dram_info *dram,
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bktmp = 3;
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rowtmp = 16;
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- for (col = coltmp; col >= 9; col -= 1) {
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- writel(0, SDRAM_ADDR);
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- test_addr = (void __iomem *)(SDRAM_ADDR +
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- (1ul << (col + bw - 1ul)));
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- writel(PATTERN, test_addr);
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- if ((readl(test_addr) == PATTERN) &&
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- (readl(SDRAM_ADDR) == 0))
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- break;
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- }
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- if (col == 8) {
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- printf("col error\n");
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+ if (sdram_detect_col(cap_info, coltmp) != 0)
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goto cap_err;
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- }
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-
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- test_addr = (void __iomem *)(SDRAM_ADDR +
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- (1ul << (coltmp + bktmp + bw - 1ul)));
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- writel(0, SDRAM_ADDR);
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- writel(PATTERN, test_addr);
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- if ((readl(test_addr) == PATTERN) &&
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- (readl(SDRAM_ADDR) == 0))
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- bk = 3;
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- else
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- bk = 2;
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- if (dram_type == LPDDR3)
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- dbw = 2;
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- else
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- dbw = 1;
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+ sdram_detect_bank(cap_info, coltmp, bktmp);
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+ sdram_detect_dbw(cap_info, dram_type);
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} else {
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/* detect bg for ddr4 */
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coltmp = 10;
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@@ -768,178 +434,49 @@ static u64 dram_detect_cap(struct dram_info *dram,
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col = 10;
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bk = 2;
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- test_addr = (void __iomem *)(SDRAM_ADDR +
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- (1ul << (coltmp + bw + 1ul)));
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- writel(0, SDRAM_ADDR);
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- writel(PATTERN, test_addr);
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- if ((readl(test_addr) == PATTERN) &&
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- (readl(SDRAM_ADDR) == 0))
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- dbw = 0;
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- else
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- dbw = 1;
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+ cap_info->col = col;
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+ cap_info->bk = bk;
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+ sdram_detect_bg(cap_info, coltmp);
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}
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+
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/* detect row */
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- for (row = rowtmp; row > 12; row--) {
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- writel(0, SDRAM_ADDR);
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- test_addr = (void __iomem *)(SDRAM_ADDR +
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- (1ul << (row + bktmp + coltmp + bw - 1ul)));
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- writel(PATTERN, test_addr);
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- if ((readl(test_addr) == PATTERN) &&
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- (readl(SDRAM_ADDR) == 0))
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- break;
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- }
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- if (row == 12) {
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- printf("row error");
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+ if (sdram_detect_row(cap_info, coltmp, bktmp, rowtmp) != 0)
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goto cap_err;
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- }
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- /* detect row_3_4 */
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- test_addr = SDRAM_ADDR;
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- test_addr1 = (void __iomem *)(SDRAM_ADDR +
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- (0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul)));
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-
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- writel(0, test_addr);
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- writel(PATTERN, test_addr1);
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- if ((readl(test_addr) == 0) &&
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- (readl(test_addr1) == PATTERN))
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- row_3_4 = 0;
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- else
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- row_3_4 = 1;
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- /* disable auto low-power */
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- pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL);
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- writel(0, pctl_base + DDR_PCTL2_PWRCTL);
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+ /* detect row_3_4 */
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+ sdram_detect_row_3_4(cap_info, coltmp, bktmp);
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- /* bw and cs detect using phy read gate training */
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+ /* bw and cs detect using data training */
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if (data_training(dram, 1, dram_type) == 0)
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cs = 1;
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else
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cs = 0;
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+ cap_info->rank = cs + 1;
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bw = 2;
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+ cap_info->bw = bw;
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- /* restore auto low-power */
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- writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL);
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-
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- sdram_ch.rank = cs + 1;
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- sdram_ch.col = col;
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- sdram_ch.bk = bk;
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- sdram_ch.dbw = dbw;
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- sdram_ch.bw = bw;
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- sdram_ch.cs0_row = row;
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- if (cs)
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- sdram_ch.cs1_row = row;
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- else
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- sdram_ch.cs1_row = 0;
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- sdram_ch.row_3_4 = row_3_4;
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-
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- if (dram_type == DDR4)
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- cap = 1llu << (cs + row + bk + col + ((dbw == 0) ? 2 : 1) + bw);
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- else
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- cap = 1llu << (cs + row + bk + col + bw);
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-
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- return cap;
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-
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-cap_err:
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- return 0;
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-}
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-
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-static u32 remodify_sdram_params(struct rk3328_sdram_params *sdram_params)
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-{
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- u32 tmp = 0, tmp_adr = 0, i;
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-
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- for (i = 0; sdram_params->pctl_regs.pctl[i][0] != 0xFFFFFFFF; i++) {
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- if (sdram_params->pctl_regs.pctl[i][0] == 0) {
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- tmp = sdram_params->pctl_regs.pctl[i][1];/* MSTR */
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- tmp_adr = i;
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- }
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- }
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-
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- tmp &= ~((3ul << 30) | (3ul << 24) | (3ul << 12));
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-
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- switch (sdram_ch.dbw) {
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- case 2:
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- tmp |= (3ul << 30);
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- break;
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- case 1:
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- tmp |= (2ul << 30);
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- break;
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- case 0:
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- default:
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- tmp |= (1ul << 30);
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- break;
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+ cap_info->cs0_high16bit_row = cap_info->cs0_row;
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+ if (cs) {
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+ cap_info->cs1_row = cap_info->cs0_row;
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+ cap_info->cs1_high16bit_row = cap_info->cs0_row;
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+ } else {
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+ cap_info->cs1_row = 0;
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+ cap_info->cs1_high16bit_row = 0;
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}
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- if (sdram_ch.rank == 2)
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- tmp |= 3 << 24;
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- else
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- tmp |= 1 << 24;
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-
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- tmp |= (2 - sdram_ch.bw) << 12;
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-
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- sdram_params->pctl_regs.pctl[tmp_adr][1] = tmp;
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-
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- if (sdram_ch.bw == 2)
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- sdram_ch.noc_timings.ddrtiming.b.bwratio = 0;
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- else
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- sdram_ch.noc_timings.ddrtiming.b.bwratio = 1;
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-
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return 0;
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-}
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-
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-static int dram_detect_cs1_row(struct rk3328_sdram_params *sdram_params,
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- unsigned char channel)
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-{
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- u32 ret = 0;
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- u32 cs1_bit;
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- void __iomem *test_addr, *cs1_addr;
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- u32 row, bktmp, coltmp, bw;
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- u32 ddrconf = sdram_ch.ddrconfig;
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-
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- if (sdram_ch.rank == 2) {
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- cs1_bit = addrmap[ddrconf][0] + 8;
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-
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- if (cs1_bit > 31)
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- goto out;
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-
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- cs1_addr = (void __iomem *)(1ul << cs1_bit);
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- if (cs1_bit < 20)
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- cs1_bit = 1;
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- else
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- cs1_bit = 0;
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-
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- if (sdram_params->dramtype == DDR4) {
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- if (sdram_ch.dbw == 0)
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- bktmp = sdram_ch.bk + 2;
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- else
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- bktmp = sdram_ch.bk + 1;
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- } else {
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- bktmp = sdram_ch.bk;
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- }
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- bw = sdram_ch.bw;
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- coltmp = sdram_ch.col;
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-
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- /* detect cs1 row */
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- for (row = sdram_ch.cs0_row; row > 12; row--) {
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- test_addr = (void __iomem *)(SDRAM_ADDR + cs1_addr +
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- (1ul << (row + cs1_bit + bktmp +
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- coltmp + bw - 1ul)));
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- writel(0, SDRAM_ADDR + cs1_addr);
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- writel(PATTERN, test_addr);
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- if ((readl(test_addr) == PATTERN) &&
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- (readl(SDRAM_ADDR + cs1_addr) == 0)) {
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- ret = row;
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- break;
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- }
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- }
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- }
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-
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-out:
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- return ret;
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+cap_err:
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+ return -1;
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}
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static int sdram_init_detect(struct dram_info *dram,
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struct rk3328_sdram_params *sdram_params)
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{
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+ u32 sys_reg = 0;
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+ u32 sys_reg3 = 0;
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+ struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
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+
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debug("Starting SDRAM initialization...\n");
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memcpy(&sdram_ch, &sdram_params->ch,
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@@ -949,13 +486,29 @@ static int sdram_init_detect(struct dram_info *dram,
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dram_detect_cap(dram, sdram_params, 0);
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/* modify bw, cs related timing */
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- remodify_sdram_params(sdram_params);
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+ pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info,
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+ sdram_params->base.dramtype);
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+
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+ if (cap_info->bw == 2)
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+ sdram_ch.noc_timings.ddrtiming.b.bwratio = 0;
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+ else
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+ sdram_ch.noc_timings.ddrtiming.b.bwratio = 1;
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+
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/* reinit sdram by real dram cap */
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sdram_init(dram, sdram_params, 0);
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/* redetect cs1 row */
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- sdram_ch.cs1_row =
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- dram_detect_cs1_row(sdram_params, 0);
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+ sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype);
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+ if (cap_info->cs1_row) {
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+ sys_reg = readl(&dram->grf->os_reg[2]);
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+ sys_reg3 = readl(&dram->grf->os_reg[3]);
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+ SYS_REG_ENC_CS1_ROW(cap_info->cs1_row,
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+ sys_reg, sys_reg3, 0);
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+ writel(sys_reg, &dram->grf->os_reg[2]);
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+ writel(sys_reg3, &dram->grf->os_reg[3]);
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+ }
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+
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+ sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base);
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return 0;
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}
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