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@@ -0,0 +1,180 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (c) 2019 MediaTek Inc.
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+ * Author: Sam Shih <sam.shih@mediatek.com>
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+ */
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+
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+/dts-v1/;
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+#include "mt7622.dtsi"
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+#include "mt7622-u-boot.dtsi"
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+
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+/ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ model = "mt7622-rfb";
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+ compatible = "mediatek,mt7622", "mediatek,mt7622-rfb";
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+ chosen {
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+ stdout-path = &uart0;
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+ tick-timer = &timer0;
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+ };
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+
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+ aliases {
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+ spi0 = &snfi;
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+ };
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+
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+ memory@40000000 {
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+ device_type = "memory";
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+ reg = <0x40000000 0x10000000>;
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+ };
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+
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+ reg_1p8v: regulator-1p8v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-1.8V";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+
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+ reg_3p3v: regulator-3p3v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-3.3V";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+};
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+
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+
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+&pinctrl {
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+ snfi_pins: snfi-pins {
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+ mux {
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+ function = "flash";
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+ groups = "snfi";
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+ };
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+ };
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+
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+ snor_pins: snor-pins {
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+ mux {
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+ function = "flash";
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+ groups = "spi_nor";
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+ };
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+ };
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+
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+ uart0_pins: uart0 {
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+ mux {
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+ function = "uart";
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+ groups = "uart0_0_tx_rx" ;
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+ };
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+ };
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+
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+ watchdog_pins: watchdog-default {
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+ mux {
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+ function = "watchdog";
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+ groups = "watchdog";
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+ };
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+ };
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+
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+ mmc0_pins_default: mmc0default {
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+ mux {
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+ function = "emmc";
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+ groups = "emmc";
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+ };
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+
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+ /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
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+ * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
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+ * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
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+ */
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+ conf-cmd-dat {
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+ pins = "NDL0", "NDL1", "NDL2",
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+ "NDL3", "NDL4", "NDL5",
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+ "NDL6", "NDL7", "NRB";
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+ input-enable;
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+ bias-pull-up;
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+ };
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+
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+ conf-clk {
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+ pins = "NCLE";
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+ bias-pull-down;
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+ };
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+
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+ };
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+
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+ mmc1_pins_default: mmc1default {
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+ mux {
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+ function = "sd";
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+ groups = "sd_0";
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+ };
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+ /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
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+ * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
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+ * DAT2, DAT3, CMD, CLK for SD respectively.
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+ */
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+ conf-cmd-data {
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+ pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
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+ "I2S2_IN","I2S4_OUT";
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+ input-enable;
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+ drive-strength = <8>;
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+ bias-pull-up;
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+ };
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+ conf-clk {
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+ pins = "I2S3_OUT";
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+ drive-strength = <12>;
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+ bias-pull-down;
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+ };
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+ conf-cd {
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+ pins = "TXD3";
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+ bias-pull-up;
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+ };
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+
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+ };
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+};
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+
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+&snfi {
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+ pinctrl-names = "default", "snfi";
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+ pinctrl-0 = <&snor_pins>;
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+ pinctrl-1 = <&snfi_pins>;
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+ status = "okay";
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+
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+ spi-flash@0{
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+ compatible = "jedec,spi-nor";
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+ reg = <0>;
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+ u-boot,dm-pre-reloc;
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+ };
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+};
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+
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+&uart0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart0_pins>;
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+ status = "okay";
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+};
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+
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+&mmc0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&mmc0_pins_default>;
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+ status = "okay";
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+ bus-width = <8>;
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+ max-frequency = <50000000>;
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+ cap-sd-highspeed;
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+ vmmc-supply = <®_3p3v>;
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+ vqmmc-supply = <®_3p3v>;
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+ non-removable;
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+};
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+
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+&mmc1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&mmc1_pins_default>;
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+ status = "okay";
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+ bus-width = <4>;
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+ max-frequency = <50000000>;
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+ cap-sd-highspeed;
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+ r_smpl = <1>;
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+ vmmc-supply = <®_3p3v>;
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+ vqmmc-supply = <®_3p3v>;
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+};
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+
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+&watchdog {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&watchdog_pins>;
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+ status = "okay";
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+};
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