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@@ -11,60 +11,67 @@
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#include <errno.h>
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#include <log.h>
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#include <malloc.h>
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+#include <dm.h>
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+#include <fdtdec.h>
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#include <part.h>
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#include <mmc.h>
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-#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <mvebu_mmc.h>
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-
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-DECLARE_GLOBAL_DATA_PTR;
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-
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-#define DRIVER_NAME "MVEBU_MMC"
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+#include <dm/device_compat.h>
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#define MVEBU_TARGET_DRAM 0
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#define TIMEOUT_DELAY 5*CONFIG_SYS_HZ /* wait 5 seconds */
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-static void mvebu_mmc_write(u32 offs, u32 val)
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+static inline void *get_regbase(const struct mmc *mmc)
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{
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- writel(val, CONFIG_SYS_MMC_BASE + (offs));
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+ struct mvebu_mmc_plat *pdata = mmc->priv;
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+
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+ return pdata->iobase;
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}
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-static u32 mvebu_mmc_read(u32 offs)
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+static void mvebu_mmc_write(const struct mmc *mmc, u32 offs, u32 val)
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{
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- return readl(CONFIG_SYS_MMC_BASE + (offs));
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+ writel(val, get_regbase(mmc) + (offs));
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}
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-static int mvebu_mmc_setup_data(struct mmc_data *data)
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+static u32 mvebu_mmc_read(const struct mmc *mmc, u32 offs)
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{
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+ return readl(get_regbase(mmc) + (offs));
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+}
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+
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+static int mvebu_mmc_setup_data(struct udevice *dev, struct mmc_data *data)
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+{
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+ struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
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+ struct mmc *mmc = &pdata->mmc;
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u32 ctrl_reg;
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- debug("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME,
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- (data->flags & MMC_DATA_READ) ? "read" : "write",
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- data->blocks, data->blocksize);
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+ dev_dbg(dev, "data %s : blocks=%d blksz=%d\n",
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+ (data->flags & MMC_DATA_READ) ? "read" : "write",
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+ data->blocks, data->blocksize);
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/* default to maximum timeout */
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- ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
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+ ctrl_reg = mvebu_mmc_read(mmc, SDIO_HOST_CTRL);
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ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
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- mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
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+ mvebu_mmc_write(mmc, SDIO_HOST_CTRL, ctrl_reg);
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if (data->flags & MMC_DATA_READ) {
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- mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);
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- mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);
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+ mvebu_mmc_write(mmc, SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);
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+ mvebu_mmc_write(mmc, SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);
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} else {
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- mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);
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- mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->src >> 16);
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+ mvebu_mmc_write(mmc, SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);
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+ mvebu_mmc_write(mmc, SDIO_SYS_ADDR_HI, (u32)data->src >> 16);
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}
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- mvebu_mmc_write(SDIO_BLK_COUNT, data->blocks);
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- mvebu_mmc_write(SDIO_BLK_SIZE, data->blocksize);
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+ mvebu_mmc_write(mmc, SDIO_BLK_COUNT, data->blocks);
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+ mvebu_mmc_write(mmc, SDIO_BLK_SIZE, data->blocksize);
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return 0;
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}
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-static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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+static int mvebu_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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ulong start;
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@@ -72,12 +79,14 @@ static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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ushort resptype = 0;
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ushort xfertype = 0;
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ushort resp_indx = 0;
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+ struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
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+ struct mmc *mmc = &pdata->mmc;
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- debug("%s: cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
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- DRIVER_NAME, cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
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+ dev_dbg(dev, "cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
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+ cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
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- debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME,
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- cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE));
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+ dev_dbg(dev, "cmd %d (hw state 0x%04x)\n",
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+ cmd->cmdidx, mvebu_mmc_read(mmc, SDIO_HW_STATE));
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/*
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* Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
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@@ -88,26 +97,26 @@ static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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* this bit comes to good sense (which eventually happens by
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* itself) then the new transfer simply fails with a timeout.
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*/
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- if (!(mvebu_mmc_read(SDIO_HW_STATE) & CMD_FIFO_EMPTY)) {
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+ if (!(mvebu_mmc_read(mmc, SDIO_HW_STATE) & CMD_FIFO_EMPTY)) {
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ushort hw_state, count = 0;
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start = get_timer(0);
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do {
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- hw_state = mvebu_mmc_read(SDIO_HW_STATE);
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+ hw_state = mvebu_mmc_read(mmc, SDIO_HW_STATE);
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if ((get_timer(0) - start) > TIMEOUT_DELAY) {
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printf("%s : FIFO_EMPTY bit missing\n",
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- DRIVER_NAME);
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+ dev->name);
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break;
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}
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count++;
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} while (!(hw_state & CMD_FIFO_EMPTY));
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- debug("%s *** wait for FIFO_EMPTY bit (hw=0x%04x, count=%d, jiffies=%ld)\n",
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- DRIVER_NAME, hw_state, count, (get_timer(0) - (start)));
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+ dev_dbg(dev, "*** wait for FIFO_EMPTY bit (hw=0x%04x, count=%d, jiffies=%ld)\n",
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+ hw_state, count, (get_timer(0) - (start)));
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}
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/* Clear status */
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- mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
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- mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
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+ mvebu_mmc_write(mmc, SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
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+ mvebu_mmc_write(mmc, SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
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resptype = SDIO_CMD_INDEX(cmd->cmdidx);
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@@ -133,11 +142,10 @@ static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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}
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if (data) {
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- int err = mvebu_mmc_setup_data(data);
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+ int err = mvebu_mmc_setup_data(dev, data);
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if (err) {
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- debug("%s: command DATA error :%x\n",
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- DRIVER_NAME, err);
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+ dev_dbg(dev, "command DATA error :%x\n", err);
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return err;
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}
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@@ -154,34 +162,33 @@ static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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}
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/* Setting cmd arguments */
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- mvebu_mmc_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
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- mvebu_mmc_write(SDIO_ARG_HI, cmd->cmdarg >> 16);
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+ mvebu_mmc_write(mmc, SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
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+ mvebu_mmc_write(mmc, SDIO_ARG_HI, cmd->cmdarg >> 16);
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/* Setting Xfer mode */
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- mvebu_mmc_write(SDIO_XFER_MODE, xfertype);
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+ mvebu_mmc_write(mmc, SDIO_XFER_MODE, xfertype);
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/* Sending command */
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- mvebu_mmc_write(SDIO_CMD, resptype);
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+ mvebu_mmc_write(mmc, SDIO_CMD, resptype);
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start = get_timer(0);
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- while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
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- if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
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- debug("%s: error! cmdidx : %d, err reg: %04x\n",
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- DRIVER_NAME, cmd->cmdidx,
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- mvebu_mmc_read(SDIO_ERR_INTR_STATUS));
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- if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
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+ while (!((mvebu_mmc_read(mmc, SDIO_NOR_INTR_STATUS)) & waittype)) {
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+ if (mvebu_mmc_read(mmc, SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
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+ dev_dbg(dev, "error! cmdidx : %d, err reg: %04x\n",
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+ cmd->cmdidx,
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+ mvebu_mmc_read(mmc, SDIO_ERR_INTR_STATUS));
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+ if (mvebu_mmc_read(mmc, SDIO_ERR_INTR_STATUS) &
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(SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) {
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- debug("%s: command READ timed out\n",
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- DRIVER_NAME);
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+ dev_dbg(dev, "command READ timed out\n");
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return -ETIMEDOUT;
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}
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- debug("%s: command READ error\n", DRIVER_NAME);
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+ dev_dbg(dev, "command READ error\n");
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return -ECOMM;
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}
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if ((get_timer(0) - start) > TIMEOUT_DELAY) {
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- debug("%s: command timed out\n", DRIVER_NAME);
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+ dev_dbg(dev, "command timed out\n");
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return -ETIMEDOUT;
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}
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}
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@@ -191,8 +198,7 @@ static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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uint response[8];
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for (resp_indx = 0; resp_indx < 8; resp_indx++)
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- response[resp_indx]
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- = mvebu_mmc_read(SDIO_RSP(resp_indx));
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+ response[resp_indx] = mvebu_mmc_read(mmc, SDIO_RSP(resp_indx));
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cmd->response[0] = ((response[0] & 0x03ff) << 22) |
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((response[1] & 0xffff) << 6) |
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@@ -209,8 +215,7 @@ static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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uint response[3];
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for (resp_indx = 0; resp_indx < 3; resp_indx++)
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- response[resp_indx]
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- = mvebu_mmc_read(SDIO_RSP(resp_indx));
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+ response[resp_indx] = mvebu_mmc_read(mmc, SDIO_RSP(resp_indx));
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cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) |
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((response[1] & 0xffff) << (14 - 8)) |
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@@ -225,64 +230,71 @@ static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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cmd->response[3] = 0;
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}
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- debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
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+ dev_dbg(dev, "resp[0x%x] ", cmd->resp_type);
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debug("[0x%x] ", cmd->response[0]);
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debug("[0x%x] ", cmd->response[1]);
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debug("[0x%x] ", cmd->response[2]);
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debug("[0x%x] ", cmd->response[3]);
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debug("\n");
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- if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
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+ if (mvebu_mmc_read(mmc, SDIO_ERR_INTR_STATUS) &
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(SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
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return -ETIMEDOUT;
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return 0;
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}
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-static void mvebu_mmc_power_up(void)
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+static void mvebu_mmc_power_up(struct udevice *dev)
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{
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- debug("%s: power up\n", DRIVER_NAME);
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+ struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
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+ struct mmc *mmc = &pdata->mmc;
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+
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+ dev_dbg(dev, "power up\n");
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/* disable interrupts */
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- mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
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- mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
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+ mvebu_mmc_write(mmc, SDIO_NOR_INTR_EN, 0);
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+ mvebu_mmc_write(mmc, SDIO_ERR_INTR_EN, 0);
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/* SW reset */
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- mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
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+ mvebu_mmc_write(mmc, SDIO_SW_RESET, SDIO_SW_RESET_NOW);
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- mvebu_mmc_write(SDIO_XFER_MODE, 0);
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+ mvebu_mmc_write(mmc, SDIO_XFER_MODE, 0);
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/* enable status */
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- mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
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- mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
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+ mvebu_mmc_write(mmc, SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
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+ mvebu_mmc_write(mmc, SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
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/* enable interrupts status */
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- mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
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- mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
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+ mvebu_mmc_write(mmc, SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
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+ mvebu_mmc_write(mmc, SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
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}
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-static void mvebu_mmc_set_clk(unsigned int clock)
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+static void mvebu_mmc_set_clk(struct udevice *dev, unsigned int clock)
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{
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unsigned int m;
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+ struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
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+ struct mmc *mmc = &pdata->mmc;
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if (clock == 0) {
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- debug("%s: clock off\n", DRIVER_NAME);
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- mvebu_mmc_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
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- mvebu_mmc_write(SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);
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+ dev_dbg(dev, "clock off\n");
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+ mvebu_mmc_write(mmc, SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
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+ mvebu_mmc_write(mmc, SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);
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} else {
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m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1;
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if (m > MVEBU_MMC_BASE_DIV_MAX)
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m = MVEBU_MMC_BASE_DIV_MAX;
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- mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
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- debug("%s: clock (%d) div : %d\n", DRIVER_NAME, clock, m);
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+ mvebu_mmc_write(mmc, SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
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+ dev_dbg(dev, "clock (%d) div : %d\n", clock, m);
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}
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}
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-static void mvebu_mmc_set_bus(unsigned int bus)
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+static void mvebu_mmc_set_bus(struct udevice *dev, unsigned int bus)
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{
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+ struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
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+ struct mmc *mmc = &pdata->mmc;
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u32 ctrl_reg = 0;
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- ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
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+ ctrl_reg = mvebu_mmc_read(mmc, SDIO_HOST_CTRL);
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ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
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switch (bus) {
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@@ -306,23 +318,26 @@ static void mvebu_mmc_set_bus(unsigned int bus)
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ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
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- debug("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg,
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- (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
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- "push-pull" : "open-drain",
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- (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
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- "4bit-width" : "1bit-width",
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- (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
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- "high-speed" : "");
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+ dev_dbg(dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
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+ (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
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+ "push-pull" : "open-drain",
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+ (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
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+ "4bit-width" : "1bit-width",
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+ (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
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|
+ "high-speed" : "");
|
|
|
|
|
|
- mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
|
|
|
+ mvebu_mmc_write(mmc, SDIO_HOST_CTRL, ctrl_reg);
|
|
|
}
|
|
|
|
|
|
-static int mvebu_mmc_set_ios(struct mmc *mmc)
|
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|
+static int mvebu_mmc_set_ios(struct udevice *dev)
|
|
|
{
|
|
|
- debug("%s: bus[%d] clock[%d]\n", DRIVER_NAME,
|
|
|
- mmc->bus_width, mmc->clock);
|
|
|
- mvebu_mmc_set_bus(mmc->bus_width);
|
|
|
- mvebu_mmc_set_clk(mmc->clock);
|
|
|
+ struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
|
|
|
+ struct mmc *mmc = &pdata->mmc;
|
|
|
+
|
|
|
+ dev_dbg(dev, "bus[%d] clock[%d]\n",
|
|
|
+ mmc->bus_width, mmc->clock);
|
|
|
+ mvebu_mmc_set_bus(dev, mmc->bus_width);
|
|
|
+ mvebu_mmc_set_clk(dev, mmc->clock);
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
@@ -330,13 +345,13 @@ static int mvebu_mmc_set_ios(struct mmc *mmc)
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|
/*
|
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|
* Set window register.
|
|
|
*/
|
|
|
-static void mvebu_window_setup(void)
|
|
|
+static void mvebu_window_setup(const struct mmc *mmc)
|
|
|
{
|
|
|
int i;
|
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
- mvebu_mmc_write(WINDOW_CTRL(i), 0);
|
|
|
- mvebu_mmc_write(WINDOW_BASE(i), 0);
|
|
|
+ mvebu_mmc_write(mmc, WINDOW_CTRL(i), 0);
|
|
|
+ mvebu_mmc_write(mmc, WINDOW_BASE(i), 0);
|
|
|
}
|
|
|
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
|
|
|
u32 size, base, attrib;
|
|
@@ -364,79 +379,119 @@ static void mvebu_window_setup(void)
|
|
|
size = gd->bd->bi_dram[i].size;
|
|
|
base = gd->bd->bi_dram[i].start;
|
|
|
if (size && attrib) {
|
|
|
- mvebu_mmc_write(WINDOW_CTRL(i),
|
|
|
+ mvebu_mmc_write(mmc, WINDOW_CTRL(i),
|
|
|
MVCPU_WIN_CTRL_DATA(size,
|
|
|
MVEBU_TARGET_DRAM,
|
|
|
attrib,
|
|
|
MVCPU_WIN_ENABLE));
|
|
|
} else {
|
|
|
- mvebu_mmc_write(WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
|
|
|
+ mvebu_mmc_write(mmc, WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
|
|
|
}
|
|
|
- mvebu_mmc_write(WINDOW_BASE(i), base);
|
|
|
+ mvebu_mmc_write(mmc, WINDOW_BASE(i), base);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
-static int mvebu_mmc_initialize(struct mmc *mmc)
|
|
|
+static int mvebu_mmc_initialize(struct udevice *dev)
|
|
|
{
|
|
|
- debug("%s: mvebu_mmc_initialize\n", DRIVER_NAME);
|
|
|
+ struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
|
|
|
+ struct mmc *mmc = &pdata->mmc;
|
|
|
+
|
|
|
+ dev_dbg(dev, "%s\n", __func__);
|
|
|
|
|
|
/*
|
|
|
* Setting host parameters
|
|
|
* Initial Host Ctrl : Timeout : max , Normal Speed mode,
|
|
|
* 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line
|
|
|
*/
|
|
|
- mvebu_mmc_write(SDIO_HOST_CTRL,
|
|
|
+ mvebu_mmc_write(mmc, SDIO_HOST_CTRL,
|
|
|
SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
|
|
|
SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
|
|
|
SDIO_HOST_CTRL_BIG_ENDIAN |
|
|
|
SDIO_HOST_CTRL_PUSH_PULL_EN |
|
|
|
SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
|
|
|
|
|
|
- mvebu_mmc_write(SDIO_CLK_CTRL, 0);
|
|
|
+ mvebu_mmc_write(mmc, SDIO_CLK_CTRL, 0);
|
|
|
|
|
|
/* enable status */
|
|
|
- mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
|
|
|
- mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
|
|
|
+ mvebu_mmc_write(mmc, SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
|
|
|
+ mvebu_mmc_write(mmc, SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
|
|
|
|
|
|
/* disable interrupts */
|
|
|
- mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
|
|
|
- mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
|
|
|
+ mvebu_mmc_write(mmc, SDIO_NOR_INTR_EN, 0);
|
|
|
+ mvebu_mmc_write(mmc, SDIO_ERR_INTR_EN, 0);
|
|
|
|
|
|
- mvebu_window_setup();
|
|
|
+ mvebu_window_setup(mmc);
|
|
|
|
|
|
/* SW reset */
|
|
|
- mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
|
|
|
+ mvebu_mmc_write(mmc, SDIO_SW_RESET, SDIO_SW_RESET_NOW);
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
-static const struct mmc_ops mvebu_mmc_ops = {
|
|
|
- .send_cmd = mvebu_mmc_send_cmd,
|
|
|
- .set_ios = mvebu_mmc_set_ios,
|
|
|
- .init = mvebu_mmc_initialize,
|
|
|
-};
|
|
|
+static int mvebu_mmc_of_to_plat(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
|
|
|
+ fdt_addr_t addr;
|
|
|
|
|
|
-static struct mmc_config mvebu_mmc_cfg = {
|
|
|
- .name = DRIVER_NAME,
|
|
|
- .ops = &mvebu_mmc_ops,
|
|
|
- .f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,
|
|
|
- .f_max = MVEBU_MMC_CLOCKRATE_MAX,
|
|
|
- .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
|
|
|
- .host_caps = MMC_MODE_4BIT | MMC_MODE_HS |
|
|
|
- MMC_MODE_HS_52MHz,
|
|
|
- .part_type = PART_TYPE_DOS,
|
|
|
- .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
|
|
|
-};
|
|
|
+ addr = dev_read_addr(dev);
|
|
|
+ if (addr == FDT_ADDR_T_NONE)
|
|
|
+ return -EINVAL;
|
|
|
|
|
|
-int mvebu_mmc_init(struct bd_info *bis)
|
|
|
-{
|
|
|
- struct mmc *mmc;
|
|
|
+ pdata->iobase = (void *)addr;
|
|
|
|
|
|
- mvebu_mmc_power_up();
|
|
|
+ return 0;
|
|
|
+}
|
|
|
|
|
|
- mmc = mmc_create(&mvebu_mmc_cfg, bis);
|
|
|
- if (mmc == NULL)
|
|
|
- return -1;
|
|
|
+static int mvebu_mmc_probe(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
|
|
|
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
|
|
+ struct mmc *mmc = &pdata->mmc;
|
|
|
+ struct mmc_config *cfg = &pdata->cfg;
|
|
|
+
|
|
|
+ cfg->name = dev->name;
|
|
|
+ cfg->f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX;
|
|
|
+ cfg->f_max = MVEBU_MMC_CLOCKRATE_MAX;
|
|
|
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
|
+ cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
|
|
|
+ cfg->part_type = PART_TYPE_DOS;
|
|
|
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
|
|
+
|
|
|
+ mmc->cfg = cfg;
|
|
|
+ mmc->priv = pdata;
|
|
|
+ mmc->dev = dev;
|
|
|
+ upriv->mmc = mmc;
|
|
|
+
|
|
|
+ mvebu_mmc_power_up(dev);
|
|
|
+ mvebu_mmc_initialize(dev);
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
|
+
|
|
|
+static const struct dm_mmc_ops mvebu_dm_mmc_ops = {
|
|
|
+ .send_cmd = mvebu_mmc_send_cmd,
|
|
|
+ .set_ios = mvebu_mmc_set_ios,
|
|
|
+};
|
|
|
+
|
|
|
+static int mvebu_mmc_bind(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
|
|
|
+
|
|
|
+ return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
|
|
|
+}
|
|
|
+
|
|
|
+static const struct udevice_id mvebu_mmc_match[] = {
|
|
|
+ { .compatible = "marvell,orion-sdio" },
|
|
|
+ { /* sentinel */ }
|
|
|
+};
|
|
|
+
|
|
|
+U_BOOT_DRIVER(mvebu_mmc) = {
|
|
|
+ .name = "mvebu_mmc",
|
|
|
+ .id = UCLASS_MMC,
|
|
|
+ .of_match = mvebu_mmc_match,
|
|
|
+ .ops = &mvebu_dm_mmc_ops,
|
|
|
+ .probe = mvebu_mmc_probe,
|
|
|
+ .bind = mvebu_mmc_bind,
|
|
|
+ .of_to_plat = mvebu_mmc_of_to_plat,
|
|
|
+ .plat_auto = sizeof(struct mvebu_mmc_plat),
|
|
|
+};
|