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@@ -0,0 +1,116 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * HSDK SoC Reset Controller driver
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+ *
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+ * Copyright (C) 2019 Synopsys, Inc. All rights reserved.
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+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
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+ */
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+
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+#include <asm/io.h>
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+#include <common.h>
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+#include <dm.h>
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+#include <linux/iopoll.h>
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+#include <reset-uclass.h>
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+
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+struct hsdk_rst {
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+ void __iomem *regs_ctl;
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+ void __iomem *regs_rst;
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+};
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+
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+static const u32 rst_map[] = {
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+ BIT(16), /* APB_RST */
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+ BIT(17), /* AXI_RST */
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+ BIT(18), /* ETH_RST */
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+ BIT(19), /* USB_RST */
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+ BIT(20), /* SDIO_RST */
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+ BIT(21), /* HDMI_RST */
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+ BIT(22), /* GFX_RST */
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+ BIT(25), /* DMAC_RST */
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+ BIT(31), /* EBI_RST */
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+};
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+
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+#define HSDK_MAX_RESETS ARRAY_SIZE(rst_map)
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+
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+#define CGU_SYS_RST_CTRL 0x0
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+#define CGU_IP_SW_RESET 0x0
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+#define CGU_IP_SW_RESET_DELAY_SHIFT 16
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+#define CGU_IP_SW_RESET_DELAY_MASK GENMASK(31, CGU_IP_SW_RESET_DELAY_SHIFT)
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+#define CGU_IP_SW_RESET_DELAY 0
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+#define CGU_IP_SW_RESET_RESET BIT(0)
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+#define SW_RESET_TIMEOUT 10000
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+
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+static void hsdk_reset_config(struct hsdk_rst *rst, unsigned long id)
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+{
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+ writel(rst_map[id], rst->regs_ctl + CGU_SYS_RST_CTRL);
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+}
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+
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+static int hsdk_reset_do(struct hsdk_rst *rst)
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+{
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+ u32 reg;
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+
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+ reg = readl(rst->regs_rst + CGU_IP_SW_RESET);
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+ reg &= ~CGU_IP_SW_RESET_DELAY_MASK;
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+ reg |= CGU_IP_SW_RESET_DELAY << CGU_IP_SW_RESET_DELAY_SHIFT;
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+ reg |= CGU_IP_SW_RESET_RESET;
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+ writel(reg, rst->regs_rst + CGU_IP_SW_RESET);
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+
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+ /* wait till reset bit is back to 0 */
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+ return readl_poll_timeout(rst->regs_rst + CGU_IP_SW_RESET, reg,
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+ !(reg & CGU_IP_SW_RESET_RESET), SW_RESET_TIMEOUT);
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+}
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+
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+static int hsdk_reset_reset(struct reset_ctl *rst_ctl)
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+{
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+ struct udevice *dev = rst_ctl->dev;
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+ struct hsdk_rst *rst = dev_get_priv(dev);
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+
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+ if (rst_ctl->id >= HSDK_MAX_RESETS)
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+ return -EINVAL;
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+
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+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, rst_ctl,
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+ rst_ctl->dev, rst_ctl->id);
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+
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+ hsdk_reset_config(rst, rst_ctl->id);
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+ return hsdk_reset_do(rst);
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+}
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+
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+static int hsdk_reset_noop(struct reset_ctl *rst_ctl)
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+{
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+ return 0;
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+}
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+
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+static const struct reset_ops hsdk_reset_ops = {
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+ .request = hsdk_reset_noop,
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+ .free = hsdk_reset_noop,
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+ .rst_assert = hsdk_reset_noop,
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+ .rst_deassert = hsdk_reset_reset,
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+};
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+
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+static const struct udevice_id hsdk_reset_dt_match[] = {
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+ { .compatible = "snps,hsdk-reset" },
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+ { },
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+};
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+
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+static int hsdk_reset_probe(struct udevice *dev)
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+{
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+ struct hsdk_rst *rst = dev_get_priv(dev);
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+
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+ rst->regs_ctl = dev_remap_addr_index(dev, 0);
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+ if (!rst->regs_ctl)
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+ return -EINVAL;
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+
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+ rst->regs_rst = dev_remap_addr_index(dev, 1);
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+ if (!rst->regs_rst)
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+ return -EINVAL;
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+
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+ return 0;
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+}
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+
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+U_BOOT_DRIVER(hsdk_reset) = {
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+ .name = "hsdk-reset",
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+ .id = UCLASS_RESET,
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+ .of_match = hsdk_reset_dt_match,
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+ .ops = &hsdk_reset_ops,
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+ .probe = hsdk_reset_probe,
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+ .priv_auto_alloc_size = sizeof(struct hsdk_rst),
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+};
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