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@@ -0,0 +1,410 @@
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+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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+/*
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+ * (C) Copyright 2020 SiFive, Inc.
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+ *
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+ * Authors:
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+ * Pragnesh Patel <pragnesh.patel@sifive.com>
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+ */
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+
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+#include <common.h>
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+#include <dm.h>
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+#include <init.h>
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+#include <ram.h>
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+#include <regmap.h>
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+#include <syscon.h>
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+#include <asm/io.h>
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+#include <clk.h>
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+#include <wait_bit.h>
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+#include <linux/bitops.h>
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+
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+#define DENALI_CTL_0 0
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+#define DENALI_CTL_21 21
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+#define DENALI_CTL_120 120
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+#define DENALI_CTL_132 132
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+#define DENALI_CTL_136 136
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+#define DENALI_CTL_170 170
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+#define DENALI_CTL_181 181
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+#define DENALI_CTL_182 182
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+#define DENALI_CTL_184 184
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+#define DENALI_CTL_208 208
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+#define DENALI_CTL_209 209
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+#define DENALI_CTL_210 210
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+#define DENALI_CTL_212 212
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+#define DENALI_CTL_214 214
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+#define DENALI_CTL_216 216
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+#define DENALI_CTL_224 224
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+#define DENALI_CTL_225 225
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+#define DENALI_CTL_260 260
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+
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+#define DENALI_PHY_1152 1152
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+#define DENALI_PHY_1214 1214
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+
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+#define PAYLOAD_DEST 0x80000000
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+#define DDR_MEM_SIZE (8UL * 1024UL * 1024UL * 1024UL)
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+
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+#define DRAM_CLASS_OFFSET 8
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+#define DRAM_CLASS_DDR4 0xA
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+#define OPTIMAL_RMODW_EN_OFFSET 0
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+#define DISABLE_RD_INTERLEAVE_OFFSET 16
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+#define OUT_OF_RANGE_OFFSET 1
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+#define MULTIPLE_OUT_OF_RANGE_OFFSET 2
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+#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
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+#define MC_INIT_COMPLETE_OFFSET 8
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+#define LEVELING_OPERATION_COMPLETED_OFFSET 22
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+#define DFI_PHY_WRLELV_MODE_OFFSET 24
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+#define DFI_PHY_RDLVL_MODE_OFFSET 24
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+#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
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+#define VREF_EN_OFFSET 24
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+#define PORT_ADDR_PROTECTION_EN_OFFSET 0
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+#define AXI0_ADDRESS_RANGE_ENABLE 8
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+#define AXI0_RANGE_PROT_BITS_0_OFFSET 24
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+#define RDLVL_EN_OFFSET 16
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+#define RDLVL_GATE_EN_OFFSET 24
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+#define WRLVL_EN_OFFSET 0
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+
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+#define PHY_RX_CAL_DQ0_0_OFFSET 0
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+#define PHY_RX_CAL_DQ1_0_OFFSET 16
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+
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+struct fu540_ddrctl {
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+ volatile u32 denali_ctl[265];
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+};
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+
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+struct fu540_ddrphy {
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+ volatile u32 denali_phy[1215];
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+};
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+
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+/**
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+ * struct fu540_ddr_info
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+ *
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+ * @dev : pointer for the device
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+ * @info : UCLASS RAM information
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+ * @ctl : DDR controller base address
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+ * @phy : DDR PHY base address
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+ * @ctrl : DDR control base address
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+ * @physical_filter_ctrl : DDR physical filter control base address
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+ */
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+struct fu540_ddr_info {
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+ struct udevice *dev;
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+ struct ram_info info;
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+ struct fu540_ddrctl *ctl;
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+ struct fu540_ddrphy *phy;
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+ struct clk ddr_clk;
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+ u32 *physical_filter_ctrl;
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+};
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+
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+#if defined(CONFIG_SPL_BUILD)
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+struct fu540_ddr_params {
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+ struct fu540_ddrctl pctl_regs;
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+ struct fu540_ddrphy phy_regs;
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+};
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+
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+struct sifive_dmc_plat {
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+ struct fu540_ddr_params ddr_params;
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+};
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+
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+/*
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+ * TODO : It can be possible to use common sdram_copy_to_reg() API
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+ * n: Unit bytes
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+ */
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+static void sdram_copy_to_reg(volatile u32 *dest,
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+ volatile u32 *src, u32 n)
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+{
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+ int i;
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+
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+ for (i = 0; i < n / sizeof(u32); i++) {
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+ writel(*src, dest);
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+ src++;
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+ dest++;
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+ }
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+}
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+
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+static void fu540_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr)
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+{
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+ u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1;
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+
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+ writel(0x0, DENALI_CTL_209 + ctl);
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+ writel(end_addr_16kblocks, DENALI_CTL_210 + ctl);
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+ writel(0x0, DENALI_CTL_212 + ctl);
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+ writel(0x0, DENALI_CTL_214 + ctl);
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+ writel(0x0, DENALI_CTL_216 + ctl);
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+ setbits_le32(DENALI_CTL_224 + ctl,
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+ 0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
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+ writel(0xFFFFFFFF, DENALI_CTL_225 + ctl);
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+ setbits_le32(DENALI_CTL_208 + ctl, 0x1 << AXI0_ADDRESS_RANGE_ENABLE);
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+ setbits_le32(DENALI_CTL_208 + ctl,
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+ 0x1 << PORT_ADDR_PROTECTION_EN_OFFSET);
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+}
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+
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+static void fu540_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl,
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+ u64 ddr_end)
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+{
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+ volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl;
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+
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+ setbits_le32(DENALI_CTL_0 + ctl, 0x1);
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+
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+ wait_for_bit_le32((void *)ctl + DENALI_CTL_132,
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+ BIT(MC_INIT_COMPLETE_OFFSET), false, 100, false);
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+
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+ /* Disable the BusBlocker in front of the controller AXI slave ports */
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+ filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2);
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+}
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+
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+static void fu540_ddr_check_errata(u32 regbase, u32 updownreg)
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+{
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+ u64 fails = 0;
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+ u32 dq = 0;
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+ u32 down, up;
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+ u8 failc0, failc1;
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+ u32 phy_rx_cal_dqn_0_offset;
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+
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+ for (u32 bit = 0; bit < 2; bit++) {
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+ if (bit == 0) {
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+ phy_rx_cal_dqn_0_offset =
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+ PHY_RX_CAL_DQ0_0_OFFSET;
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+ } else {
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+ phy_rx_cal_dqn_0_offset =
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+ PHY_RX_CAL_DQ1_0_OFFSET;
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+ }
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+
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+ down = (updownreg >>
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+ phy_rx_cal_dqn_0_offset) & 0x3F;
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+ up = (updownreg >>
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+ (phy_rx_cal_dqn_0_offset + 6)) &
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+ 0x3F;
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+
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+ failc0 = ((down == 0) && (up == 0x3F));
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+ failc1 = ((up == 0) && (down == 0x3F));
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+
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+ /* print error message on failure */
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+ if (failc0 || failc1) {
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+ if (fails == 0)
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+ printf("DDR error in fixing up\n");
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+
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+ fails |= (1 << dq);
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+
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+ char slicelsc = '0';
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+ char slicemsc = '0';
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+
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+ slicelsc += (dq % 10);
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+ slicemsc += (dq / 10);
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+ printf("S ");
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+ printf("%c", slicemsc);
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+ printf("%c", slicelsc);
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+
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+ if (failc0)
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+ printf("U");
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+ else
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+ printf("D");
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+
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+ printf("\n");
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+ }
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+ dq++;
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+ }
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+}
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+
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+static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg)
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+{
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+ u32 slicebase = 0;
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+
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+ /* check errata condition */
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+ for (u32 slice = 0; slice < 8; slice++) {
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+ u32 regbase = slicebase + 34;
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+
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+ for (u32 reg = 0; reg < 4; reg++) {
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+ u32 updownreg = readl(regbase + reg + ddrphyreg);
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+
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+ fu540_ddr_check_errata(regbase, updownreg);
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+ }
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+ slicebase += 128;
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+ }
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+
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+ return(0);
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+}
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+
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+static u32 fu540_ddr_get_dram_class(volatile u32 *ctl)
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+{
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+ u32 reg = readl(DENALI_CTL_0 + ctl);
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+
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+ return ((reg >> DRAM_CLASS_OFFSET) & 0xF);
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+}
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+
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+static int fu540_ddr_setup(struct udevice *dev)
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+{
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+ struct fu540_ddr_info *priv = dev_get_priv(dev);
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+ struct sifive_dmc_plat *plat = dev_get_platdata(dev);
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+ struct fu540_ddr_params *params = &plat->ddr_params;
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+ volatile u32 *denali_ctl = priv->ctl->denali_ctl;
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+ volatile u32 *denali_phy = priv->phy->denali_phy;
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+ const u64 ddr_size = DDR_MEM_SIZE;
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+ const u64 ddr_end = PAYLOAD_DEST + ddr_size;
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+ int ret, i;
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+ u32 physet;
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+
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+ ret = dev_read_u32_array(dev, "sifive,ddr-params",
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+ (u32 *)&plat->ddr_params,
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+ sizeof(plat->ddr_params) / sizeof(u32));
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+ if (ret) {
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+ printf("%s: Cannot read sifive,ddr-params %d\n",
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+ __func__, ret);
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+ return ret;
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+ }
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+
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+ sdram_copy_to_reg(priv->ctl->denali_ctl,
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+ params->pctl_regs.denali_ctl,
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+ sizeof(struct fu540_ddrctl));
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+
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+ /* phy reset */
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+ for (i = DENALI_PHY_1152; i <= DENALI_PHY_1214; i++) {
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+ physet = params->phy_regs.denali_phy[i];
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+ priv->phy->denali_phy[i] = physet;
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+ }
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+
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+ for (i = 0; i < DENALI_PHY_1152; i++) {
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+ physet = params->phy_regs.denali_phy[i];
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+ priv->phy->denali_phy[i] = physet;
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+ }
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+
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+ /* Disable read interleave DENALI_CTL_120 */
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+ setbits_le32(DENALI_CTL_120 + denali_ctl,
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+ 1 << DISABLE_RD_INTERLEAVE_OFFSET);
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+
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+ /* Disable optimal read/modify/write logic DENALI_CTL_21 */
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+ clrbits_le32(DENALI_CTL_21 + denali_ctl, 1 << OPTIMAL_RMODW_EN_OFFSET);
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+
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+ /* Enable write Leveling DENALI_CTL_170 */
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+ setbits_le32(DENALI_CTL_170 + denali_ctl, (1 << WRLVL_EN_OFFSET)
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+ | (1 << DFI_PHY_WRLELV_MODE_OFFSET));
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+
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+ /* Enable read leveling DENALI_CTL_181 and DENALI_CTL_260 */
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+ setbits_le32(DENALI_CTL_181 + denali_ctl,
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+ 1 << DFI_PHY_RDLVL_MODE_OFFSET);
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+ setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_EN_OFFSET);
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+
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+ /* Enable read leveling gate DENALI_CTL_260 and DENALI_CTL_182 */
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+ setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_GATE_EN_OFFSET);
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+ setbits_le32(DENALI_CTL_182 + denali_ctl,
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+ 1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET);
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+
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+ if (fu540_ddr_get_dram_class(denali_ctl) == DRAM_CLASS_DDR4) {
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+ /* Enable vref training DENALI_CTL_184 */
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+ setbits_le32(DENALI_CTL_184 + denali_ctl, 1 << VREF_EN_OFFSET);
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+ }
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+
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+ /* Mask off leveling completion interrupt DENALI_CTL_136 */
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+ setbits_le32(DENALI_CTL_136 + denali_ctl,
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+ 1 << LEVELING_OPERATION_COMPLETED_OFFSET);
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+
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+ /* Mask off MC init complete interrupt DENALI_CTL_136 */
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+ setbits_le32(DENALI_CTL_136 + denali_ctl, 1 << MC_INIT_COMPLETE_OFFSET);
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+
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+ /* Mask off out of range interrupts DENALI_CTL_136 */
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+ setbits_le32(DENALI_CTL_136 + denali_ctl, (1 << OUT_OF_RANGE_OFFSET)
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+ | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET));
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+
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+ /* set up range protection */
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+ fu540_ddr_setup_range_protection(denali_ctl, DDR_MEM_SIZE);
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+
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+ /* Mask off port command error interrupt DENALI_CTL_136 */
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+ setbits_le32(DENALI_CTL_136 + denali_ctl,
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+ 1 << PORT_COMMAND_CHANNEL_ERROR_OFFSET);
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+
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+ fu540_ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end);
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+
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+ fu540_ddr_phy_fixup(denali_phy);
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+
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+ /* check size */
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+ priv->info.size = get_ram_size((long *)priv->info.base,
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+ DDR_MEM_SIZE);
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+
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+ debug("%s : %lx\n", __func__, priv->info.size);
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+
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+ /* check memory access for all memory */
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+ if (priv->info.size != DDR_MEM_SIZE) {
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+ printf("DDR invalid size : 0x%lx, expected 0x%lx\n",
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+ priv->info.size, DDR_MEM_SIZE);
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+#endif
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+
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+static int fu540_ddr_probe(struct udevice *dev)
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+{
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+ struct fu540_ddr_info *priv = dev_get_priv(dev);
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+
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+#if defined(CONFIG_SPL_BUILD)
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+ struct regmap *map;
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+ int ret;
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+ u32 clock = 0;
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+
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+ debug("FU540 DDR probe\n");
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+ priv->dev = dev;
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+
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+ ret = regmap_init_mem(dev_ofnode(dev), &map);
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+ if (ret)
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+ return ret;
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+
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+ ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
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+ if (ret) {
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+ debug("clk get failed %d\n", ret);
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+ return ret;
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+ }
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+
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+ ret = dev_read_u32(dev, "clock-frequency", &clock);
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+ if (ret) {
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+ debug("clock-frequency not found in dt %d\n", ret);
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+ return ret;
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+ } else {
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+ ret = clk_set_rate(&priv->ddr_clk, clock);
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+ if (ret < 0) {
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+ debug("Could not set DDR clock\n");
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+ return ret;
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+ }
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+ }
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+
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+ ret = clk_enable(&priv->ddr_clk);
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+ priv->ctl = regmap_get_range(map, 0);
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+ priv->phy = regmap_get_range(map, 1);
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+ priv->physical_filter_ctrl = regmap_get_range(map, 2);
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+
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+ priv->info.base = CONFIG_SYS_SDRAM_BASE;
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+
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+ priv->info.size = 0;
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+ return fu540_ddr_setup(dev);
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+#else
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+ priv->info.base = CONFIG_SYS_SDRAM_BASE;
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+ priv->info.size = DDR_MEM_SIZE;
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+#endif
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+ return 0;
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+}
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+
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+static int fu540_ddr_get_info(struct udevice *dev, struct ram_info *info)
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+{
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+ struct fu540_ddr_info *priv = dev_get_priv(dev);
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+
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+ *info = priv->info;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static struct ram_ops fu540_ddr_ops = {
|
|
|
+ .get_info = fu540_ddr_get_info,
|
|
|
+};
|
|
|
+
|
|
|
+static const struct udevice_id fu540_ddr_ids[] = {
|
|
|
+ { .compatible = "sifive,fu540-c000-ddr" },
|
|
|
+ { }
|
|
|
+};
|
|
|
+
|
|
|
+U_BOOT_DRIVER(fu540_ddr) = {
|
|
|
+ .name = "fu540_ddr",
|
|
|
+ .id = UCLASS_RAM,
|
|
|
+ .of_match = fu540_ddr_ids,
|
|
|
+ .ops = &fu540_ddr_ops,
|
|
|
+ .probe = fu540_ddr_probe,
|
|
|
+ .priv_auto_alloc_size = sizeof(struct fu540_ddr_info),
|
|
|
+#if defined(CONFIG_SPL_BUILD)
|
|
|
+ .platdata_auto_alloc_size = sizeof(struct sifive_dmc_plat),
|
|
|
+#endif
|
|
|
+};
|