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@@ -42,7 +42,9 @@
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* |-->| TUNNEL PLL |
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* | --------------
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* | |
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- * | |-->|CGU_TUN_IDIV|----------->
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+ * | |-->|CGU_TUN_IDIV_TUN|----------->
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+ * | |-->|CGU_TUN_IDIV_ROM|----------->
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+ * | |-->|CGU_TUN_IDIV_PWM|----------->
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* |
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* | ------------
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* |-->| HDMI PLL |
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@@ -60,7 +62,9 @@
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DECLARE_GLOBAL_DATA_PTR;
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#define CGU_ARC_IDIV 0x080
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-#define CGU_TUN_IDIV 0x380
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+#define CGU_TUN_IDIV_TUN 0x380
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+#define CGU_TUN_IDIV_ROM 0x390
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+#define CGU_TUN_IDIV_PWM 0x3A0
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#define CGU_HDMI_IDIV_APB 0x480
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#define CGU_SYS_IDIV_APB 0x180
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#define CGU_SYS_IDIV_AXI 0x190
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@@ -114,8 +118,68 @@ DECLARE_GLOBAL_DATA_PTR;
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#define CREG_CORE_IF_CLK_DIV_1 0x0
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#define CREG_CORE_IF_CLK_DIV_2 0x1
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+#define MIN_PLL_RATE 100000000 /* 100 MHz */
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#define PARENT_RATE 33333333 /* fixed clock - xtal */
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-#define CGU_MAX_CLOCKS 24
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+#define CGU_MAX_CLOCKS 26
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+
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+#define CGU_SYS_CLOCKS 16
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+#define MAX_AXI_CLOCKS 4
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+
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+#define CGU_TUN_CLOCKS 3
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+#define MAX_TUN_CLOCKS 6
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+
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+struct hsdk_tun_idiv_cfg {
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+ u32 oft;
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+ u8 val[MAX_TUN_CLOCKS];
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+};
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+
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+struct hsdk_tun_clk_cfg {
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+ const u32 clk_rate[MAX_TUN_CLOCKS];
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+ const u32 pll_rate[MAX_TUN_CLOCKS];
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+ const struct hsdk_tun_idiv_cfg idiv[CGU_TUN_CLOCKS];
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+};
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+
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+static const struct hsdk_tun_clk_cfg tun_clk_cfg = {
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+ { 25000000, 50000000, 75000000, 100000000, 125000000, 150000000 },
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+ { 600000000, 600000000, 600000000, 600000000, 700000000, 600000000 }, {
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+ { CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
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+ { CGU_TUN_IDIV_ROM, { 4, 4, 4, 4, 5, 4 } },
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+ { CGU_TUN_IDIV_PWM, { 8, 8, 8, 8, 10, 8 } }
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+ }
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+};
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+
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+struct hsdk_sys_idiv_cfg {
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+ u32 oft;
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+ u8 val[MAX_AXI_CLOCKS];
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+};
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+
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+struct hsdk_axi_clk_cfg {
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+ const u32 clk_rate[MAX_AXI_CLOCKS];
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+ const u32 pll_rate[MAX_AXI_CLOCKS];
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+ const struct hsdk_sys_idiv_cfg idiv[CGU_SYS_CLOCKS];
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+};
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+
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+static const struct hsdk_axi_clk_cfg axi_clk_cfg = {
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+ { 200000000, 400000000, 600000000, 800000000 },
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+ { 800000000, 800000000, 600000000, 800000000 }, {
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+ { CGU_SYS_IDIV_APB, { 4, 4, 3, 4 } }, /* APB */
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+ { CGU_SYS_IDIV_AXI, { 4, 2, 1, 1 } }, /* AXI */
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+ { CGU_SYS_IDIV_ETH, { 2, 2, 2, 2 } }, /* ETH */
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+ { CGU_SYS_IDIV_USB, { 2, 2, 2, 2 } }, /* USB */
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+ { CGU_SYS_IDIV_SDIO, { 2, 2, 2, 2 } }, /* SDIO */
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+ { CGU_SYS_IDIV_HDMI, { 2, 2, 2, 2 } }, /* HDMI */
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+ { CGU_SYS_IDIV_GFX_CORE, { 1, 1, 1, 1 } }, /* GPU-CORE */
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+ { CGU_SYS_IDIV_GFX_DMA, { 2, 2, 2, 2 } }, /* GPU-DMA */
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+ { CGU_SYS_IDIV_GFX_CFG, { 4, 4, 3, 4 } }, /* GPU-CFG */
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+ { CGU_SYS_IDIV_DMAC_CORE,{ 2, 2, 2, 2 } }, /* DMAC-CORE */
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+ { CGU_SYS_IDIV_DMAC_CFG, { 4, 4, 3, 4 } }, /* DMAC-CFG */
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+ { CGU_SYS_IDIV_SDIO_REF, { 8, 8, 6, 8 } }, /* SDIO-REF */
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+ { CGU_SYS_IDIV_SPI_REF, { 24, 24, 18, 24 } }, /* SPI-REF */
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+ { CGU_SYS_IDIV_I2C_REF, { 4, 4, 3, 4 } }, /* I2C-REF */
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+ { CGU_SYS_IDIV_UART_REF, { 24, 24, 18, 24 } }, /* UART-REF */
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+ { CGU_SYS_IDIV_EBI_REF, { 16, 16, 12, 16 } } /* EBI-REF */
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+ }
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+};
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struct hsdk_pll_cfg {
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u32 rate;
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@@ -201,6 +265,9 @@ static const struct hsdk_pll_devdata hdmi_pll_dat = {
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};
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static ulong idiv_set(struct clk *, ulong);
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+static ulong cpu_clk_set(struct clk *, ulong);
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+static ulong axi_clk_set(struct clk *, ulong);
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+static ulong tun_clk_set(struct clk *, ulong);
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static ulong idiv_get(struct clk *);
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static int idiv_off(struct clk *);
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static ulong pll_set(struct clk *, ulong);
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@@ -218,11 +285,11 @@ struct hsdk_cgu_clock_map {
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static const struct hsdk_cgu_clock_map clock_map[] = {
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{ CGU_ARC_PLL, 0, 0, &core_pll_dat, pll_get, pll_set, NULL },
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- { CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, idiv_set, idiv_off },
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+ { CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off },
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{ CGU_DDR_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
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{ CGU_SYS_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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+ { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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@@ -238,7 +305,9 @@ static const struct hsdk_cgu_clock_map clock_map[] = {
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_TUN_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
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- { CGU_TUN_PLL, 0, CGU_TUN_IDIV, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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+ { CGU_TUN_PLL, 0, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_clk_set, idiv_off },
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+ { CGU_TUN_PLL, 0, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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+ { CGU_TUN_PLL, 0, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
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{ CGU_HDMI_PLL, 0, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
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};
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@@ -423,7 +492,7 @@ static ulong pll_set(struct clk *sclk, ulong rate)
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}
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}
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- pr_err("invalid rate=%ld, parent_rate=%d\n", best_rate, PARENT_RATE);
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+ pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate, PARENT_RATE);
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return -EINVAL;
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}
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@@ -453,6 +522,94 @@ static ulong idiv_get(struct clk *sclk)
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return parent_rate / div_factor;
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}
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+/* Special behavior: wen we set this clock we set both idiv and pll */
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+static ulong cpu_clk_set(struct clk *sclk, ulong rate)
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+{
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+ ulong ret;
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+
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+ ret = pll_set(sclk, rate);
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+ idiv_set(sclk, rate);
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+
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+ return ret;
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+}
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+
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+/* Special behavior: wen we set this clock we set both idiv and pll and all pll dividers */
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+static ulong axi_clk_set(struct clk *sclk, ulong rate)
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+{
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+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
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+ ulong pll_rate;
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+ int i, freq_idx = -1;
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+ ulong ret = 0;
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+
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+ pll_rate = pll_get(sclk);
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+
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+ for (i = 0; i < MAX_AXI_CLOCKS; i++) {
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+ if (axi_clk_cfg.clk_rate[i] == rate) {
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+ freq_idx = i;
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+ break;
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+ }
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+ }
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+
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+ if (freq_idx < 0) {
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+ pr_err("axi clk: invalid rate=%ld Hz\n", rate);
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+ return -EINVAL;
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+ }
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+
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+ /* configure PLL before dividers */
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+ if (axi_clk_cfg.pll_rate[freq_idx] < pll_rate)
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+ ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
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+
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+ /* configure SYS dividers */
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+ for (i = 0; i < CGU_SYS_CLOCKS; i++) {
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+ clk->idiv_regs = clk->cgu_regs + axi_clk_cfg.idiv[i].oft;
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+ hsdk_idiv_write(clk, axi_clk_cfg.idiv[i].val[freq_idx]);
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+ }
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+
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+ /* configure PLL after dividers */
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+ if (axi_clk_cfg.pll_rate[freq_idx] >= pll_rate)
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+ ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
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+
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+ return ret;
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+}
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+
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+static ulong tun_clk_set(struct clk *sclk, ulong rate)
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+{
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+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
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+ ulong pll_rate;
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+ int i, freq_idx = -1;
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+ ulong ret = 0;
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+
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+ pll_rate = pll_get(sclk);
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+
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+ for (i = 0; i < MAX_TUN_CLOCKS; i++) {
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+ if (tun_clk_cfg.clk_rate[i] == rate) {
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+ freq_idx = i;
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+ break;
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+ }
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+ }
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+
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+ if (freq_idx < 0) {
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+ pr_err("tun clk: invalid rate=%ld Hz\n", rate);
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+ return -EINVAL;
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+ }
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+
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+ /* configure PLL before dividers */
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+ if (tun_clk_cfg.pll_rate[freq_idx] < pll_rate)
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+ ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
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+
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+ /* configure SYS dividers */
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+ for (i = 0; i < CGU_TUN_CLOCKS; i++) {
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+ clk->idiv_regs = clk->cgu_regs + tun_clk_cfg.idiv[i].oft;
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+ hsdk_idiv_write(clk, tun_clk_cfg.idiv[i].val[freq_idx]);
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+ }
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+
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+ /* configure PLL after dividers */
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+ if (tun_clk_cfg.pll_rate[freq_idx] >= pll_rate)
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+ ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
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+
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+ return ret;
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+}
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+
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static ulong idiv_set(struct clk *sclk, ulong rate)
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{
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struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
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@@ -466,14 +623,14 @@ static ulong idiv_set(struct clk *sclk, ulong rate)
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}
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if (div_factor & ~CGU_IDIV_MASK) {
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- pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: max divider valie is%d\n",
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+ pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
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rate, parent_rate, div_factor, CGU_IDIV_MASK);
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div_factor = CGU_IDIV_MASK;
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}
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if (div_factor == 0) {
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- pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: min divider valie is 1\n",
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+ pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
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rate, parent_rate, div_factor);
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div_factor = 1;
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@@ -559,6 +716,6 @@ U_BOOT_DRIVER(hsdk_cgu_clk) = {
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.id = UCLASS_CLK,
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.of_match = hsdk_cgu_clk_id,
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.probe = hsdk_cgu_clk_probe,
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- .platdata_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
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+ .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
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.ops = &hsdk_cgu_ops,
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};
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