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SPL:riscv:starfive-jh7110: Adjust CPU working frequency

Adjust CPU working frequency from 1G to 1.25G for starfive EVB board.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
yanhong.wang 2 years ago
parent
commit
c43d281323

+ 1 - 1
arch/riscv/dts/jh7110_clk.dtsi

@@ -117,7 +117,7 @@
 	pll0_out: pll0_out {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-		clock-frequency = <1000000000>;
+		clock-frequency = <1250000000>;
 	};
 
 	pll1_out: pll1_out {

+ 17 - 0
arch/riscv/include/asm/arch-jh7110/jh7110-regs.h

@@ -31,6 +31,9 @@
 /*usb cfg*/
 #define STG_SYSCON_4			0x4U
 #define SYS_SYSCON_24			0x18U
+#define SYS_SYSCON_28			0x1CU
+#define SYS_SYSCON_32			0x20U
+#define SYS_SYSCON_36			0x24U
 #define SYS_IOMUX_32			0x80U
 #define USB_MODE_STRAP_SHIFT		0x10U
 #define USB_MODE_STRAP_MASK		0x70000U
@@ -79,5 +82,19 @@
 #define CLK_QSPI_REF_SW_SHIFT	24
 #define CLK_QSPI_REF_SW_MASK	0x1000000U
 
+#define PLL0_DACPD_SHIFT	0x18U
+#define PLL0_DACPD_MASK	0x1000000U
+#define PLL0_DSMPD_SHIFT	0x19U
+#define PLL0_DSMPD_MASK	0x2000000U
+
+#define PLL0_PREDIV_SHIFT	0x0U
+#define PLL0_PREDIV_MASK	0x3FU
+#define PLL0_FBDIV_SHIFT	0x0U
+#define PLL0_FBDIV_MASK	0xFFFU
+
+#define PLL0_POSTDIV1_SHIFT	0x1CU
+#define PLL0_POSTDIV1_MASK	0x30000000U
+
+
 #endif /* __STARFIVE_JH7110_REGS_H */
 

+ 34 - 1
board/starfive/evb/spl.c

@@ -58,10 +58,43 @@ struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
 	return (struct image_header *)(STARFIVE_SPL_BOOT_LOAD_ADDR);
 }
 
+/* set PLL0 output to 1.5GHz*/
+__maybe_unused static void spl_cpu_fre_150(void)
+{
+	clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DACPD_MASK,
+		BIT(PLL0_DACPD_SHIFT) & PLL0_DACPD_MASK);
+	clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DSMPD_MASK,
+		BIT(PLL0_DSMPD_SHIFT) & PLL0_DSMPD_MASK);
+	clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_36, PLL0_PREDIV_MASK,
+		BIT(PLL0_PREDIV_SHIFT) & PLL0_PREDIV_MASK);
+	clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_28, PLL0_FBDIV_MASK,
+		(125 << PLL0_FBDIV_SHIFT) & PLL0_FBDIV_MASK);
+	clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_32, PLL0_POSTDIV1_MASK,
+		BIT(PLL0_POSTDIV1_SHIFT) & PLL0_POSTDIV1_MASK);
+}
+
+/* set PLL0 output to 1.25GHz*/
+static void spl_cpu_fre_125(void)
+{
+	clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DACPD_MASK,
+		BIT(PLL0_DACPD_SHIFT) & PLL0_DACPD_MASK);
+	clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DSMPD_MASK,
+		BIT(PLL0_DSMPD_SHIFT) & PLL0_DSMPD_MASK);
+	clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_36, PLL0_PREDIV_MASK,
+		BIT(PLL0_PREDIV_SHIFT) & PLL0_PREDIV_MASK);
+	clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_28, PLL0_FBDIV_MASK,
+		(52 << PLL0_FBDIV_SHIFT) & PLL0_FBDIV_MASK);
+	clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_32, PLL0_POSTDIV1_MASK,
+		(0 << PLL0_POSTDIV1_SHIFT) & PLL0_POSTDIV1_MASK);
+}
+
+
 void board_init_f(ulong dummy)
 {
 	int ret;
 
+	spl_cpu_fre_125();
+
 	/*DDR control depend clk init*/
 	clrsetbits_le32(SYS_CRG_BASE, CLK_CPU_ROOT_SW_MASK,
 		BIT(CLK_CPU_ROOT_SW_SHIFT) & CLK_CPU_ROOT_SW_MASK);
@@ -81,7 +114,7 @@ void board_init_f(ulong dummy)
 
 	clrsetbits_le32(SYS_CRG_BASE + CLK_QSPI_REF_OFFSET,
 		CLK_QSPI_REF_SW_MASK,
-		BIT(CLK_QSPI_REF_SW_SHIFT) & CLK_QSPI_REF_SW_MASK);
+		(0 << CLK_QSPI_REF_SW_SHIFT) & CLK_QSPI_REF_SW_MASK);
 
 	/*set GPIO to 1.8v*/
 	setbits_be32(SYS_SYSCON_BASE + 0xC, 0xf);