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@@ -58,10 +58,43 @@ struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
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return (struct image_header *)(STARFIVE_SPL_BOOT_LOAD_ADDR);
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}
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+/* set PLL0 output to 1.5GHz*/
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+__maybe_unused static void spl_cpu_fre_150(void)
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+{
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+ clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DACPD_MASK,
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+ BIT(PLL0_DACPD_SHIFT) & PLL0_DACPD_MASK);
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+ clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DSMPD_MASK,
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+ BIT(PLL0_DSMPD_SHIFT) & PLL0_DSMPD_MASK);
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+ clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_36, PLL0_PREDIV_MASK,
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+ BIT(PLL0_PREDIV_SHIFT) & PLL0_PREDIV_MASK);
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+ clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_28, PLL0_FBDIV_MASK,
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+ (125 << PLL0_FBDIV_SHIFT) & PLL0_FBDIV_MASK);
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+ clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_32, PLL0_POSTDIV1_MASK,
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+ BIT(PLL0_POSTDIV1_SHIFT) & PLL0_POSTDIV1_MASK);
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+}
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+
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+/* set PLL0 output to 1.25GHz*/
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+static void spl_cpu_fre_125(void)
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+{
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+ clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DACPD_MASK,
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+ BIT(PLL0_DACPD_SHIFT) & PLL0_DACPD_MASK);
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+ clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DSMPD_MASK,
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+ BIT(PLL0_DSMPD_SHIFT) & PLL0_DSMPD_MASK);
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+ clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_36, PLL0_PREDIV_MASK,
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+ BIT(PLL0_PREDIV_SHIFT) & PLL0_PREDIV_MASK);
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+ clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_28, PLL0_FBDIV_MASK,
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+ (52 << PLL0_FBDIV_SHIFT) & PLL0_FBDIV_MASK);
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+ clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_32, PLL0_POSTDIV1_MASK,
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+ (0 << PLL0_POSTDIV1_SHIFT) & PLL0_POSTDIV1_MASK);
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+}
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+
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+
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void board_init_f(ulong dummy)
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{
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int ret;
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+ spl_cpu_fre_125();
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+
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/*DDR control depend clk init*/
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clrsetbits_le32(SYS_CRG_BASE, CLK_CPU_ROOT_SW_MASK,
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BIT(CLK_CPU_ROOT_SW_SHIFT) & CLK_CPU_ROOT_SW_MASK);
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@@ -81,7 +114,7 @@ void board_init_f(ulong dummy)
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clrsetbits_le32(SYS_CRG_BASE + CLK_QSPI_REF_OFFSET,
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CLK_QSPI_REF_SW_MASK,
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- BIT(CLK_QSPI_REF_SW_SHIFT) & CLK_QSPI_REF_SW_MASK);
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+ (0 << CLK_QSPI_REF_SW_SHIFT) & CLK_QSPI_REF_SW_MASK);
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/*set GPIO to 1.8v*/
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setbits_be32(SYS_SYSCON_BASE + 0xC, 0xf);
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