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@@ -47,7 +47,7 @@ static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
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PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
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};
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-int fracpll_configure(enum pll_clocks pll, u32 freq)
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+static int fracpll_configure(enum pll_clocks pll, u32 freq)
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{
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int i;
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u32 tmp, div_val;
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@@ -268,7 +268,7 @@ u32 imx_get_uartclk(void)
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return 24000000U;
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}
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-u32 decode_intpll(enum clk_root_src intpll)
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+static u32 decode_intpll(enum clk_root_src intpll)
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{
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u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
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u32 main_div, pre_div, post_div, div;
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@@ -415,7 +415,7 @@ u32 decode_intpll(enum clk_root_src intpll)
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return lldiv(freq, pre_div * (1 << post_div) * div);
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}
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-u32 decode_fracpll(enum clk_root_src frac_pll)
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+static u32 decode_fracpll(enum clk_root_src frac_pll)
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{
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u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
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u32 main_div, pre_div, post_div, k;
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@@ -480,7 +480,7 @@ u32 decode_fracpll(enum clk_root_src frac_pll)
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65536 * pre_div * (1 << post_div));
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}
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-u32 get_root_src_clk(enum clk_root_src root_src)
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+static u32 get_root_src_clk(enum clk_root_src root_src)
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{
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switch (root_src) {
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case OSC_24M_CLK:
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@@ -524,7 +524,7 @@ u32 get_root_src_clk(enum clk_root_src root_src)
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return 0;
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}
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-u32 get_root_clk(enum clk_root_index clock_id)
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+static u32 get_root_clk(enum clk_root_index clock_id)
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{
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enum clk_root_src root_src;
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u32 post_podf, pre_podf, root_src_clk;
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