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@@ -461,6 +461,11 @@ void reset_cmplx_set_enable(int cpu, int which, int reset)
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writel(mask, &clkrst->crc_cpu_cmplx_clr);
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}
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+unsigned int __weak clk_m_get_rate(unsigned int parent_rate)
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+{
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+ return parent_rate;
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+}
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+
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unsigned clock_get_rate(enum clock_id clkid)
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{
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struct clk_pll *pll;
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@@ -472,6 +477,9 @@ unsigned clock_get_rate(enum clock_id clkid)
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if (clkid == CLOCK_ID_OSC)
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return parent_rate;
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+ if (clkid == CLOCK_ID_CLK_M)
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+ return clk_m_get_rate(parent_rate);
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+
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pll = get_pll(clkid);
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if (!pll)
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return 0;
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@@ -622,8 +630,10 @@ void clock_init(void)
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pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
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pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
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pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
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+ pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M);
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debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
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+ debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]);
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debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
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debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
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debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
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