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board:starfive:evb: add jh7110_gmac_sel_tx_to_rgmii

JH7110B needs switch gmac0/1 tx to rgmii phy.

Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Samin Guo 1 year ago
parent
commit
bd7deb0588

+ 8 - 0
arch/riscv/include/asm/arch-jh7110/jh7110-regs.h

@@ -25,8 +25,16 @@
 #define SYS_SYSCON_144			0x90U
 #define GMAC5_0_SEL_I_SHIFT             0x12U
 #define GMAC5_0_SEL_I_MASK              0x1C0000U
+#define GMAC5_0_CLK_TX_SHIFT            0x14
+#define GMAC5_0_CLK_RX_SHIFT            0x1C
+#define GMAC5_0_CLK_TX_BIT              0x18
+#define GMAC5_0_CLK_TX_MASK             0x1000000U
 #define GMAC5_1_SEL_I_SHIFT             0x2U
 #define GMAC5_1_SEL_I_MASK              0x1CU
+#define GMAC5_1_CLK_TX_SHIFT            0x1A4
+#define GMAC5_1_CLK_RX_SHIFT            0x19C
+#define GMAC5_1_CLK_TX_BIT              0x18
+#define GMAC5_1_CLK_TX_MASK             0x1000000U
 
 /*usb cfg*/
 #define STG_SYSCON_4			0x4U

+ 18 - 0
board/starfive/evb/starfive_evb.c

@@ -50,6 +50,24 @@ static void jh7110_timer_init(void)
 			SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER3_SHIFT);
 }
 
+static void jh7110_gmac_sel_tx_to_rgmii(int id)
+{
+	switch (id) {
+	case 0:
+		clrsetbits_le32(AON_CRG_BASE + GMAC5_0_CLK_TX_SHIFT,
+		GMAC5_0_CLK_TX_MASK,
+		BIT(GMAC5_0_CLK_TX_BIT) & GMAC5_0_CLK_TX_MASK);
+		break;
+	case 1:
+		clrsetbits_le32(SYS_CRG_BASE + GMAC5_1_CLK_TX_SHIFT,
+		GMAC5_1_CLK_TX_MASK,
+		BIT(GMAC5_1_CLK_TX_BIT) & GMAC5_1_CLK_TX_MASK);
+		break;
+	default:
+		break;
+	}
+}
+
 static void jh7110_gmac_init(int id)
 {
 	switch (id) {