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@@ -33,14 +33,16 @@ void flush_cache(ulong start_addr, ulong size)
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start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
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end = start_addr + size - 1;
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- for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
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+ for (addr = start; (addr <= end) && (addr >= start);
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+ addr += CONFIG_SYS_CACHELINE_SIZE) {
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asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
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WATCHDOG_RESET();
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}
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/* wait for all dcbst to complete on bus */
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asm volatile("sync" : : : "memory");
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- for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
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+ for (addr = start; (addr <= end) && (addr >= start);
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+ addr += CONFIG_SYS_CACHELINE_SIZE) {
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asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
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WATCHDOG_RESET();
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}
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