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@@ -77,8 +77,10 @@ void get_sys_info(struct sys_info *sys_info)
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sys_info->freq_systembus = sysclk;
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#ifdef CONFIG_DDR_CLK_FREQ
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sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
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+ sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
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#else
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sys_info->freq_ddrbus = sysclk;
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+ sys_info->freq_ddrbus2 = sysclk;
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#endif
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sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
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@@ -87,6 +89,9 @@ void get_sys_info(struct sys_info *sys_info)
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sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
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FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
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FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
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+ sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >>
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+ FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
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+ FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
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for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
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/*
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@@ -129,7 +134,7 @@ int get_clocks(void)
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gd->cpu_clk = sys_info.freq_processor[0];
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gd->bus_clk = sys_info.freq_systembus;
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gd->mem_clk = sys_info.freq_ddrbus;
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-
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+ gd->arch.mem2_clk = sys_info.freq_ddrbus2;
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#if defined(CONFIG_FSL_ESDHC)
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gd->arch.sdhc_clk = gd->bus_clk / 2;
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#endif /* defined(CONFIG_FSL_ESDHC) */
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@@ -156,11 +161,18 @@ ulong get_bus_freq(ulong dummy)
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* get_ddr_freq
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* return ddr bus freq in Hz
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*********************************************/
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-ulong get_ddr_freq(ulong dummy)
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+ulong get_ddr_freq(ulong ctrl_num)
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{
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if (!gd->mem_clk)
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get_clocks();
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+ /*
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+ * DDR controller 0 & 1 are on memory complex 0
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+ * DDR controler 2 is on memory complext 1
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+ */
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+ if (ctrl_num >= 2)
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+ return gd->arch.mem2_clk;
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+
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return gd->mem_clk;
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}
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