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spl: enable uart1 for RT-thread using

Set clock and uart1 pin (pin 43 and pin 45) in spl
stage, used as RT-thread console.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Minda Chen 7 maanden geleden
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commit
b7cc16149a
2 gewijzigde bestanden met toevoegingen van 17 en 1 verwijderingen
  1. 4 1
      arch/riscv/include/asm/arch-jh7110/jh7110-regs.h
  2. 13 0
      board/starfive/visionfive2/spl.c

+ 4 - 1
arch/riscv/include/asm/arch-jh7110/jh7110-regs.h

@@ -114,5 +114,8 @@
 #define CLK_QSPI_REF_SW_SHIFT	24
 #define CLK_QSPI_REF_SW_MASK	0x1000000U
 
-#endif /* __STARFIVE_JH7110_REGS_H */
+#define CLK_UART1_APB_OFFSET	0x24c
+#define CLK_UART1_CORE_OFFSET	0x250
+#define CLK_RSTN_3_OFFSET	0x300
 
+#endif /* __STARFIVE_JH7110_REGS_H */

+ 13 - 0
board/starfive/visionfive2/spl.c

@@ -117,6 +117,19 @@ void board_init_f(ulong dummy)
 	SYS_IOMUX_DOEN(6, HIGH);
 	SYS_IOMUX_DIN(6, 14);
 
+	/* uart1 clock */
+	setbits_le32(SYS_CRG_BASE + CLK_UART1_APB_OFFSET, BIT(31));
+	setbits_le32(SYS_CRG_BASE + CLK_UART1_CORE_OFFSET, BIT(31));
+	clrsetbits_le32(SYS_CRG_BASE + CLK_RSTN_3_OFFSET, BIT(21) | BIT(22), 0);
+
+	/*uart1 tx*/
+	SYS_IOMUX_DOEN(43, LOW);
+	SYS_IOMUX_DOUT(43, 0x44);
+	SYS_IOMUX_SET_DS(43, 3);
+	/*uart1 rx*/
+	SYS_IOMUX_DOEN(45, HIGH);
+	SYS_IOMUX_DIN(45, 55);
+
 	/*jtag*/
 	SYS_IOMUX_DOEN(36, HIGH);
 	SYS_IOMUX_DIN(36, 4);