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@@ -6,11 +6,7 @@
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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-#include <asm/arch/iomux.h>
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-#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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-#include <asm/gpio.h>
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-#include <asm/mach-imx/iomux-v3.h>
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#include <asm/io.h>
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#include <common.h>
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#include <env.h>
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@@ -20,43 +16,6 @@ DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_FEC_MXC
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#include <miiphy.h>
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-#define MDIO_PAD_CTRL ( \
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- PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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- PAD_CTL_DSE_40ohm \
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-)
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-
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-#define ENET_PAD_CTRL_PU ( \
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- PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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- PAD_CTL_DSE_40ohm \
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-)
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-
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-#define ENET_PAD_CTRL_PD ( \
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- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
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- PAD_CTL_DSE_40ohm \
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-)
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-
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-#define ENET_CLK_PAD_CTRL ( \
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- PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
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- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \
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-)
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-
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-static iomux_v3_cfg_t const fec1_pads[] = {
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- MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
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- MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
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- MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
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- MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
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- MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
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- MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
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- MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
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- MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
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- MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
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- /* PHY Int */
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- MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
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- /* PHY Reset */
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- MX6_PAD_NAND_DATA00__GPIO4_IO02 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
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- MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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-};
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-
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int board_phy_config(struct phy_device *phydev)
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{
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
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@@ -67,43 +26,16 @@ int board_phy_config(struct phy_device *phydev)
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return 0;
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}
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-int board_eth_init(bd_t *bis)
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+static int setup_fec(void)
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{
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struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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- struct gpio_desc rst;
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- int ret;
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/* Use 50M anatop loopback REF_CLK1 for ENET1,
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* clear gpr1[13], set gpr1[17] */
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
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IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
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- ret = enable_fec_anatop_clock(0, ENET_50MHZ);
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- if (ret)
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- return ret;
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-
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- enable_enet_clk(1);
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-
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- imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
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-
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- ret = dm_gpio_lookup_name("GPIO4_2", &rst);
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- if (ret) {
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- printf("Cannot get GPIO4_2\n");
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- return ret;
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- }
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-
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- ret = dm_gpio_request(&rst, "phy-rst");
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- if (ret) {
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- printf("Cannot request GPIO4_2\n");
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- return ret;
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- }
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-
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- dm_gpio_set_dir_flags(&rst, GPIOD_IS_OUT);
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- dm_gpio_set_value(&rst, 0);
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- udelay(1000);
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- dm_gpio_set_value(&rst, 1);
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-
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- return fecmxc_initialize(bis);
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+ return enable_fec_anatop_clock(0, ENET_50MHZ);
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}
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#endif /* CONFIG_FEC_MXC */
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@@ -112,6 +44,10 @@ int board_init(void)
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/* Address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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+#ifdef CONFIG_FEC_MXC
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+ setup_fec();
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+#endif
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+
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return 0;
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}
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