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armv8: cache_v8: fix mmu_set_region_dcache_behaviour

The enum dcache_optoion contains a shift left 2 bits in the armv8 case
already.  The PMD_ATTRINDX(option) macro will perform a left shift of 2
bits.  Perform a right shift so that in the end we get the correct
value.

[trini: Reword the commit message]
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan 4 年之前
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當前提交
b4b2619211
共有 1 個文件被更改,包括 1 次插入1 次删除
  1. 1 1
      arch/arm/cpu/armv8/cache_v8.c

+ 1 - 1
arch/arm/cpu/armv8/cache_v8.c

@@ -557,7 +557,7 @@ static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 				     enum dcache_option option)
 {
-	u64 attrs = PMD_ATTRINDX(option);
+	u64 attrs = PMD_ATTRINDX(option >> 2);
 	u64 real_start = start;
 	u64 real_size = size;