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@@ -0,0 +1,374 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Texas Instruments K3 clock driver
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+ *
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+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
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+ * Tero Kristo <t-kristo@ti.com>
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+ */
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+
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+#include <common.h>
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+#include <dm.h>
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+#include <errno.h>
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+#include <soc.h>
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+#include <clk-uclass.h>
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+#include "k3-clk.h"
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+
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+#define PLL_MIN_FREQ 800000000
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+#define PLL_MAX_FREQ 3200000000UL
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+#define PLL_MAX_DIV 127
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+
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+/**
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+ * struct clk_map - mapping from dev/clk id tuples towards physical clocks
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+ * @dev_id: device ID for the clock
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+ * @clk_id: clock ID for the clock
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+ * @clk: pointer to the registered clock entry for the mapping
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+ */
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+struct clk_map {
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+ u16 dev_id;
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+ u32 clk_id;
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+ struct clk *clk;
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+};
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+
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+/**
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+ * struct ti_clk_data - clock controller information structure
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+ * @map: mapping from dev/clk id tuples to physical clock entries
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+ * @size: number of entries in the map
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+ */
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+struct ti_clk_data {
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+ struct clk_map *map;
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+ int size;
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+};
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+
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+static ulong osc_freq;
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+
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+static void clk_add_map(struct ti_clk_data *data, struct clk *clk,
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+ u32 dev_id, u32 clk_id)
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+{
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+ struct clk_map *map;
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+
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+ debug("%s: added clk=%p, data=%p, dev=%d, clk=%d\n", __func__,
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+ clk, data, dev_id, clk_id);
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+ if (!clk)
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+ return;
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+
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+ map = data->map + data->size++;
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+
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+ map->dev_id = dev_id;
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+ map->clk_id = clk_id;
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+ map->clk = clk;
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+}
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+
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+static const struct soc_attr ti_k3_soc_clk_data[] = {
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+#if IS_ENABLED(CONFIG_SOC_K3_J721E)
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+ {
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+ .family = "J721E",
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+ .data = &j721e_clk_platdata,
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+ },
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+ {
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+ .family = "J7200",
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+ .data = &j7200_clk_platdata,
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+ },
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+#endif
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+ { /* sentinel */ }
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+};
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+
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+static int ti_clk_probe(struct udevice *dev)
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+{
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+ struct ti_clk_data *data = dev_get_priv(dev);
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+ struct clk *clk;
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+ const char *name;
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+ const struct clk_data *ti_clk_data;
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+ int i, j;
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+ const struct soc_attr *soc_match_data;
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+ const struct ti_k3_clk_platdata *pdata;
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+
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+ debug("%s(dev=%p)\n", __func__, dev);
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+
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+ soc_match_data = soc_device_match(ti_k3_soc_clk_data);
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+ if (!soc_match_data)
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+ return -ENODEV;
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+
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+ pdata = (const struct ti_k3_clk_platdata *)soc_match_data->data;
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+
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+ data->map = kcalloc(pdata->soc_dev_clk_data_cnt, sizeof(*data->map),
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+ GFP_KERNEL);
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+ data->size = 0;
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+
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+ for (i = 0; i < pdata->clk_list_cnt; i++) {
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+ ti_clk_data = &pdata->clk_list[i];
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+
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+ switch (ti_clk_data->type) {
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+ case CLK_TYPE_FIXED_RATE:
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+ name = ti_clk_data->clk.fixed_rate.name;
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+ clk = clk_register_fixed_rate(NULL,
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+ name,
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+ ti_clk_data->clk.fixed_rate.rate);
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+ break;
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+ case CLK_TYPE_DIV:
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+ name = ti_clk_data->clk.div.name;
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+ clk = clk_register_divider(NULL, name,
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+ ti_clk_data->clk.div.parent,
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+ ti_clk_data->clk.div.flags,
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+ map_physmem(ti_clk_data->clk.div.reg, 0, MAP_NOCACHE),
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+ ti_clk_data->clk.div.shift,
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+ ti_clk_data->clk.div.width,
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+ 0);
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+ break;
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+ case CLK_TYPE_MUX:
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+ name = ti_clk_data->clk.mux.name;
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+ clk = clk_register_mux(NULL, name,
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+ ti_clk_data->clk.mux.parents,
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+ ti_clk_data->clk.mux.num_parents,
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+ ti_clk_data->clk.mux.flags,
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+ map_physmem(ti_clk_data->clk.mux.reg, 0, MAP_NOCACHE),
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+ ti_clk_data->clk.mux.shift,
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+ ti_clk_data->clk.mux.width,
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+ 0);
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+ break;
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+ case CLK_TYPE_PLL:
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+ name = ti_clk_data->clk.pll.name;
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+ clk = clk_register_ti_pll(name,
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+ ti_clk_data->clk.pll.parent,
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+ map_physmem(ti_clk_data->clk.pll.reg, 0, MAP_NOCACHE));
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+
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+ if (!osc_freq)
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+ osc_freq = clk_get_rate(clk_get_parent(clk));
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+ break;
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+ default:
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+ name = NULL;
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+ clk = NULL;
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+ printf("WARNING: %s has encountered unknown clk type %d\n",
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+ __func__, ti_clk_data->type);
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+ }
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+
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+ if (clk && ti_clk_data->default_freq)
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+ clk_set_rate(clk, ti_clk_data->default_freq);
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+
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+ if (clk && name) {
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+ for (j = 0; j < pdata->soc_dev_clk_data_cnt; j++) {
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+ if (!strcmp(name, pdata->soc_dev_clk_data[j].clk_name)) {
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+ clk_add_map(data, clk, pdata->soc_dev_clk_data[j].dev_id,
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+ pdata->soc_dev_clk_data[j].clk_id);
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+ }
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+ }
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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+static int _clk_cmp(u32 dev_id, u32 clk_id, const struct clk_map *map)
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+{
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+ if (map->dev_id == dev_id && map->clk_id == clk_id)
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+ return 0;
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+ if (map->dev_id > dev_id ||
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+ (map->dev_id == dev_id && map->clk_id > clk_id))
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+ return -1;
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+ return 1;
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+}
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+
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+static int bsearch(u32 dev_id, u32 clk_id, struct clk_map *map, int num)
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+{
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+ int result;
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+ int idx;
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+
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+ for (idx = 0; idx < num; idx++) {
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+ result = _clk_cmp(dev_id, clk_id, &map[idx]);
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+
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+ if (result == 0)
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+ return idx;
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+ }
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+
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+ return -ENOENT;
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+}
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+
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+static int ti_clk_of_xlate(struct clk *clk,
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+ struct ofnode_phandle_args *args)
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+{
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+ struct ti_clk_data *data = dev_get_priv(clk->dev);
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+ int idx;
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+
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+ debug("%s(clk=%p, args_count=%d [0]=%d [1]=%d)\n", __func__, clk,
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+ args->args_count, args->args[0], args->args[1]);
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+
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+ if (args->args_count != 2) {
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+ debug("Invalid args_count: %d\n", args->args_count);
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+ return -EINVAL;
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+ }
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+
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+ if (!data->size)
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+ return -EPROBE_DEFER;
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+
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+ idx = bsearch(args->args[0], args->args[1], data->map, data->size);
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+ if (idx < 0)
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+ return idx;
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+
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+ clk->id = idx;
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+
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+ return 0;
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+}
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+
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+static ulong ti_clk_get_rate(struct clk *clk)
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+{
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+ struct ti_clk_data *data = dev_get_priv(clk->dev);
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+ struct clk *clkp = data->map[clk->id].clk;
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+
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+ return clk_get_rate(clkp);
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+}
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+
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+static ulong ti_clk_set_rate(struct clk *clk, ulong rate)
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+{
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+ struct ti_clk_data *data = dev_get_priv(clk->dev);
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+ struct clk *clkp = data->map[clk->id].clk;
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+ int div = 1;
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+ ulong child_rate;
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+ const struct clk_ops *ops;
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+ ulong new_rate, rem;
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+ ulong diff, new_diff;
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+
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+ /*
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+ * We must propagate rate change to parent if current clock type
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+ * does not allow setting it.
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+ */
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+ while (clkp) {
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+ ops = clkp->dev->driver->ops;
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+ if (ops->set_rate)
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+ break;
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+
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+ /*
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+ * Store child rate so we can calculate the clock rate
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+ * that must be passed to parent
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+ */
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+ child_rate = clk_get_rate(clkp);
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+ clkp = clk_get_parent(clkp);
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+ if (clkp) {
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+ debug("%s: propagating rate change to parent %s, rate=%u.\n",
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+ __func__, clkp->dev->name, (u32)rate / div);
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+ div *= clk_get_rate(clkp) / child_rate;
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+ }
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+ }
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+
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+ if (!clkp)
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+ return -ENOSYS;
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+
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+ child_rate = clk_get_rate(clkp);
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+
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+ new_rate = clk_set_rate(clkp, rate / div);
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+
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+ diff = abs(new_rate - rate / div);
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+
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+ debug("%s: clk=%s, div=%d, rate=%u, new_rate=%u, diff=%u\n", __func__,
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+ clkp->dev->name, div, (u32)rate, (u32)new_rate, (u32)diff);
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+
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+ /*
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+ * If the new rate differs by 50% of the target,
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+ * modify parent. This handles typical cases where we have a hsdiv
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+ * following directly a PLL
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+ */
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+
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+ if (diff > rate / div / 2) {
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+ ulong pll_tgt;
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+ int pll_div = 0;
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+
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+ clk = clkp;
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+
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+ debug("%s: propagating rate change to parent, rate=%u.\n",
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+ __func__, (u32)rate / div);
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+
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+ clkp = clk_get_parent(clkp);
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+
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+ if (rate > osc_freq) {
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+ if (rate > PLL_MAX_FREQ / 2 && rate < PLL_MAX_FREQ) {
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+ pll_tgt = rate;
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+ pll_div = 1;
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+ } else {
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+ for (pll_div = 2; pll_div < PLL_MAX_DIV; pll_div++) {
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+ pll_tgt = rate / div * pll_div;
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+ if (pll_tgt >= PLL_MIN_FREQ && pll_tgt <= PLL_MAX_FREQ)
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+ break;
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+ }
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+ }
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+ } else {
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+ pll_tgt = osc_freq;
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+ pll_div = rate / div / osc_freq;
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+ }
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+
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+ debug("%s: pll_tgt=%u, rate=%u, div=%u\n", __func__,
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+ (u32)pll_tgt, (u32)rate, pll_div);
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+
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+ clk_set_rate(clkp, pll_tgt);
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+
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+ return clk_set_rate(clk, rate / div) * div;
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+ }
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+
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+ /*
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+ * If the new rate differs by at least 5% of the target,
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+ * we must check for rounding error in a divider, so try
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+ * set rate with rate + (parent_freq % rate).
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+ */
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+
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+ if (diff > rate / div / 20) {
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+ u64 parent_freq = clk_get_parent_rate(clkp);
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+
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+ rem = parent_freq % rate;
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+ new_rate = clk_set_rate(clkp, (rate / div) + rem);
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+ new_diff = abs(new_rate - rate / div);
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+
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+ if (new_diff > diff) {
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+ new_rate = clk_set_rate(clkp, rate / div);
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+ } else {
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+ debug("%s: Using better rate %lu that gives diff %lu\n",
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+ __func__, new_rate, new_diff);
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+ }
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+ }
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+
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+ return new_rate;
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+}
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+
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+static int ti_clk_set_parent(struct clk *clk, struct clk *parent)
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+{
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+ struct ti_clk_data *data = dev_get_priv(clk->dev);
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+ struct clk *clkp = data->map[clk->id].clk;
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+ struct clk *parentp = data->map[parent->id].clk;
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+
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+ return clk_set_parent(clkp, parentp);
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+}
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+
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+static int ti_clk_enable(struct clk *clk)
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+{
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+ struct ti_clk_data *data = dev_get_priv(clk->dev);
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+ struct clk *clkp = data->map[clk->id].clk;
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+
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+ return clk_enable(clkp);
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+}
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+
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+static int ti_clk_disable(struct clk *clk)
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+{
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+ struct ti_clk_data *data = dev_get_priv(clk->dev);
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+ struct clk *clkp = data->map[clk->id].clk;
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+
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+ return clk_disable(clkp);
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+}
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+
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+static const struct udevice_id ti_clk_of_match[] = {
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+ { .compatible = "ti,k2g-sci-clk" },
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+ { /* sentinel */ },
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+};
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+
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+static const struct clk_ops ti_clk_ops = {
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+ .of_xlate = ti_clk_of_xlate,
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+ .set_rate = ti_clk_set_rate,
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+ .get_rate = ti_clk_get_rate,
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+ .enable = ti_clk_enable,
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+ .disable = ti_clk_disable,
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+ .set_parent = ti_clk_set_parent,
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+};
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+
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+U_BOOT_DRIVER(ti_clk) = {
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+ .name = "ti-clk",
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+ .id = UCLASS_CLK,
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+ .of_match = ti_clk_of_match,
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+ .probe = ti_clk_probe,
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+ .priv_auto = sizeof(struct ti_clk_data),
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+ .ops = &ti_clk_ops,
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+};
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