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@@ -34,6 +34,10 @@
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DECLARE_GLOBAL_DATA_PTR;
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+#define CPUID_FEATURE_PAE BIT(6)
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+#define CPUID_FEATURE_PSE36 BIT(17)
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+#define CPUID_FEAURE_HTT BIT(28)
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+
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/*
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* Constructor for a conventional segment GDT (or LDT) entry
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* This is a macro so it can be used in initialisers
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@@ -388,6 +392,25 @@ static void setup_identity(void)
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}
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}
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+static uint cpu_cpuid_extended_level(void)
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+{
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+ return cpuid_eax(0x80000000);
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+}
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+
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+int cpu_phys_address_size(void)
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+{
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+ if (!has_cpuid())
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+ return 32;
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+
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+ if (cpu_cpuid_extended_level() >= 0x80000008)
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+ return cpuid_eax(0x80000008) & 0xff;
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+
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+ if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
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+ return 36;
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+
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+ return 32;
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+}
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+
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/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
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static void setup_pci_ram_top(void)
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{
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