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@@ -12,6 +12,7 @@
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#include <env.h>
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#include <init.h>
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#include <log.h>
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+#include <lmb.h>
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#include <misc.h>
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#include <net.h>
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#include <asm/io.h>
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@@ -90,6 +91,8 @@
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*/
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u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
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+struct lmb lmb;
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+
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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#ifndef CONFIG_TFABOOT
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static void security_init(void)
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@@ -221,6 +224,8 @@ void dram_bank_mmu_setup(int bank)
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int i;
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phys_addr_t start;
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phys_size_t size;
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+ bool use_lmb = false;
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+ enum dcache_option option;
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if (IS_ENABLED(CONFIG_SPL_BUILD)) {
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start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
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@@ -229,6 +234,7 @@ void dram_bank_mmu_setup(int bank)
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/* bd->bi_dram is available only after relocation */
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start = bd->bi_dram[bank].start;
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size = bd->bi_dram[bank].size;
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+ use_lmb = true;
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} else {
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/* mark cacheable and executable the beggining of the DDR */
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start = STM32_DDR_BASE;
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@@ -237,8 +243,12 @@ void dram_bank_mmu_setup(int bank)
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for (i = start >> MMU_SECTION_SHIFT;
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i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
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- i++)
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- set_section_dcache(i, DCACHE_DEFAULT_OPTION);
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+ i++) {
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+ option = DCACHE_DEFAULT_OPTION;
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+ if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP))
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+ option = 0; /* INVALID ENTRY in TLB */
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+ set_section_dcache(i, option);
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+ }
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}
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/*
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* initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
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@@ -302,6 +312,9 @@ int arch_cpu_init(void)
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void enable_caches(void)
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{
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+ /* parse device tree when data cache is still activated */
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+ lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
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+
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/* I-cache is already enabled in start.S: icache_enable() not needed */
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/* deactivate the data cache, early enabled in arch_cpu_init() */
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