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@@ -1,5 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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+ * Copyright (C) 2021 Tony Dinh <mibodhi@gmail.com>
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* (C) Copyright 2011
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* Jason Cooper <u-boot@lakedaemon.net>
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*
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@@ -97,42 +98,75 @@ int board_init(void)
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return 0;
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}
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+static int fdt_get_phy_addr(const char *path)
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+{
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+ const void *fdt = gd->fdt_blob;
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+ const u32 *reg;
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+ const u32 *val;
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+ int node, phandle, addr;
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+
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+ /* Find the node by its full path */
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+ node = fdt_path_offset(fdt, path);
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+ if (node >= 0) {
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+ /* Look up phy-handle */
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+ val = fdt_getprop(fdt, node, "phy-handle", NULL);
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+ if (val) {
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+ phandle = fdt32_to_cpu(*val);
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+ if (!phandle)
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+ return -1;
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+ /* Follow it to its node */
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+ node = fdt_node_offset_by_phandle(fdt, phandle);
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+ if (node) {
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+ /* Look up reg */
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+ reg = fdt_getprop(fdt, node, "reg", NULL);
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+ if (reg) {
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+ addr = fdt32_to_cpu(*reg);
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+ return addr;
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+ }
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+ }
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+ }
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+ }
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+ return -1;
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+}
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+
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#ifdef CONFIG_RESET_PHY_R
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-void mv_phy_88e1116_init(char *name)
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+void mv_phy_88e1116_init(const char *name, const char *path)
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{
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u16 reg;
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- u16 devadr;
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+ int phyaddr;
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if (miiphy_set_current_dev(name))
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return;
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- /* command to read PHY dev address */
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- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
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- printf("Err..%s could not read PHY dev address\n",
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- __func__);
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+ phyaddr = fdt_get_phy_addr(path);
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+ if (phyaddr < 0)
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return;
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- }
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
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- miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
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+ miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
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+ miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL2_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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- miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
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- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
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+ miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL2_REG, reg);
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+ miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
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/* reset the phy */
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- miiphy_reset(name, devadr);
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+ miiphy_reset(name, phyaddr);
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printf("88E1116 Initialized on %s\n", name);
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}
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void reset_phy(void)
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{
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+ char *eth0_name = "ethernet-controller@72000";
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+ char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
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+ char *eth1_name = "ethernet-controller@76000";
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+ char *eth1_path = "/ocp@f1000000/ethernet-controller@72000/ethernet1-port@0";
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+
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/* configure and initialize both PHY's */
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- mv_phy_88e1116_init("egiga0");
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- mv_phy_88e1116_init("egiga1");
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+ mv_phy_88e1116_init(eth0_name, eth0_path);
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+ mv_phy_88e1116_init(eth1_name, eth1_path);
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}
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#endif /* CONFIG_RESET_PHY_R */
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