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@@ -0,0 +1,40 @@
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+/* SPDX-License-Identifier: GPL-2.0+ */
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+/*
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+ * Copyright 2018 NXP
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+ */
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+
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+#ifndef __ASM_ARCH_IMX8_IOMUX_H__
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+#define __ASM_ARCH_IMX8_IOMUX_H__
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+
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+/*
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+ * We use 64bits value for iomux settings.
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+ * High 32bits are used for padring register value,
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+ * low 16bits are used for pin index.
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+ */
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+typedef u64 iomux_cfg_t;
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+
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+#define PADRING_IFMUX_EN_SHIFT 31
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+#define PADRING_IFMUX_EN_MASK BIT(31)
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+#define PADRING_GP_EN_SHIFT 30
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+#define PADRING_GP_EN_MASK BIT(30)
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+#define PADRING_IFMUX_SHIFT 27
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+#define PADRING_IFMUX_MASK GENMASK(29, 27)
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+#define PADRING_CONFIG_SHIFT 25
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+#define PADRING_LPCONFIG_SHIFT 23
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+#define PADRING_PULL_SHIFT 5
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+#define PADRING_DSE_SHIFT 0
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+
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+#define MUX_PAD_CTRL_SHIFT 32
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+#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0xFFFFFFFF << MUX_PAD_CTRL_SHIFT)
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+#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
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+#define MUX_MODE_SHIFT (PADRING_IFMUX_SHIFT + MUX_PAD_CTRL_SHIFT)
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+#define MUX_MODE_MASK ((iomux_cfg_t)0x7 << MUX_MODE_SHIFT)
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+#define PIN_ID_MASK ((iomux_cfg_t)0xFFFF)
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+
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+/* Valid mux alt0 to alt7 */
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+#define MUX_MODE_ALT(x) (((iomux_cfg_t)(x) << MUX_MODE_SHIFT) & \
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+ MUX_MODE_MASK)
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+
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+void imx8_iomux_setup_pad(iomux_cfg_t pad);
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+void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count);
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+#endif /* __ASM_ARCH_IMX8_IOMUX_H__ */
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