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@@ -143,17 +143,6 @@
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
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-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
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- | BR_PS_16 /* 16 bit port */ \
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- | BR_MS_GPCM /* MSEL = GPCM */ \
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- | BR_V) /* valid */
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-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
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- | OR_GPCM_XACS \
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- | OR_GPCM_SCY_9 \
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- | OR_GPCM_EHTR \
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- | OR_GPCM_EAD)
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- /* 0xFF006FF7 TODO SLOW 16 MB flash size */
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-
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
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@@ -199,20 +188,13 @@
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#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
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#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
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-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
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- | BR_DECC_CHK_GEN /* Use HW ECC */ \
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- | BR_PS_8 /* 8 bit port */ \
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- | BR_MS_FCM /* MSEL = FCM */ \
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- | BR_V) /* valid */
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-#define CONFIG_SYS_OR1_PRELIM \
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- (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
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- | OR_FCM_CSCT \
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- | OR_FCM_CST \
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- | OR_FCM_CHT \
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- | OR_FCM_SCY_1 \
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- | OR_FCM_TRLX \
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- | OR_FCM_EHTR)
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- /* 0xFFFF8396 */
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+/* FLASH*/
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+#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
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+#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
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+
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+/* NAND */
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+#define CONFIG_SYS_BR1_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V)
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+#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR)
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/* Still needed for spl_minimal.c */
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#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
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@@ -222,20 +204,9 @@
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#define CONFIG_SYS_BCSR_ADDR 0xFA000000
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#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
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/* map at 0xFA000000 on LCS3 */
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-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
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- | BR_PS_8 /* 8 bit port */ \
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- | BR_MS_GPCM /* MSEL = GPCM */ \
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- | BR_V) /* valid */
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- /* 0xFA000801 */
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-#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
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- | OR_GPCM_CSNT \
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- | OR_GPCM_ACS_DIV2 \
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- | OR_GPCM_XACS \
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- | OR_GPCM_SCY_15 \
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- | OR_GPCM_TRLX_SET \
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- | OR_GPCM_EHTR_SET \
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- | OR_GPCM_EAD)
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- /* 0xFFFF8FF7 */
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+/* BCSR */
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+#define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
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+#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
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/* Vitesse 7385 */
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#ifdef CONFIG_VSC7385_ENET
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@@ -244,19 +215,10 @@
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#define CONFIG_SYS_VSC7385_BASE 0xF0000000
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#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
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-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
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- | BR_PS_8 /* 8 bit port */ \
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- | BR_MS_GPCM /* MSEL = GPCM */ \
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- | BR_V) /* valid */
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-#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
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- | OR_GPCM_CSNT \
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- | OR_GPCM_XACS \
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- | OR_GPCM_SCY_15 \
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- | OR_GPCM_SETA \
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- | OR_GPCM_TRLX_SET \
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- | OR_GPCM_EHTR_SET \
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- | OR_GPCM_EAD)
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- /* 0xFFFE09FF */
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+/* VSC7385 */
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+#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
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+#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
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+
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#endif
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#define CONFIG_MPC83XX_GPIO 1
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