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@@ -0,0 +1,77 @@
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+/*
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+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#include <common.h>
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+#include <miiphy.h>
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+#include <asm/io.h>
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+#include <asm/arch/cpu.h>
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+#include <asm/arch/soc.h>
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+#include <linux/mbus.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+/* Base addresses for the external device chip selects */
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+#define DEV_CS0_BASE 0xe0000000
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+#define DEV_CS1_BASE 0xe1000000
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+#define DEV_CS2_BASE 0xe2000000
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+#define DEV_CS3_BASE 0xe3000000
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+
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+/* Needed for dynamic (board-specific) mbus configuration */
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+extern struct mvebu_mbus_state mbus_state;
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+
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+int board_early_init_f(void)
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+{
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+ /*
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+ * Don't configure MPP (pin multiplexing) and GPIO here,
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+ * its already done in bin_hdr
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+ */
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+
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+ /*
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+ * Setup some board specific mbus address windows
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+ */
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+ mbus_dt_setup_win(&mbus_state, DEV_CS0_BASE, 16 << 20,
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+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS0);
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+ mbus_dt_setup_win(&mbus_state, DEV_CS1_BASE, 16 << 20,
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+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
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+ mbus_dt_setup_win(&mbus_state, DEV_CS2_BASE, 16 << 20,
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+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS2);
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+ mbus_dt_setup_win(&mbus_state, DEV_CS3_BASE, 16 << 20,
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+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS3);
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+
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+ return 0;
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+}
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+
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+int board_init(void)
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+{
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+ /* adress of boot parameters */
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+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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+
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+ return 0;
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+}
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+
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+int checkboard(void)
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+{
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+ puts("Board: maxBCM\n");
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+
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+ return 0;
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+}
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+
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+#ifdef CONFIG_RESET_PHY_R
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+/* Configure and enable MV88E6185 switch */
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+void reset_phy(void)
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+{
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+ u16 devadr = CONFIG_PHY_BASE_ADDR;
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+ char *name = "neta0";
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+ u16 reg;
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+
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+ if (miiphy_set_current_dev(name))
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+ return;
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+
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+ /* todo: fill this with the real setup / config code */
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+
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+ printf("88E6185 Initialized on %s\n", name);
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+}
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+#endif /* CONFIG_RESET_PHY_R */
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