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@@ -26,6 +26,9 @@ DECLARE_GLOBAL_DATA_PTR;
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int riscv_get_time(u64 *time)
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{
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+ /* ensure timer register base has a sane value */
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+ riscv_init_ipi();
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+
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*time = readq((void __iomem *)MTIME_REG(gd->arch.clint));
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return 0;
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@@ -33,6 +36,9 @@ int riscv_get_time(u64 *time)
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int riscv_set_timecmp(int hart, u64 cmp)
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{
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+ /* ensure timer register base has a sane value */
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+ riscv_init_ipi();
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+
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writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart));
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return 0;
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@@ -40,11 +46,13 @@ int riscv_set_timecmp(int hart, u64 cmp)
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int riscv_init_ipi(void)
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{
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- long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT);
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+ if (!gd->arch.clint) {
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+ long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT);
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- if (IS_ERR(ret))
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- return PTR_ERR(ret);
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- gd->arch.clint = ret;
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+ if (IS_ERR(ret))
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+ return PTR_ERR(ret);
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+ gd->arch.clint = ret;
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+ }
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return 0;
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}
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