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@@ -44,8 +44,10 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun8i-de2.h>
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#include <dt-bindings/clock/sun8i-r40-ccu.h>
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+#include <dt-bindings/clock/sun8i-tcon-top.h>
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#include <dt-bindings/reset/sun8i-r40-ccu.h>
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#include <dt-bindings/reset/sun8i-de2.h>
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+#include <dt-bindings/thermal/thermal.h>
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/ {
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#address-cells = <1>;
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@@ -78,25 +80,25 @@
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#address-cells = <1>;
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#size-cells = <0>;
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- cpu@0 {
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+ cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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- cpu@1 {
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+ cpu1: cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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- cpu@2 {
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+ cpu2: cpu@2 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <2>;
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};
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- cpu@3 {
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+ cpu3: cpu@3 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <3>;
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@@ -109,6 +111,22 @@
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status = "disabled";
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};
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+ thermal-zones {
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+ cpu_thermal: cpu0-thermal {
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+ /* milliseconds */
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&ths 0>;
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+ };
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+
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+ gpu_thermal: gpu-thermal {
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+ /* milliseconds */
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+ polling-delay-passive = <0>;
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+ polling-delay = <0>;
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+ thermal-sensors = <&ths 1>;
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+ };
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+ };
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+
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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@@ -118,11 +136,11 @@
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display_clocks: clock@1000000 {
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compatible = "allwinner,sun8i-r40-de2-clk",
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"allwinner,sun8i-h3-de2-clk";
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- reg = <0x01000000 0x100000>;
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- clocks = <&ccu CLK_DE>,
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- <&ccu CLK_BUS_DE>;
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- clock-names = "mod",
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- "bus";
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+ reg = <0x01000000 0x10000>;
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+ clocks = <&ccu CLK_BUS_DE>,
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+ <&ccu CLK_DE>;
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+ clock-names = "bus",
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+ "mod";
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resets = <&ccu RST_BUS_DE>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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@@ -172,6 +190,48 @@
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};
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};
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+ deinterlace: deinterlace@1400000 {
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+ compatible = "allwinner,sun8i-r40-deinterlace",
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+ "allwinner,sun8i-h3-deinterlace";
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+ reg = <0x01400000 0x20000>;
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+ clocks = <&ccu CLK_BUS_DEINTERLACE>,
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+ <&ccu CLK_DEINTERLACE>,
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+ /*
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+ * NOTE: Contrary to what datasheet claims,
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+ * DRAM deinterlace gate doesn't exist and
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+ * it's shared with CSI1.
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+ */
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+ <&ccu CLK_DRAM_CSI1>;
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+ clock-names = "bus", "mod", "ram";
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+ resets = <&ccu RST_BUS_DEINTERLACE>;
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+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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+ interconnects = <&mbus 9>;
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+ interconnect-names = "dma-mem";
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+ };
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+
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+ syscon: system-control@1c00000 {
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+ compatible = "allwinner,sun8i-r40-system-control",
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+ "allwinner,sun4i-a10-system-control";
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+ reg = <0x01c00000 0x30>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+
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+ sram_c: sram@1d00000 {
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+ compatible = "mmio-sram";
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+ reg = <0x01d00000 0xd0000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0x01d00000 0xd0000>;
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+
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+ ve_sram: sram-section@0 {
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+ compatible = "allwinner,sun8i-r40-sram-c1",
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+ "allwinner,sun4i-a10-sram-c1";
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+ reg = <0x000000 0x80000>;
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+ };
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+ };
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+ };
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+
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nmi_intc: interrupt-controller@1c00030 {
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compatible = "allwinner,sun7i-a20-sc-nmi";
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interrupt-controller;
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@@ -180,6 +240,69 @@
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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+ dma: dma-controller@1c02000 {
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+ compatible = "allwinner,sun8i-r40-dma",
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+ "allwinner,sun50i-a64-dma";
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+ reg = <0x01c02000 0x1000>;
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+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_DMA>;
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+ dma-channels = <16>;
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+ dma-requests = <31>;
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+ resets = <&ccu RST_BUS_DMA>;
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+ #dma-cells = <1>;
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+ };
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+
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+ spi0: spi@1c05000 {
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+ compatible = "allwinner,sun8i-r40-spi",
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+ "allwinner,sun8i-h3-spi";
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+ reg = <0x01c05000 0x1000>;
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+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
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+ clock-names = "ahb", "mod";
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+ resets = <&ccu RST_BUS_SPI0>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ spi1: spi@1c06000 {
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+ compatible = "allwinner,sun8i-r40-spi",
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+ "allwinner,sun8i-h3-spi";
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+ reg = <0x01c06000 0x1000>;
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+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
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+ clock-names = "ahb", "mod";
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+ resets = <&ccu RST_BUS_SPI1>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ csi0: csi@1c09000 {
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+ compatible = "allwinner,sun8i-r40-csi0",
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+ "allwinner,sun7i-a20-csi0";
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+ reg = <0x01c09000 0x1000>;
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+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
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+ <&ccu CLK_DRAM_CSI0>;
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+ clock-names = "bus", "isp", "ram";
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+ resets = <&ccu RST_BUS_CSI0>;
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+ interconnects = <&mbus 5>;
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+ interconnect-names = "dma-mem";
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+ status = "disabled";
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+ };
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+
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+ video-codec@1c0e000 {
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+ compatible = "allwinner,sun8i-r40-video-engine";
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+ reg = <0x01c0e000 0x1000>;
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+ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
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+ <&ccu CLK_DRAM_VE>;
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+ clock-names = "ahb", "mod", "ram";
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+ resets = <&ccu RST_BUS_VE>;
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+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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+ allwinner,sram = <&ve_sram 1>;
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+ };
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+
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun8i-r40-mmc",
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"allwinner,sun50i-a64-mmc";
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@@ -266,6 +389,38 @@
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#phy-cells = <1>;
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};
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+ crypto: crypto@1c15000 {
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+ compatible = "allwinner,sun8i-r40-crypto";
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+ reg = <0x01c15000 0x1000>;
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+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
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+ clock-names = "bus", "mod";
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+ resets = <&ccu RST_BUS_CE>;
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+ };
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+
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+ spi2: spi@1c17000 {
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+ compatible = "allwinner,sun8i-r40-spi",
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+ "allwinner,sun8i-h3-spi";
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+ reg = <0x01c17000 0x1000>;
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+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
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+ clock-names = "ahb", "mod";
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+ resets = <&ccu RST_BUS_SPI2>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ ahci: sata@1c18000 {
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+ compatible = "allwinner,sun8i-r40-ahci";
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+ reg = <0x01c18000 0x1000>;
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+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
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+ resets = <&ccu RST_BUS_SATA>;
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+ reset-names = "ahci";
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+ status = "disabled";
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+ };
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+
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ehci1: usb@1c19000 {
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compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
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reg = <0x01c19000 0x100>;
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@@ -312,6 +467,19 @@
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status = "disabled";
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};
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+ spi3: spi@1c1f000 {
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+ compatible = "allwinner,sun8i-r40-spi",
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+ "allwinner,sun8i-h3-spi";
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+ reg = <0x01c1f000 0x1000>;
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+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
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+ clock-names = "ahb", "mod";
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+ resets = <&ccu RST_BUS_SPI3>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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ccu: clock@1c20000 {
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compatible = "allwinner,sun8i-r40-ccu";
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reg = <0x01c20000 0x400>;
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@@ -322,8 +490,7 @@
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};
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rtc: rtc@1c20400 {
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- compatible = "allwinner,sun8i-r40-rtc",
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- "allwinner,sun8i-h3-rtc";
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+ compatible = "allwinner,sun8i-r40-rtc";
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reg = <0x01c20400 0x400>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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clock-output-names = "osc32k", "osc32k-out";
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@@ -347,6 +514,20 @@
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function = "clk_out_a";
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};
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+ /omit-if-no-ref/
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+ csi0_8bits_pins: csi0-8bits-pins {
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+ pins = "PE0", "PE2", "PE3", "PE4", "PE5",
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+ "PE6", "PE7", "PE8", "PE9", "PE10",
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+ "PE11";
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+ function = "csi0";
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+ };
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+
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+ /omit-if-no-ref/
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+ csi0_mclk_pin: csi0-mclk-pin {
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+ pins = "PE1";
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+ function = "csi0";
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+ };
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+
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gmac_rgmii_pins: gmac-rgmii-pins {
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pins = "PA0", "PA1", "PA2", "PA3",
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"PA4", "PA5", "PA6", "PA7",
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@@ -365,6 +546,36 @@
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function = "i2c0";
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};
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+ i2c1_pins: i2c1-pins {
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+ pins = "PB18", "PB19";
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+ function = "i2c1";
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+ };
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+
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+ i2c2_pins: i2c2-pins {
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+ pins = "PB20", "PB21";
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+ function = "i2c2";
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+ };
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+
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+ i2c3_pins: i2c3-pins {
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+ pins = "PI0", "PI1";
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+ function = "i2c3";
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+ };
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+
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+ i2c4_pins: i2c4-pins {
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+ pins = "PI2", "PI3";
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+ function = "i2c4";
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+ };
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+
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+ ir0_pins: ir0-pins {
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+ pins = "PB4";
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+ function = "ir0";
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+ };
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+
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+ ir1_pins: ir1-pins {
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+ pins = "PB23";
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+ function = "ir1";
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+ };
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+
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2",
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"PF3", "PF4", "PF5";
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@@ -390,6 +601,36 @@
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bias-pull-up;
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};
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+ /omit-if-no-ref/
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+ spi0_pc_pins: spi0-pc-pins {
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+ pins = "PC0", "PC1", "PC2";
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+ function = "spi0";
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+ };
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+
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+ /omit-if-no-ref/
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+ spi0_cs0_pc_pin: spi0-cs0-pc-pin {
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+ pins = "PC23";
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+ function = "spi0";
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+ };
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+
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+ /omit-if-no-ref/
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+ spi1_pi_pins: spi1-pi-pins {
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+ pins = "PI17", "PI18", "PI19";
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+ function = "spi1";
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+ };
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+
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+ /omit-if-no-ref/
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+ spi1_cs0_pi_pin: spi1-cs0-pi-pin {
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+ pins = "PI16";
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+ function = "spi1";
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+ };
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+
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+ /omit-if-no-ref/
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+ spi1_cs1_pi_pin: spi1-cs1-pi-pin {
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+ pins = "PI15";
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+ function = "spi1";
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+ };
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+
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uart0_pb_pins: uart0-pb-pins {
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pins = "PB22", "PB23";
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function = "uart0";
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@@ -409,6 +650,45 @@
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wdt: watchdog@1c20c90 {
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compatible = "allwinner,sun4i-a10-wdt";
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reg = <0x01c20c90 0x10>;
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+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&osc24M>;
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+ };
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+
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+ ir0: ir@1c21800 {
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+ compatible = "allwinner,sun8i-r40-ir",
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+ "allwinner,sun6i-a31-ir";
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+ reg = <0x01c21800 0x400>;
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+ pinctrl-0 = <&ir0_pins>;
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+ pinctrl-names = "default";
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+ clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>;
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+ clock-names = "apb", "ir";
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+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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+ resets = <&ccu RST_BUS_IR0>;
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+ status = "disabled";
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+ };
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+
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+ ir1: ir@1c21c00 {
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+ compatible = "allwinner,sun8i-r40-ir",
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+ "allwinner,sun6i-a31-ir";
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+ reg = <0x01c21c00 0x400>;
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+ pinctrl-0 = <&ir1_pins>;
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+ pinctrl-names = "default";
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+ clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>;
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+ clock-names = "apb", "ir";
|
|
|
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ resets = <&ccu RST_BUS_IR1>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ ths: thermal-sensor@1c24c00 {
|
|
|
+ compatible = "allwinner,sun8i-r40-ths";
|
|
|
+ reg = <0x01c24c00 0x100>;
|
|
|
+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
|
|
|
+ clock-names = "bus", "mod";
|
|
|
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ resets = <&ccu RST_BUS_THS>;
|
|
|
+ /* TODO: add nvmem-cells for calibration */
|
|
|
+ #thermal-sensor-cells = <1>;
|
|
|
};
|
|
|
|
|
|
uart0: serial@1c28000 {
|
|
@@ -518,6 +798,8 @@
|
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
clocks = <&ccu CLK_BUS_I2C1>;
|
|
|
resets = <&ccu RST_BUS_I2C1>;
|
|
|
+ pinctrl-0 = <&i2c1_pins>;
|
|
|
+ pinctrl-names = "default";
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
@@ -529,6 +811,8 @@
|
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
clocks = <&ccu CLK_BUS_I2C2>;
|
|
|
resets = <&ccu RST_BUS_I2C2>;
|
|
|
+ pinctrl-0 = <&i2c2_pins>;
|
|
|
+ pinctrl-names = "default";
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
@@ -540,6 +824,8 @@
|
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
clocks = <&ccu CLK_BUS_I2C3>;
|
|
|
resets = <&ccu RST_BUS_I2C3>;
|
|
|
+ pinctrl-0 = <&i2c3_pins>;
|
|
|
+ pinctrl-names = "default";
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
@@ -551,22 +837,33 @@
|
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
clocks = <&ccu CLK_BUS_I2C4>;
|
|
|
resets = <&ccu RST_BUS_I2C4>;
|
|
|
+ pinctrl-0 = <&i2c4_pins>;
|
|
|
+ pinctrl-names = "default";
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
|
};
|
|
|
|
|
|
- ahci: sata@1c18000 {
|
|
|
- compatible = "allwinner,sun8i-r40-ahci";
|
|
|
- reg = <0x01c18000 0x1000>;
|
|
|
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
|
|
|
- resets = <&ccu RST_BUS_SATA>;
|
|
|
- resets-name = "ahci";
|
|
|
- #address-cells = <1>;
|
|
|
- #size-cells = <0>;
|
|
|
- status = "disabled";
|
|
|
-
|
|
|
+ mali: gpu@1c40000 {
|
|
|
+ compatible = "allwinner,sun8i-r40-mali", "arm,mali-400";
|
|
|
+ reg = <0x01c40000 0x10000>;
|
|
|
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ interrupt-names = "gp",
|
|
|
+ "gpmmu",
|
|
|
+ "pp0",
|
|
|
+ "ppmmu0",
|
|
|
+ "pp1",
|
|
|
+ "ppmmu1",
|
|
|
+ "pmu";
|
|
|
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
|
|
|
+ clock-names = "bus", "core";
|
|
|
+ resets = <&ccu RST_BUS_GPU>;
|
|
|
};
|
|
|
|
|
|
gmac: ethernet@1c50000 {
|
|
@@ -588,6 +885,16 @@
|
|
|
};
|
|
|
};
|
|
|
|
|
|
+ mbus: dram-controller@1c62000 {
|
|
|
+ compatible = "allwinner,sun8i-r40-mbus";
|
|
|
+ reg = <0x01c62000 0x1000>;
|
|
|
+ clocks = <&ccu 155>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <1>;
|
|
|
+ dma-ranges = <0x00000000 0x40000000 0x80000000>;
|
|
|
+ #interconnect-cells = <1>;
|
|
|
+ };
|
|
|
+
|
|
|
tcon_top: tcon-top@1c70000 {
|
|
|
compatible = "allwinner,sun8i-r40-tcon-top";
|
|
|
reg = <0x01c70000 0x1000>;
|
|
@@ -614,12 +921,9 @@
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
tcon_top_mixer0_in: port@0 {
|
|
|
- #address-cells = <1>;
|
|
|
- #size-cells = <0>;
|
|
|
reg = <0>;
|
|
|
|
|
|
- tcon_top_mixer0_in_mixer0: endpoint@0 {
|
|
|
- reg = <0>;
|
|
|
+ tcon_top_mixer0_in_mixer0: endpoint {
|
|
|
remote-endpoint = <&mixer0_out_tcon_top>;
|
|
|
};
|
|
|
};
|
|
@@ -713,7 +1017,7 @@
|
|
|
compatible = "allwinner,sun8i-r40-tcon-tv";
|
|
|
reg = <0x01c73000 0x1000>;
|
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
|
|
|
+ clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
|
|
|
clock-names = "ahb", "tcon-ch1";
|
|
|
resets = <&ccu RST_BUS_TCON_TV0>;
|
|
|
reset-names = "lcd";
|
|
@@ -756,7 +1060,7 @@
|
|
|
compatible = "allwinner,sun8i-r40-tcon-tv";
|
|
|
reg = <0x01c74000 0x1000>;
|
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
|
|
|
+ clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
|
|
|
clock-names = "ahb", "tcon-ch1";
|
|
|
resets = <&ccu RST_BUS_TCON_TV1>;
|
|
|
reset-names = "lcd";
|
|
@@ -798,7 +1102,7 @@
|
|
|
gic: interrupt-controller@1c81000 {
|
|
|
compatible = "arm,gic-400";
|
|
|
reg = <0x01c81000 0x1000>,
|
|
|
- <0x01c82000 0x1000>,
|
|
|
+ <0x01c82000 0x2000>,
|
|
|
<0x01c84000 0x2000>,
|
|
|
<0x01c86000 0x2000>;
|
|
|
interrupt-controller;
|
|
@@ -818,7 +1122,7 @@
|
|
|
resets = <&ccu RST_BUS_HDMI1>;
|
|
|
reset-names = "ctrl";
|
|
|
phys = <&hdmi_phy>;
|
|
|
- phy-names = "hdmi-phy";
|
|
|
+ phy-names = "phy";
|
|
|
status = "disabled";
|
|
|
|
|
|
ports {
|
|
@@ -843,7 +1147,7 @@
|
|
|
compatible = "allwinner,sun8i-r40-hdmi-phy";
|
|
|
reg = <0x01ef0000 0x10000>;
|
|
|
clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
|
|
|
- <&ccu 7>, <&ccu 16>;
|
|
|
+ <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
|
|
|
clock-names = "bus", "mod", "pll-0", "pll-1";
|
|
|
resets = <&ccu RST_BUS_HDMI0>;
|
|
|
reset-names = "phy";
|
|
@@ -851,6 +1155,15 @@
|
|
|
};
|
|
|
};
|
|
|
|
|
|
+ pmu {
|
|
|
+ compatible = "arm,cortex-a7-pmu";
|
|
|
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
|
|
+ };
|
|
|
+
|
|
|
timer {
|
|
|
compatible = "arm,armv7-timer";
|
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|