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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (C) 2021 Toradex
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+ * Copyright (C) 2016 Broadcom
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+ */
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+
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+/**
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+ * DOC: FXL6408 I2C to GPIO expander.
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+ *
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+ * This chip has 8 GPIO lines out of it, and is controlled by an I2C
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+ * bus (a pair of lines), providing 4x expansion of GPIO lines. It
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+ * also provides an interrupt line out for notifying of state changes.
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+ *
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+ * Any preconfigured state will be left in place until the GPIO lines
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+ * get activated. At power on, everything is treated as an input,
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+ * default input is HIGH and pulled-up, all interrupts are masked.
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+ *
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+ * Documentation can be found at:
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+ * ------------------------------
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+ *
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+ * https://www.fairchildsemi.com/datasheets/FX/FXL6408.pdf
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+ *
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+ * This driver bases on:
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+ * ---------------------
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+ *
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+ * - the original driver by Eric Anholt <eric@anholt.net>:
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+ * https://patchwork.kernel.org/patch/9148419/
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+ * - the Toradex version by Max Krummenacher <max.krummenacher@toradex.com>:
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+ * http://git.toradex.com/cgit/linux-toradex.git/tree/drivers/gpio/gpio-fxl6408.c?h=toradex_5.4-2.3.x-imx
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+ * - the U-boot PCA953x driver by Peng Fan <van.freenix@gmail.com>:
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+ * drivers/gpio/pca953x_gpio.c
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+ *
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+ * TODO:
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+ * - Add interrupts support
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+ * - Replace deprecated callbacks direction_input/output() with set_flags()
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+ */
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+
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+#include <asm-generic/gpio.h>
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+#include <asm/global_data.h>
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+#include <common.h>
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+#include <dm.h>
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+#include <dm/device_compat.h>
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+#include <dt-bindings/gpio/gpio.h>
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+#include <i2c.h>
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+#include <linux/bitops.h>
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+#include <log.h>
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+
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+#define REG_DEVID_CTRL 0x1
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+# define SW_RST BIT(0)
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+# define RST_INT BIT(1)
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+/** 0b101 is the Manufacturer's ID assigned to Fairchild by Nokia */
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+# define MF_ID_FAIRCHILD 5
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+
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+/** Bits set here indicate that the GPIO is an output */
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+#define REG_IO_DIR 0x3
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+
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+/**
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+ * REG_OUT_STATE - a high-output state register address
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+ *
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+ * Bits set here, when the corresponding bit of REG_IO_DIR is set,
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+ * drive the output high instead of low.
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+ */
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+#define REG_OUT_STATE 0x5
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+
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+/** Bits here make the output High-Z, instead of the OUTPUT value */
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+#define REG_OUT_HIGH_Z 0x7
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+
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+/**
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+ * REG_IN_DEFAULT_STATE - an interrupt state register address
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+ *
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+ * Bits here define the expected input state of the GPIO.
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+ * INTERRUPT_STATUS bits will be set when the INPUT transitions away
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+ * from this value.
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+ */
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+#define REG_IN_DEFAULT_STATE 0x9
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+
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+/**
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+ * REG_PULL_ENABLE - a pull-up/down enable state register address
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+ *
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+ * Bits here enable either pull up or pull down according to
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+ * REG_PULL_MODE.
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+ */
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+#define REG_PULL_ENABLE 0xb
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+
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+/**
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+ * REG_PULL_MODE - a pull-up/pull-down mode state register address
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+ *
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+ * Bits set here selects a pull-up/pull-down state of pin, which
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+ * is configured as Input and the corresponding REG_PULL_ENABLE bit is
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+ * set.
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+ */
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+#define REG_PULL_MODE 0xd
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+
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+/** Returns the current status (1 = HIGH) of the input pins */
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+#define REG_IN_STATUS 0xf
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+
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+/** Mask of pins which can generate interrupts */
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+#define REG_INT_MASK 0x11
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+
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+/** Mask of pins which have generated an interrupt. Cleared on read */
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+#define REG_INT_STATUS 0x13
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+
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+/* Manufacturer's ID getting from Device ID & Ctrl register */
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+enum {
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+ MF_ID_MASK = GENMASK(7, 5),
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+ MF_ID_SHIFT = 5,
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+};
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+
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+/* Firmware revision getting from Device ID & Ctrl register */
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+enum {
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+ FW_REV_MASK = GENMASK(4, 2),
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+ FW_REV_SHIFT = 2,
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+};
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+
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+enum io_direction {
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+ DIR_IN = 0,
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+ DIR_OUT = 1,
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+};
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+
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+/**
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+ * struct fxl6408_info - Data for fxl6408
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+ *
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+ * @dev: udevice structure for the device
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+ * @addr: i2c slave address
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+ * @device_id: hold the value of device id register
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+ * @reg_io_dir: hold the value of direction register
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+ * @reg_output: hold the value of output register
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+ */
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+struct fxl6408_info {
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+ struct udevice *dev;
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+ int addr;
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+ u8 device_id;
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+ u8 reg_io_dir;
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+ u8 reg_output;
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+};
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+
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+static inline int fxl6408_write(struct udevice *dev, int reg, u8 val)
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+{
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+ return dm_i2c_write(dev, reg, &val, 1);
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+}
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+
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+static int fxl6408_read(struct udevice *dev, int reg)
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+{
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+ int ret;
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+ u8 tmp;
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+
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+ ret = dm_i2c_read(dev, reg, &tmp, 1);
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+ if (!ret)
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+ ret = tmp;
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+
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+ return ret;
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+}
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+
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+/**
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+ * fxl6408_is_output() - check whether the gpio configures as either
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+ * output or input.
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+ *
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+ * @dev: an instance of a driver
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+ * @offset: a gpio offset
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+ *
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+ * Return: false - input, true - output.
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+ */
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+static bool fxl6408_is_output(struct udevice *dev, int offset)
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+{
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+ struct fxl6408_info *info = dev_get_plat(dev);
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+
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+ return info->reg_io_dir & BIT(offset);
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+}
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+
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+static int fxl6408_get_value(struct udevice *dev, uint offset)
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+{
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+ int ret, reg = fxl6408_is_output(dev, offset) ? REG_OUT_STATE : REG_IN_STATUS;
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+
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+ ret = fxl6408_read(dev, reg);
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+ if (ret < 0)
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+ return ret;
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+
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+ return !!(ret & BIT(offset));
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+}
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+
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+static int fxl6408_set_value(struct udevice *dev, uint offset, int value)
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+{
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+ struct fxl6408_info *info = dev_get_plat(dev);
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+ u8 val;
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+ int ret;
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+
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+ if (value)
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+ val = info->reg_output | BIT(offset);
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+ else
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+ val = info->reg_output & ~BIT(offset);
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+
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+ ret = fxl6408_write(dev, REG_OUT_STATE, val);
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+ if (ret < 0)
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+ return ret;
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+
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+ info->reg_output = val;
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+
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+ return 0;
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+}
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+
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+static int fxl6408_set_direction(struct udevice *dev, uint offset,
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+ enum io_direction dir)
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+{
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+ struct fxl6408_info *info = dev_get_plat(dev);
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+ u8 val;
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+ int ret;
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+
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+ if (dir == DIR_IN)
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+ val = info->reg_io_dir & ~BIT(offset);
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+ else
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+ val = info->reg_io_dir | BIT(offset);
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+
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+ ret = fxl6408_write(dev, REG_IO_DIR, val);
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+ if (ret < 0)
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+ return ret;
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+
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+ info->reg_io_dir = val;
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+
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+ return 0;
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+}
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+
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+static int fxl6408_direction_input(struct udevice *dev, uint offset)
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+{
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+ return fxl6408_set_direction(dev, offset, DIR_IN);
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+}
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+
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+static int fxl6408_direction_output(struct udevice *dev, uint offset, int value)
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+{
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+ int ret;
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+
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+ /* Configure output value */
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+ ret = fxl6408_set_value(dev, offset, value);
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+ if (ret < 0)
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+ return ret;
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+
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+ /* Configure direction as output */
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+ fxl6408_set_direction(dev, offset, DIR_OUT);
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+
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+ return 0;
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+}
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+
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+static int fxl6408_get_function(struct udevice *dev, uint offset)
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+{
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+ if (fxl6408_is_output(dev, offset))
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+ return GPIOF_OUTPUT;
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+
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+ return GPIOF_INPUT;
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+}
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+
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+static int fxl6408_xlate(struct udevice *dev, struct gpio_desc *desc,
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+ struct ofnode_phandle_args *args)
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+{
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+ desc->offset = args->args[0];
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+ desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
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+
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+ return 0;
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+}
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+
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+static const struct dm_gpio_ops fxl6408_ops = {
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+ .direction_input = fxl6408_direction_input,
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+ .direction_output = fxl6408_direction_output,
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+ .get_value = fxl6408_get_value,
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+ .set_value = fxl6408_set_value,
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+ .get_function = fxl6408_get_function,
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+ .xlate = fxl6408_xlate,
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+};
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+
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+static int fxl6408_probe(struct udevice *dev)
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+{
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+ struct fxl6408_info *info = dev_get_plat(dev);
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+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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+ char bank_name[32], *tmp_str;
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+ int addr, ret, size;
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+ u32 val32;
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+
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+ addr = dev_read_addr(dev);
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+ if (addr == 0)
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+ return -EINVAL;
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+
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+ info->addr = addr;
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+
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+ /*
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+ * Check the device ID register to see if it's responding.
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+ * This also clears RST_INT as a side effect, so we won't get
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+ * the "we've been power cycled" interrupt once interrupts
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+ * being enabled.
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+ */
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+ ret = fxl6408_read(dev, REG_DEVID_CTRL);
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+ if (ret < 0) {
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+ dev_err(dev, "FXL6408 probe returned %d\n", ret);
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+ return ret;
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+ }
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+
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+ if ((ret & MF_ID_MASK) >> MF_ID_SHIFT != MF_ID_FAIRCHILD) {
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+ dev_err(dev, "FXL6408 probe: wrong Manufacturer's ID: 0x%02x\n", ret);
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+ return -ENXIO;
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+ }
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+ info->device_id = ret;
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+
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+ /*
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+ * Disable High-Z of outputs, so that the OUTPUT updates
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+ * actually take effect.
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+ */
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+ ret = fxl6408_write(dev, REG_OUT_HIGH_Z, (u8)0);
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+ if (ret < 0) {
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+ dev_err(dev, "Error writing High-Z register\n");
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+ return ret;
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+ }
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+
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+ /*
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+ * If configured, set initial output state and direction,
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+ * otherwise read them from the chip.
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+ */
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+ if (dev_read_u32(dev, "initial_io_dir", &val32)) {
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+ ret = fxl6408_read(dev, REG_IO_DIR);
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+ if (ret < 0) {
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+ dev_err(dev, "Error reading direction register\n");
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+ return ret;
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+ }
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+ info->reg_io_dir = ret;
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+ } else {
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+ info->reg_io_dir = val32 & 0xFF;
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+ ret = fxl6408_write(dev, REG_IO_DIR, info->reg_io_dir);
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+ if (ret < 0) {
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+ dev_err(dev, "Error setting direction register\n");
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+ return ret;
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+ }
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+ }
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+
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+ if (dev_read_u32(dev, "initial_output", &val32)) {
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+ ret = fxl6408_read(dev, REG_OUT_STATE);
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+ if (ret < 0) {
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+ dev_err(dev, "Error reading output register\n");
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+ return ret;
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+ }
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+ info->reg_output = ret;
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+ } else {
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+ info->reg_output = val32 & 0xFF;
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+ ret = fxl6408_write(dev, REG_OUT_STATE, info->reg_output);
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+ if (ret < 0) {
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+ dev_err(dev, "Error setting output register\n");
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+ return ret;
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+ }
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+ }
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+
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+ tmp_str = (char *)dev_read_prop(dev, "bank-name", &size);
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+ if (tmp_str) {
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+ snprintf(bank_name, sizeof(bank_name), "%s@%x_", tmp_str,
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+ info->addr);
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+ } else {
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+ snprintf(bank_name, sizeof(bank_name), "gpio@%x_", info->addr);
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+ }
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+
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+ tmp_str = strdup(bank_name);
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+ if (!tmp_str)
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+ return -ENOMEM;
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+
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+ uc_priv->bank_name = tmp_str;
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+ uc_priv->gpio_count = dev_get_driver_data(dev);
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+ uc_priv->gpio_base = -1;
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+
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+ dev_dbg(dev, "%s (FW rev. %d) is ready\n", bank_name,
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+ (info->device_id & FW_REV_MASK) >> FW_REV_SHIFT);
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+
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+ return 0;
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+}
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+
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+static const struct udevice_id fxl6408_ids[] = {
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+ { .compatible = "fcs,fxl6408", .data = 8 },
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+ { }
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+};
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+
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+U_BOOT_DRIVER(fxl6408_gpio) = {
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+ .name = "fxl6408_gpio",
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+ .id = UCLASS_GPIO,
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+ .ops = &fxl6408_ops,
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+ .probe = fxl6408_probe,
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+ .of_match = fxl6408_ids,
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+ .plat_auto = sizeof(struct fxl6408_info),
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+};
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