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@@ -0,0 +1,467 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Rockchip AXI PCIe host controller driver
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+ *
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+ * Copyright (c) 2016 Rockchip, Inc.
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+ * Copyright (c) 2020 Amarula Solutions(India)
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+ * Copyright (c) 2020 Jagan Teki <jagan@amarulasolutions.com>
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+ * Copyright (c) 2019 Patrick Wildt <patrick@blueri.se>
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+ * Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org>
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+ *
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+ * Bits taken from Linux Rockchip PCIe host controller.
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+ */
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+
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+#include <common.h>
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+#include <clk.h>
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+#include <dm.h>
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+#include <dm/device_compat.h>
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+#include <pci.h>
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+#include <power-domain.h>
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+#include <power/regulator.h>
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+#include <reset.h>
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+#include <syscon.h>
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+#include <asm/io.h>
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+#include <asm-generic/gpio.h>
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+#include <asm/arch-rockchip/clock.h>
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+#include <linux/iopoll.h>
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+
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+#include "pcie_rockchip.h"
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+static int rockchip_pcie_off_conf(pci_dev_t bdf, uint offset)
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+{
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+ unsigned int bus = PCI_BUS(bdf);
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+ unsigned int dev = PCI_DEV(bdf);
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+ unsigned int func = PCI_FUNC(bdf);
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+
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+ return (bus << 20) | (dev << 15) | (func << 12) | (offset & ~0x3);
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+}
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+
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+static int rockchip_pcie_rd_conf(const struct udevice *udev, pci_dev_t bdf,
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+ uint offset, ulong *valuep,
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+ enum pci_size_t size)
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+{
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+ struct rockchip_pcie *priv = dev_get_priv(udev);
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+ unsigned int bus = PCI_BUS(bdf);
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+ unsigned int dev = PCI_DEV(bdf);
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+ int where = rockchip_pcie_off_conf(bdf, offset);
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+ ulong value;
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+
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+ if (bus == priv->first_busno && dev == 0) {
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+ value = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + where);
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+ *valuep = pci_conv_32_to_size(value, offset, size);
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+ return 0;
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+ }
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+
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+ if ((bus == priv->first_busno + 1) && dev == 0) {
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+ value = readl(priv->axi_base + where);
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+ *valuep = pci_conv_32_to_size(value, offset, size);
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+ return 0;
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+ }
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+
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+ *valuep = pci_get_ff(size);
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+
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+ return 0;
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+}
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+
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+static int rockchip_pcie_wr_conf(struct udevice *udev, pci_dev_t bdf,
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+ uint offset, ulong value,
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+ enum pci_size_t size)
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+{
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+ struct rockchip_pcie *priv = dev_get_priv(udev);
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+ unsigned int bus = PCI_BUS(bdf);
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+ unsigned int dev = PCI_DEV(bdf);
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+ int where = rockchip_pcie_off_conf(bdf, offset);
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+ ulong old;
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+
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+ if (bus == priv->first_busno && dev == 0) {
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+ old = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + where);
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+ value = pci_conv_size_to_32(old, value, offset, size);
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+ writel(value, priv->apb_base + PCIE_RC_NORMAL_BASE + where);
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+ return 0;
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+ }
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+
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+ if ((bus == priv->first_busno + 1) && dev == 0) {
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+ old = readl(priv->axi_base + where);
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+ value = pci_conv_size_to_32(old, value, offset, size);
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+ writel(value, priv->axi_base + where);
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+ return 0;
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+ }
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+
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+ return 0;
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+}
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+
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+static int rockchip_pcie_atr_init(struct rockchip_pcie *priv)
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+{
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+ struct udevice *ctlr = pci_get_controller(priv->dev);
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+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
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+ u64 addr, size, offset;
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+ u32 type;
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+ int i, region;
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+
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+ /* Use region 0 to map PCI configuration space. */
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+ writel(25 - 1, priv->apb_base + PCIE_ATR_OB_ADDR0(0));
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+ writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(0));
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+ writel(PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID,
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+ priv->apb_base + PCIE_ATR_OB_DESC0(0));
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+ writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(0));
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+
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+ for (i = 0; i < hose->region_count; i++) {
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+ if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
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+ continue;
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+
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+ if (hose->regions[i].flags == PCI_REGION_IO)
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+ type = PCIE_ATR_HDR_IO;
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+ else
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+ type = PCIE_ATR_HDR_MEM;
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+
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+ /* Only support identity mappings. */
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+ if (hose->regions[i].bus_start !=
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+ hose->regions[i].phys_start)
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+ return -EINVAL;
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+
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+ /* Only support mappings aligned on a region boundary. */
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+ addr = hose->regions[i].bus_start;
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+ if (addr & (PCIE_ATR_OB_REGION_SIZE - 1))
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+ return -EINVAL;
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+
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+ /* Mappings should lie between AXI and APB regions. */
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+ size = hose->regions[i].size;
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+ if (addr < (u64)priv->axi_base + PCIE_ATR_OB_REGION0_SIZE)
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+ return -EINVAL;
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+ if (addr + size > (u64)priv->apb_base)
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+ return -EINVAL;
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+
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+ offset = addr - (u64)priv->axi_base - PCIE_ATR_OB_REGION0_SIZE;
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+ region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE);
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+ while (size > 0) {
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+ writel(32 - 1,
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+ priv->apb_base + PCIE_ATR_OB_ADDR0(region));
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+ writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(region));
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+ writel(type | PCIE_ATR_HDR_RID,
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+ priv->apb_base + PCIE_ATR_OB_DESC0(region));
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+ writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(region));
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+
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+ addr += PCIE_ATR_OB_REGION_SIZE;
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+ size -= PCIE_ATR_OB_REGION_SIZE;
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+ region++;
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+ }
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+ }
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+
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+ /* Passthrough inbound translations unmodified. */
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+ writel(32 - 1, priv->apb_base + PCIE_ATR_IB_ADDR0(2));
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+ writel(0, priv->apb_base + PCIE_ATR_IB_ADDR1(2));
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+
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+ return 0;
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+}
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+
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+static int rockchip_pcie_init_port(struct udevice *dev)
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+{
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+ struct rockchip_pcie *priv = dev_get_priv(dev);
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+ u32 cr, val, status;
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+ int ret;
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+
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+ if (dm_gpio_is_valid(&priv->ep_gpio))
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+ dm_gpio_set_value(&priv->ep_gpio, 0);
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+
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+ ret = reset_assert(&priv->aclk_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to assert aclk reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ ret = reset_assert(&priv->pclk_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to assert pclk reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ ret = reset_assert(&priv->pm_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to assert pm reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ ret = reset_assert(&priv->core_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to assert core reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ ret = reset_assert(&priv->mgmt_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to assert mgmt reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ ret = reset_assert(&priv->mgmt_sticky_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to assert mgmt-sticky reset (ret=%d)\n",
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+ ret);
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+ return ret;
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+ }
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+
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+ ret = reset_assert(&priv->pipe_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to assert pipe reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ udelay(10);
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+
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+ ret = reset_deassert(&priv->pm_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to deassert pm reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ ret = reset_deassert(&priv->aclk_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to deassert aclk reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ ret = reset_deassert(&priv->pclk_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to deassert pclk reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ /* Select GEN1 for now */
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+ cr = PCIE_CLIENT_GEN_SEL_1;
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+ /* Set Root complex mode */
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+ cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
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+ writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);
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+
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+ ret = reset_deassert(&priv->mgmt_sticky_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to deassert mgmt-sticky reset (ret=%d)\n",
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+ ret);
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+ return ret;
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+ }
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+
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+ ret = reset_deassert(&priv->core_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to deassert core reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ ret = reset_deassert(&priv->mgmt_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to deassert mgmt reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ ret = reset_deassert(&priv->pipe_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to deassert pipe reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ /* Enable Gen1 training */
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+ writel(PCIE_CLIENT_LINK_TRAIN_ENABLE,
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+ priv->apb_base + PCIE_CLIENT_CONFIG);
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+
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+ if (dm_gpio_is_valid(&priv->ep_gpio))
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+ dm_gpio_set_value(&priv->ep_gpio, 1);
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+
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+ ret = readl_poll_sleep_timeout
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+ (priv->apb_base + PCIE_CLIENT_BASIC_STATUS1,
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+ status, PCIE_LINK_UP(status), 20, 500 * 1000);
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+ if (ret) {
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+ dev_err(dev, "PCIe link training gen1 timeout!\n");
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+ return ret;
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+ }
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+
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+ /* Initialize Root Complex registers. */
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+ writel(PCIE_LM_VENDOR_ROCKCHIP, priv->apb_base + PCIE_LM_VENDOR_ID);
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+ writel(PCI_CLASS_BRIDGE_PCI << 16,
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+ priv->apb_base + PCIE_RC_BASE + PCI_CLASS_REVISION);
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+ writel(PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS,
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+ priv->apb_base + PCIE_LM_RCBAR);
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+
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+ if (dev_read_bool(dev, "aspm-no-l0s")) {
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+ val = readl(priv->apb_base + PCIE_RC_PCIE_LCAP);
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+ val &= ~PCIE_RC_PCIE_LCAP_APMS_L0S;
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+ writel(val, priv->apb_base + PCIE_RC_PCIE_LCAP);
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+ }
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+
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+ /* Configure Address Translation. */
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+ ret = rockchip_pcie_atr_init(priv);
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+ if (ret) {
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+ dev_err(dev, "PCIE-%d: ATR init failed\n", dev->seq);
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+static int rockchip_pcie_set_vpcie(struct udevice *dev)
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+{
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+ struct rockchip_pcie *priv = dev_get_priv(dev);
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+ int ret;
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+
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+ if (!IS_ERR(priv->vpcie3v3)) {
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+ ret = regulator_set_enable(priv->vpcie3v3, true);
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+ if (ret) {
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+ dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n",
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+ ret);
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+ return ret;
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+ }
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+ }
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+
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+ ret = regulator_set_enable(priv->vpcie1v8, true);
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+ if (ret) {
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+ dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n", ret);
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+ goto err_disable_3v3;
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+ }
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+
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+ ret = regulator_set_enable(priv->vpcie0v9, true);
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+ if (ret) {
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+ dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n", ret);
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+ goto err_disable_1v8;
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+ }
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+
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+ return 0;
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+
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+err_disable_1v8:
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+ regulator_set_enable(priv->vpcie1v8, false);
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+err_disable_3v3:
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+ if (!IS_ERR(priv->vpcie3v3))
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+ regulator_set_enable(priv->vpcie3v3, false);
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+ return ret;
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+}
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+
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+static int rockchip_pcie_parse_dt(struct udevice *dev)
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+{
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+ struct rockchip_pcie *priv = dev_get_priv(dev);
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+ int ret;
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+
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+ priv->axi_base = dev_read_addr_name(dev, "axi-base");
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+ if (!priv->axi_base)
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+ return -ENODEV;
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+
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+ priv->apb_base = dev_read_addr_name(dev, "apb-base");
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+ if (!priv->axi_base)
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+ return -ENODEV;
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+
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+ ret = gpio_request_by_name(dev, "ep-gpios", 0,
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+ &priv->ep_gpio, GPIOD_IS_OUT);
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+ if (ret) {
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+ dev_err(dev, "failed to find ep-gpios property\n");
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+ return ret;
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+ }
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+
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+ ret = reset_get_by_name(dev, "core", &priv->core_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to get core reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ ret = reset_get_by_name(dev, "mgmt", &priv->mgmt_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to get mgmt reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ ret = reset_get_by_name(dev, "mgmt-sticky", &priv->mgmt_sticky_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to get mgmt-sticky reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ ret = reset_get_by_name(dev, "pipe", &priv->pipe_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to get pipe reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ ret = reset_get_by_name(dev, "pm", &priv->pm_rst);
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+ if (ret) {
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+ dev_err(dev, "failed to get pm reset (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ ret = reset_get_by_name(dev, "pclk", &priv->pclk_rst);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dev, "failed to get pclk reset (ret=%d)\n", ret);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = reset_get_by_name(dev, "aclk", &priv->aclk_rst);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dev, "failed to get aclk reset (ret=%d)\n", ret);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = device_get_supply_regulator(dev, "vpcie3v3-supply",
|
|
|
+ &priv->vpcie3v3);
|
|
|
+ if (ret && ret != -ENOENT) {
|
|
|
+ dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = device_get_supply_regulator(dev, "vpcie1v8-supply",
|
|
|
+ &priv->vpcie1v8);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dev, "failed to get vpcie1v8 supply (ret=%d)\n", ret);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = device_get_supply_regulator(dev, "vpcie0v9-supply",
|
|
|
+ &priv->vpcie0v9);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dev, "failed to get vpcie0v9 supply (ret=%d)\n", ret);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int rockchip_pcie_probe(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct rockchip_pcie *priv = dev_get_priv(dev);
|
|
|
+ struct udevice *ctlr = pci_get_controller(dev);
|
|
|
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ priv->first_busno = dev->seq;
|
|
|
+ priv->dev = dev;
|
|
|
+
|
|
|
+ ret = rockchip_pcie_parse_dt(dev);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ ret = rockchip_pcie_set_vpcie(dev);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ ret = rockchip_pcie_init_port(dev);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ dev_info(dev, "PCIE-%d: Link up (Bus%d)\n",
|
|
|
+ dev->seq, hose->first_busno);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static const struct dm_pci_ops rockchip_pcie_ops = {
|
|
|
+ .read_config = rockchip_pcie_rd_conf,
|
|
|
+ .write_config = rockchip_pcie_wr_conf,
|
|
|
+};
|
|
|
+
|
|
|
+static const struct udevice_id rockchip_pcie_ids[] = {
|
|
|
+ { .compatible = "rockchip,rk3399-pcie" },
|
|
|
+ { }
|
|
|
+};
|
|
|
+
|
|
|
+U_BOOT_DRIVER(rockchip_pcie) = {
|
|
|
+ .name = "rockchip_pcie",
|
|
|
+ .id = UCLASS_PCI,
|
|
|
+ .of_match = rockchip_pcie_ids,
|
|
|
+ .ops = &rockchip_pcie_ops,
|
|
|
+ .probe = rockchip_pcie_probe,
|
|
|
+ .priv_auto_alloc_size = sizeof(struct rockchip_pcie),
|
|
|
+};
|