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clk: starfive: jh7110: Add full i2c clocks

Correct the parent of i2c clocks and add full i2c clocks.
The code mainly is ported from tag JH7110_DVK_515_v3.9.3 of Devkits repo.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng 8 months ago
parent
commit
96ee0021ad
1 changed files with 52 additions and 18 deletions
  1. 52 18
      drivers/clk/starfive/clk-jh7110.c

+ 52 - 18
drivers/clk/starfive/clk-jh7110.c

@@ -425,6 +425,58 @@ static int jh7110_clk_init(struct udevice *dev)
 	       starfive_clk_divider(priv->sys,
 				    "nocstg_bus", "bus_root",
 				    SYS_OFFSET(JH7110_NOCSTG_BUS), 3));
+
+	/*I2C*/
+	clk_dm(JH7110_I2C0_CLK_APB,
+	       starfive_clk_gate(priv->sys,
+				 "u0_dw_i2c_clk_apb", "apb0",
+				 SYS_OFFSET(JH7110_I2C0_CLK_APB)));
+	clk_dm(JH7110_I2C0_CLK_CORE,
+	       starfive_clk_fix_factor(priv->sys,
+				       "u0_dw_i2c_clk_core", "u0_dw_i2c_clk_apb", 1, 1));
+	clk_dm(JH7110_I2C1_CLK_APB,
+	       starfive_clk_gate(priv->sys,
+				 "u1_dw_i2c_clk_apb", "apb0",
+				 SYS_OFFSET(JH7110_I2C1_CLK_APB)));
+	clk_dm(JH7110_I2C1_CLK_CORE,
+	       starfive_clk_fix_factor(priv->sys,
+				       "u1_dw_i2c_clk_core", "u1_dw_i2c_clk_apb", 1, 1));
+	clk_dm(JH7110_I2C2_CLK_APB,
+	       starfive_clk_gate(priv->sys,
+				 "u2_dw_i2c_clk_apb", "apb0",
+				 SYS_OFFSET(JH7110_I2C2_CLK_APB)));
+	clk_dm(JH7110_I2C2_CLK_CORE,
+	       starfive_clk_fix_factor(priv->sys,
+				       "u2_dw_i2c_clk_core", "u2_dw_i2c_clk_apb", 1, 1));
+	clk_dm(JH7110_I2C3_CLK_APB,
+	       starfive_clk_gate(priv->sys,
+				 "u3_dw_i2c_clk_apb", "apb12",
+				 SYS_OFFSET(JH7110_I2C3_CLK_APB)));
+	clk_dm(JH7110_I2C3_CLK_CORE,
+	       starfive_clk_fix_factor(priv->sys,
+				       "u3_dw_i2c_clk_core", "u3_dw_i2c_clk_apb", 1, 1));
+	clk_dm(JH7110_I2C4_CLK_APB,
+	       starfive_clk_gate(priv->sys,
+				 "u4_dw_i2c_clk_apb", "apb12",
+				 SYS_OFFSET(JH7110_I2C4_CLK_APB)));
+	clk_dm(JH7110_I2C4_CLK_CORE,
+	       starfive_clk_fix_factor(priv->sys,
+				       "u4_dw_i2c_clk_core", "u4_dw_i2c_clk_apb", 1, 1));
+	clk_dm(JH7110_I2C5_CLK_APB,
+	       starfive_clk_gate(priv->sys,
+				 "u5_dw_i2c_clk_apb", "apb12",
+				 SYS_OFFSET(JH7110_I2C5_CLK_APB)));
+	clk_dm(JH7110_I2C5_CLK_CORE,
+	       starfive_clk_fix_factor(priv->sys,
+				       "u5_dw_i2c_clk_core", "u5_dw_i2c_clk_apb", 1, 1));
+	clk_dm(JH7110_I2C6_CLK_APB,
+	       starfive_clk_gate(priv->sys,
+				 "u6_dw_i2c_clk_apb", "apb12",
+				 SYS_OFFSET(JH7110_I2C6_CLK_APB)));
+	clk_dm(JH7110_I2C6_CLK_CORE,
+	       starfive_clk_fix_factor(priv->sys,
+				       "u6_dw_i2c_clk_core", "u6_dw_i2c_clk_apb", 1, 1));
+
 	/*QSPI*/
 	clk_dm(JH7110_QSPI_CLK_AHB,
 	       starfive_clk_gate(priv->sys,
@@ -699,24 +751,6 @@ static int jh7110_clk_init(struct udevice *dev)
 				    "u0_dom_vout_top_clk_mipiphy_ref", "osc",
 				    SYS_OFFSET(JH7110_MCLK_INNER), 2));
 
-	/*i2c5*/
-	clk_dm(JH7110_I2C5_CLK_APB,
-		starfive_clk_gate(priv->sys,
-			"u5_dw_i2c_clk_apb", "apb0",
-			SYS_OFFSET(JH7110_I2C5_CLK_APB)));
-	clk_dm(JH7110_I2C5_CLK_CORE,
-		starfive_clk_fix_factor(priv->sys,
-			"u5_dw_i2c_clk_core", "u5_dw_i2c_clk_apb", 1, 1));
-
-	/*i2c2*/
-	clk_dm(JH7110_I2C2_CLK_APB,
-		starfive_clk_gate(priv->sys,
-			"u2_dw_i2c_clk_apb", "apb0",
-			SYS_OFFSET(JH7110_I2C2_CLK_APB)));
-	clk_dm(JH7110_I2C2_CLK_CORE,
-		starfive_clk_fix_factor(priv->sys,
-			"u2_dw_i2c_clk_core", "u2_dw_i2c_clk_apb", 1, 1));
-
 	/*pcie0*/
 	clk_dm(JH7110_PCIE0_CLK_TL,
 		starfive_clk_gate(priv->stg,