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@@ -425,6 +425,58 @@ static int jh7110_clk_init(struct udevice *dev)
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starfive_clk_divider(priv->sys,
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"nocstg_bus", "bus_root",
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SYS_OFFSET(JH7110_NOCSTG_BUS), 3));
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+
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+ /*I2C*/
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+ clk_dm(JH7110_I2C0_CLK_APB,
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+ starfive_clk_gate(priv->sys,
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+ "u0_dw_i2c_clk_apb", "apb0",
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+ SYS_OFFSET(JH7110_I2C0_CLK_APB)));
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+ clk_dm(JH7110_I2C0_CLK_CORE,
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+ starfive_clk_fix_factor(priv->sys,
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+ "u0_dw_i2c_clk_core", "u0_dw_i2c_clk_apb", 1, 1));
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+ clk_dm(JH7110_I2C1_CLK_APB,
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+ starfive_clk_gate(priv->sys,
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+ "u1_dw_i2c_clk_apb", "apb0",
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+ SYS_OFFSET(JH7110_I2C1_CLK_APB)));
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+ clk_dm(JH7110_I2C1_CLK_CORE,
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+ starfive_clk_fix_factor(priv->sys,
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+ "u1_dw_i2c_clk_core", "u1_dw_i2c_clk_apb", 1, 1));
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+ clk_dm(JH7110_I2C2_CLK_APB,
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+ starfive_clk_gate(priv->sys,
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+ "u2_dw_i2c_clk_apb", "apb0",
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+ SYS_OFFSET(JH7110_I2C2_CLK_APB)));
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+ clk_dm(JH7110_I2C2_CLK_CORE,
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+ starfive_clk_fix_factor(priv->sys,
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+ "u2_dw_i2c_clk_core", "u2_dw_i2c_clk_apb", 1, 1));
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+ clk_dm(JH7110_I2C3_CLK_APB,
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+ starfive_clk_gate(priv->sys,
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+ "u3_dw_i2c_clk_apb", "apb12",
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+ SYS_OFFSET(JH7110_I2C3_CLK_APB)));
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+ clk_dm(JH7110_I2C3_CLK_CORE,
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+ starfive_clk_fix_factor(priv->sys,
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+ "u3_dw_i2c_clk_core", "u3_dw_i2c_clk_apb", 1, 1));
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+ clk_dm(JH7110_I2C4_CLK_APB,
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+ starfive_clk_gate(priv->sys,
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+ "u4_dw_i2c_clk_apb", "apb12",
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+ SYS_OFFSET(JH7110_I2C4_CLK_APB)));
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+ clk_dm(JH7110_I2C4_CLK_CORE,
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+ starfive_clk_fix_factor(priv->sys,
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+ "u4_dw_i2c_clk_core", "u4_dw_i2c_clk_apb", 1, 1));
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+ clk_dm(JH7110_I2C5_CLK_APB,
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+ starfive_clk_gate(priv->sys,
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+ "u5_dw_i2c_clk_apb", "apb12",
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+ SYS_OFFSET(JH7110_I2C5_CLK_APB)));
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+ clk_dm(JH7110_I2C5_CLK_CORE,
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+ starfive_clk_fix_factor(priv->sys,
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+ "u5_dw_i2c_clk_core", "u5_dw_i2c_clk_apb", 1, 1));
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+ clk_dm(JH7110_I2C6_CLK_APB,
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+ starfive_clk_gate(priv->sys,
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+ "u6_dw_i2c_clk_apb", "apb12",
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+ SYS_OFFSET(JH7110_I2C6_CLK_APB)));
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+ clk_dm(JH7110_I2C6_CLK_CORE,
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+ starfive_clk_fix_factor(priv->sys,
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+ "u6_dw_i2c_clk_core", "u6_dw_i2c_clk_apb", 1, 1));
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+
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/*QSPI*/
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clk_dm(JH7110_QSPI_CLK_AHB,
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starfive_clk_gate(priv->sys,
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@@ -699,24 +751,6 @@ static int jh7110_clk_init(struct udevice *dev)
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"u0_dom_vout_top_clk_mipiphy_ref", "osc",
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SYS_OFFSET(JH7110_MCLK_INNER), 2));
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- /*i2c5*/
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- clk_dm(JH7110_I2C5_CLK_APB,
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- starfive_clk_gate(priv->sys,
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- "u5_dw_i2c_clk_apb", "apb0",
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- SYS_OFFSET(JH7110_I2C5_CLK_APB)));
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- clk_dm(JH7110_I2C5_CLK_CORE,
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- starfive_clk_fix_factor(priv->sys,
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- "u5_dw_i2c_clk_core", "u5_dw_i2c_clk_apb", 1, 1));
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-
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- /*i2c2*/
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- clk_dm(JH7110_I2C2_CLK_APB,
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- starfive_clk_gate(priv->sys,
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- "u2_dw_i2c_clk_apb", "apb0",
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- SYS_OFFSET(JH7110_I2C2_CLK_APB)));
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- clk_dm(JH7110_I2C2_CLK_CORE,
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- starfive_clk_fix_factor(priv->sys,
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- "u2_dw_i2c_clk_core", "u2_dw_i2c_clk_apb", 1, 1));
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-
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/*pcie0*/
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clk_dm(JH7110_PCIE0_CLK_TL,
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starfive_clk_gate(priv->stg,
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