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@@ -14,27 +14,27 @@
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DECLARE_GLOBAL_DATA_PTR;
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-struct kw_sdram_bank {
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+struct sdram_bank {
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u32 win_bar;
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u32 win_sz;
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};
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-struct kw_sdram_addr_dec {
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- struct kw_sdram_bank sdram_bank[4];
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+struct sdram_addr_dec {
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+ struct sdram_bank sdram_bank[4];
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};
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-#define KW_REG_CPUCS_WIN_ENABLE (1 << 0)
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-#define KW_REG_CPUCS_WIN_WR_PROTECT (1 << 1)
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-#define KW_REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
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-#define KW_REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
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+#define REG_CPUCS_WIN_ENABLE (1 << 0)
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+#define REG_CPUCS_WIN_WR_PROTECT (1 << 1)
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+#define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
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+#define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
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/*
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- * kw_sdram_bar - reads SDRAM Base Address Register
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+ * mvebu_sdram_bar - reads SDRAM Base Address Register
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*/
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-u32 kw_sdram_bar(enum memory_bank bank)
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+u32 mvebu_sdram_bar(enum memory_bank bank)
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{
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- struct kw_sdram_addr_dec *base =
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- (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
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+ struct sdram_addr_dec *base =
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+ (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
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u32 result = 0;
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u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
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@@ -46,31 +46,31 @@ u32 kw_sdram_bar(enum memory_bank bank)
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}
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/*
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- * kw_sdram_bs_set - writes SDRAM Bank size
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+ * mvebu_sdram_bs_set - writes SDRAM Bank size
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*/
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-static void kw_sdram_bs_set(enum memory_bank bank, u32 size)
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+static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
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{
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- struct kw_sdram_addr_dec *base =
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- (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
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+ struct sdram_addr_dec *base =
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+ (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
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/* Read current register value */
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u32 reg = readl(&base->sdram_bank[bank].win_sz);
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/* Clear window size */
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- reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF);
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+ reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
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/* Set new window size */
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- reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24);
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+ reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
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writel(reg, &base->sdram_bank[bank].win_sz);
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}
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/*
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- * kw_sdram_bs - reads SDRAM Bank size
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+ * mvebu_sdram_bs - reads SDRAM Bank size
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*/
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-u32 kw_sdram_bs(enum memory_bank bank)
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+u32 mvebu_sdram_bs(enum memory_bank bank)
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{
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- struct kw_sdram_addr_dec *base =
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- (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
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+ struct sdram_addr_dec *base =
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+ (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
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u32 result = 0;
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u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
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@@ -81,15 +81,16 @@ u32 kw_sdram_bs(enum memory_bank bank)
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return result;
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}
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-void kw_sdram_size_adjust(enum memory_bank bank)
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+void mvebu_sdram_size_adjust(enum memory_bank bank)
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{
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u32 size;
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/* probe currently equipped RAM size */
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- size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank));
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+ size = get_ram_size((void *)mvebu_sdram_bar(bank),
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+ mvebu_sdram_bs(bank));
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/* adjust SDRAM window size accordingly */
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- kw_sdram_bs_set(bank, size);
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+ mvebu_sdram_bs_set(bank, size);
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}
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#ifndef CONFIG_SYS_BOARD_DRAM_INIT
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@@ -99,8 +100,8 @@ int dram_init(void)
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gd->ram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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- gd->bd->bi_dram[i].start = kw_sdram_bar(i);
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- gd->bd->bi_dram[i].size = kw_sdram_bs(i);
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+ gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
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+ gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
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/*
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* It is assumed that all memory banks are consecutive
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* and without gaps.
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