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@@ -0,0 +1,377 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (C) 2018 Kontron Electronics GmbH
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+ */
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+
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+#include <asm/arch/clock.h>
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+#include <asm/arch/crm_regs.h>
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+#include <asm/arch/mx6-pins.h>
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+#include <asm/arch/sys_proto.h>
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+#include <asm/global_data.h>
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+#include <asm/gpio.h>
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+#include <asm/io.h>
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+#include <asm/mach-imx/iomux-v3.h>
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+#include <fsl_esdhc_imx.h>
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+#include <init.h>
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+#include <linux/delay.h>
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+#include <linux/sizes.h>
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+#include <linux/errno.h>
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+#include <mmc.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+enum {
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+ BOARD_TYPE_KTN_N631X = 1,
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+ BOARD_TYPE_KTN_N641X,
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+ BOARD_TYPE_MAX
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+};
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+
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+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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+
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+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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+
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+#define USDHC_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
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+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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+
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+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
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+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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+
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+#include <spl.h>
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+#include <asm/arch/mx6-ddr.h>
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+
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+static iomux_v3_cfg_t const usdhc1_pads[] = {
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+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+
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+ /* CD */
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+ MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
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+};
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+
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+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
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+
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+static iomux_v3_cfg_t const usdhc2_pads[] = {
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+ MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ /* RST */
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+ MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+};
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+
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+#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
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+
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+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
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+ {USDHC1_BASE_ADDR, 0, 4},
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+ {USDHC2_BASE_ADDR, 0, 4},
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+};
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+
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+int board_mmc_getcd(struct mmc *mmc)
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+{
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+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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+ int ret = 0;
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+
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+ switch (cfg->esdhc_base) {
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+ case USDHC1_BASE_ADDR:
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+ ret = !gpio_get_value(USDHC1_CD_GPIO);
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+ break;
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+ case USDHC2_BASE_ADDR:
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+ // This SDHC interface does not use a CD pin
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+ ret = 1;
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+ break;
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+ }
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+
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+ return ret;
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+}
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+
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+int board_mmc_init(struct bd_info *bis)
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+{
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+ int i, ret;
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+
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+ /*
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+ * According to the board_mmc_init() the following map is done:
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+ * (U-boot device node) (Physical Port)
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+ * mmc0 USDHC1
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+ * mmc1 USDHC2
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+ */
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+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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+ switch (i) {
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+ case 0:
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+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
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+ gpio_direction_input(USDHC1_CD_GPIO);
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+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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+ break;
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+ case 1:
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+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
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+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
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+ udelay(500);
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+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
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+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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+ break;
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+ default:
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+ printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n",
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+ i + 1);
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+ return -EINVAL;
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+ }
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+
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+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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+ if (ret) {
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+ printf("Warning: failed to initialize mmc dev %d\n", i);
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+ return ret;
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+ }
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+ }
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+ return 0;
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+}
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+
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+iomux_v3_cfg_t const ecspi2_pads[] = {
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+ MX6_PAD_CSI_DATA00__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
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+ MX6_PAD_CSI_DATA02__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
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+ MX6_PAD_CSI_DATA03__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
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+ MX6_PAD_CSI_DATA01__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+};
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+
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+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
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+{
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+ return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
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+ ? (IMX_GPIO_NR(4, 22)) : -1;
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+}
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+
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+static void setup_spi(void)
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+{
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+ gpio_request(IMX_GPIO_NR(4, 22), "spi2_cs0");
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+ gpio_direction_output(IMX_GPIO_NR(4, 22), 1);
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+ imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
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+
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+ enable_spi_clk(true, 1);
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+}
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+
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+static iomux_v3_cfg_t const uart4_pads[] = {
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+ MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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+ MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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+};
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+
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+static void setup_iomux_uart(void)
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+{
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+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
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+}
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+
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+// DDR 256MB (Hynix H5TQ2G63DFR)
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+static struct mx6_ddr3_cfg mem_256M_ddr = {
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+ .mem_speed = 800,
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+ .density = 2,
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+ .width = 16,
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+ .banks = 8,
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+ .rowaddr = 14,
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+ .coladdr = 10,
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+ .pagesz = 2,
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+ .trcd = 1350,
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+ .trcmin = 4950,
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+ .trasmin = 3600,
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+};
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+
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+static struct mx6_mmdc_calibration mx6_mmcd_256M_calib = {
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+ .p0_mpwldectrl0 = 0x00000000,
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+ .p0_mpdgctrl0 = 0x01340134,
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+ .p0_mprddlctl = 0x40405052,
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+ .p0_mpwrdlctl = 0x40404E48,
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+};
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+
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+// DDR 512MB (Hynix H5TQ4G63DFR)
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+static struct mx6_ddr3_cfg mem_512M_ddr = {
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+ .mem_speed = 800,
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+ .density = 4,
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+ .width = 16,
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+ .banks = 8,
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+ .rowaddr = 15,
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+ .coladdr = 10,
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+ .pagesz = 2,
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+ .trcd = 1350,
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+ .trcmin = 4950,
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+ .trasmin = 3600,
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+};
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+
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+static struct mx6_mmdc_calibration mx6_mmcd_512M_calib = {
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+ .p0_mpwldectrl0 = 0x00000000,
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+ .p0_mpdgctrl0 = 0X01440144,
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+ .p0_mprddlctl = 0x40405454,
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+ .p0_mpwrdlctl = 0x40404E4C,
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+};
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+
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+// Common DDR parameters (256MB and 512MB)
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+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
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+ .grp_addds = 0x00000028,
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+ .grp_ddrmode_ctl = 0x00020000,
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+ .grp_b0ds = 0x00000028,
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+ .grp_ctlds = 0x00000028,
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+ .grp_b1ds = 0x00000028,
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+ .grp_ddrpke = 0x00000000,
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+ .grp_ddrmode = 0x00020000,
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+ .grp_ddr_type = 0x000c0000,
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+};
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+
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+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
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+ .dram_dqm0 = 0x00000028,
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+ .dram_dqm1 = 0x00000028,
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+ .dram_ras = 0x00000028,
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+ .dram_cas = 0x00000028,
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+ .dram_odt0 = 0x00000028,
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+ .dram_odt1 = 0x00000028,
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+ .dram_sdba2 = 0x00000000,
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+ .dram_sdclk_0 = 0x00000028,
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+ .dram_sdqs0 = 0x00000028,
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+ .dram_sdqs1 = 0x00000028,
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+ .dram_reset = 0x00000028,
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+};
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+
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+struct mx6_ddr_sysinfo ddr_sysinfo = {
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+ .dsize = 0,
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+ .cs_density = 20,
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+ .ncs = 1,
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+ .cs1_mirror = 0,
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+ .rtt_wr = 2,
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+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
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+ .walat = 1, /* Write additional latency */
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+ .ralat = 5, /* Read additional latency */
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+ .mif3_mode = 3, /* Command prediction working mode */
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+ .bi_on = 1, /* Bank interleaving enabled */
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+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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+ .ddr_type = DDR_TYPE_DDR3,
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+ .refsel = 0, /* Refresh cycles at 64KHz */
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+ .refr = 1, /* 2 refresh commands per refresh cycle */
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+};
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+
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+static void ccgr_init(void)
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+{
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+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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+
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+ writel(0xFFFFFFFF, &ccm->CCGR0);
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+ writel(0xFFFFFFFF, &ccm->CCGR1);
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+ writel(0xFFFFFFFF, &ccm->CCGR2);
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+ writel(0xFFFFFFFF, &ccm->CCGR3);
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+ writel(0xFFFFFFFF, &ccm->CCGR4);
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+ writel(0xFFFFFFFF, &ccm->CCGR5);
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+ writel(0xFFFFFFFF, &ccm->CCGR6);
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+ writel(0xFFFFFFFF, &ccm->CCGR7);
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+}
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+
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+static void spl_dram_init(void)
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+{
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+ unsigned int size;
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+
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+ // DDR RAM connection is always 16 bit wide. Init IOs.
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+ mx6ul_dram_iocfg(16, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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+
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+ // Try to detect the 512MB RAM chip first.
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+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_512M_calib, &mem_512M_ddr);
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+
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+ // Get the available RAM size
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+ size = get_ram_size((void *)PHYS_SDRAM, SZ_512M);
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+
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+ gd->ram_size = size;
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+
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+ if (size == SZ_512M) {
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+ // 512MB RAM was detected
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+ return;
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+ } else if (size == SZ_256M) {
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+ // 256MB RAM was detected, use correct config and calibration
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+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_256M_calib, &mem_256M_ddr);
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+ } else {
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+ printf("Invalid DDR RAM size detected: %x\n", size);
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+ }
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+}
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+
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+static int do_board_detect(void)
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+{
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+ if (is_mx6ul())
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+ gd->board_type = BOARD_TYPE_KTN_N631X;
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+ else if (is_mx6ull())
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+ gd->board_type = BOARD_TYPE_KTN_N641X;
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+
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+ printf("Kontron SL i.MX6UL%s (N6%s1x) module, %lu MB RAM detected\n",
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+ is_mx6ull() ? "L" : "", is_mx6ull() ? "4" : "3", gd->ram_size / SZ_1M);
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+
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+ return 0;
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+}
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+
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+void board_init_f(ulong dummy)
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+{
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+ ccgr_init();
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+
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+ /* setup AIPS and disable watchdog */
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+ arch_cpu_init();
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+
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+ /* iomux and setup of UART and SPI */
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+ board_early_init_f();
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+
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+ /* setup GP timer */
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+ timer_init();
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+
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+ /* UART clocks enabled and gd valid - init serial console */
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+ preloader_console_init();
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+
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+ /* DDR initialization */
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+ spl_dram_init();
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+
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+ /* Clear the BSS. */
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+ memset(__bss_start, 0, __bss_end - __bss_start);
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+
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+ /* Detect the board type */
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+ do_board_detect();
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+
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+ /* load/boot image from boot device */
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+ board_init_r(NULL, 0);
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+}
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+
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+void board_boot_order(u32 *spl_boot_list)
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+{
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+ u32 bootdev = spl_boot_device();
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+
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+ /*
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+ * The default boot fuse settings use the SD card (MMC1) as primary
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+ * boot device, but allow SPI NOR as a fallback boot device.
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+ * We can't detect the fallback case and spl_boot_device() will return
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+ * BOOT_DEVICE_MMC1 despite the actual boot device being SPI NOR.
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+ * Therefore we try to load U-Boot proper vom SPI NOR after loading
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+ * from MMC has failed.
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+ */
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+ spl_boot_list[0] = bootdev;
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+
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+ switch (bootdev) {
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+ case BOOT_DEVICE_MMC1:
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+ case BOOT_DEVICE_MMC2:
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+ spl_boot_list[1] = BOOT_DEVICE_SPI;
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+ break;
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+ }
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+}
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+
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+int board_early_init_f(void)
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+{
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+ setup_iomux_uart();
|
|
|
+ setup_spi();
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+int board_fit_config_name_match(const char *name)
|
|
|
+{
|
|
|
+ if (gd->board_type == BOARD_TYPE_KTN_N631X && is_mx6ul() &&
|
|
|
+ !strcmp(name, "imx6ul-kontron-n631x-s"))
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ if (gd->board_type == BOARD_TYPE_KTN_N641X && is_mx6ull() &&
|
|
|
+ !strcmp(name, "imx6ull-kontron-n641x-s"))
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ return -1;
|
|
|
+}
|