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@@ -6,14 +6,16 @@
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#ifndef _SEQUENCER_H_
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#define _SEQUENCER_H_
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-#define RW_MGR_NUM_DM_PER_WRITE_GROUP (rwcfg->mem_data_mask_width \
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- / rwcfg->mem_if_write_dqs_width)
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-#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (rwcfg->true_mem_data_mask_width \
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- / rwcfg->mem_if_write_dqs_width)
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+#define RW_MGR_NUM_DM_PER_WRITE_GROUP (seq->rwcfg->mem_data_mask_width \
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+ / seq->rwcfg->mem_if_write_dqs_width)
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+#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP ( \
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+ seq->rwcfg->true_mem_data_mask_width \
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+ / seq->rwcfg->mem_if_write_dqs_width)
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-#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (rwcfg->mem_if_read_dqs_width \
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- / rwcfg->mem_if_write_dqs_width)
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-#define NUM_RANKS_PER_SHADOW_REG (rwcfg->mem_number_of_ranks / NUM_SHADOW_REGS)
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+#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (seq->rwcfg->mem_if_read_dqs_width \
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+ / seq->rwcfg->mem_if_write_dqs_width)
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+#define NUM_RANKS_PER_SHADOW_REG (seq->rwcfg->mem_number_of_ranks \
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+ / NUM_SHADOW_REGS)
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#define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0
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#define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400
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@@ -256,6 +258,26 @@ struct socfpga_sdr {
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u8 _align9[0xea4];
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};
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+struct socfpga_sdrseq {
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+ const struct socfpga_sdram_rw_mgr_config *rwcfg;
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+ const struct socfpga_sdram_io_config *iocfg;
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+ const struct socfpga_sdram_misc_config *misccfg;
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+ /* calibration steps requested by the rtl */
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+ u16 dyn_calib_steps;
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+ /*
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+ * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
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+ * instead of static, we use boolean logic to select between
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+ * non-skip and skip values
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+ *
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+ * The mask is set to include all bits when not-skipping, but is
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+ * zero when skipping
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+ */
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+
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+ u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
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+ struct gbl_type gbl;
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+ struct param_type param;
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+};
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+
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int sdram_calibration_full(struct socfpga_sdr *sdr);
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#endif /* _SEQUENCER_H_ */
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