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@@ -476,6 +476,13 @@ static void setup_display_bx50v3(void)
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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+ /* When a reset/reboot is performed the display power needs to be turned
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+ * off for atleast 500ms. The boot time is ~300ms, we need to wait for
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+ * an additional 200ms here. Unfortunately we use external PMIC for
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+ * doing the reset, so can not differentiate between POR vs soft reset
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+ */
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+ mdelay(200);
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+
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/* IPU1 DI0 clock is 480/7 = 68.5 MHz */
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setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
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